| Age | Commit message (Collapse) | Author | Files | Lines |
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FEAT_Debugv8p9 adds a new MDSELR_EL1 register to select between banks of
breakpoints and watchpoints. Accesses to MDSELR_EL1 from EL2 and below trap to
EL3 unless MDCR_EL3.EBWE is set.
Enable access to MDSELR_EL1 when it is implemented.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Allow lower ELs to access the registers associated with the Permission
Indirection Extension.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Allow access the TCR2_ELx register which provides extended translation
controls similar to TCR_ELx.
Initialise these registers to a value of 0.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Inserting arbitrary paths in a linker script verbatim can be
problematic, even if they don't contain whitespaces, as ld has a
special interpretation for certain special characters (such as @).
Fix this by quoting all user-provided paths in model.lds.S using the
preprocessor.
Signed-off-by: Kevin Brodsky <kevin.brodsky@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Older Arm Fast Models (AEM < RevC) had a base frequency of 24 MHz. but
the RevC base models use 100 MHz. There is not a robust method of
determining the configured base frequency at runtime, so update
COUNTER_FREQ to be 100 MHz.
Signed-off-by: Peter Hoyes <Peter.Hoyes@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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To enable the full AArch64 ISA support in streaming SVE mode, we need to
set bit 31 in the SMCR_EL3 system register. However ORing (1 << 31) into
an unsigned long variable will lead to all upper 32 bits becoming 1,
which is not what we want. We are just saved by those bits being RES0,
at least for now.
Explicitly use an unsigned base for the shift, to avoid the sign
extension.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Mark: use 'BIT(31)' rather than '(1U << 31)']
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20221004145152.3020464-1-andre.przywara@arm.com/
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When we are trying to find the array index for a given MPIDR, we check
that we don't overrun the array boundary, by comparing against NR_CPUS.
However the resulting conditional branch should also fire when we reach
the exact number of elements, since it's all 0 based.
Change the comparison to be '>=' instead of just '>', to only allow
array indicies 0 .. (NR_CPUS - 1).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Allow EL2 to access the HCRX_EL2 register which provides hypervisor
controls similarly to HCR_EL2.
Signed-off-by: Kristina Martsenko <kristina.martsenko@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Allow lower ELs to use SME when booted on a system that support it. This
requires us to set two new bits, one in each of SCR_EL3 and CPTR_EL3, set
the maximum vector length in a similar fashion to SVE and if the optional
FA64 feature is present then set another feature bit in the new SMCR
register.
Signed-off-by: Mark Brown <broonie@kernel.org>
[Mark R: use BIT() for ID_AA64SMFR0_EL1_FA64, sort ID_AA64PFR1_EL1 fields]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220201172132.2399026-2-broonie@kernel.org
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The enumeration and configuration algorithm for SVE vector lengths is not
100% obvious so add a comment explaining what's going on in case someone
looks at this code as a reference. If this is ever used on hardware with
asymmetric vector lengths we will need to handle this differently to meet
Linux's boot requirements but this is not a present issue and such hardware
would be fairly surprising.
Signed-off-by: Mark Brown <broonie@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Link: https://lore.kernel.org/r/20220201172132.2399026-1-broonie@kernel.org
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QARMA3 is relaxed version of the QARMA5 algorithm which expected to
reduce the latency of calculation while still delivering a suitable
level of security.
Support for QARMA3 can be discovered via ID_AA64ISAR2_EL1 [1]
APA3, bits [15:12] Indicates whether the QARMA3 algorithm is
implemented in the PE for address authentication in
AArch64 state.
GPA3, bits [11:8] Indicates whether the QARMA3 algorithm is
implemented in the PE for generic code
authentication in AArch64 state.
[1] https://developer.arm.com/documentation/ddi0601/2021-12/AArch64-Registers/ID-AA64ISAR2-EL1--AArch64-Instruction-Set-Attribute-Register-2?lang=en
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When we add the PSCI nodes to the provided DTB, we use dtc to de-compile
the blob first, then re-compile it with our nodes and properties added.
In our input DTB the proper phandle references have already been lost,
all we see in the DTB is phandle properties in the target node, and some
numbers in the clocks and gpios properties:
===========
clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x16e3600>;
clock-output-names = "v2m:clk24mhz";
-> phandle = <0x05>;
};
...
serial@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x90000 0x1000>;
interrupts = <0x05>;
-> clocks = <0x05 0x05>;
clock-names = "uartclk", "apb_pclk";
};
===========
dtc warns that those numbers might be wrong:
=========
<stdin>:177.6-27: Warning (clocks_property):
/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000:
clocks: cell 0 is not a phandle reference
....
=========
The proper solution would be to use references (&v2m_clk24mhz) instead,
as there are in the source .dts file, but we don't have that information
anymore, and cannot easily recover it.
To avoid the lengthy list of warnings, just drop those checks from the
dtc compilation run. This disables more checks than we want or need, but
we somewhat trust in the original DTB to be sane, so that should be
fine.
Since those warning options are not supported by older dtc versions,
introduce a compatiblity check before using them.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Now that the start_el3 and start_no_el3 labels point at the same place,
unify them into a start_bootmethod label and update callers.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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We currently initialize the bootmethod late, in assembly code. This
requires us to maintain the el3/no_el3 distintion late into the boot
process, and means we cannot produce any helpful diagnostic when booted
at an unexpected exception level.
Rework things so that we initialize the bootmethod early, with a warning
when things are wrong. The el3/no_el3 distinction is now irrelevant to
the bootmethod code, and can be removed in subsequent patches.
When a boot-wrapper configured for PSCI is entered at EL2, a warning is
looged to the serial console as:
| Boot-wrapper v0.2
| Entered at EL2
| Memory layout:
| [0000000080000000..0000000080001f90] => boot-wrapper
| [000000008000fff8..0000000080010000] => mbox
| [0000000080200000..00000000822af200] => kernel
| [0000000088000000..0000000088002857] => dtb
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| WARNING: PSCI could not be initialized. Boot may fail
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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To make it easier to debug boot failures, log the location of memory
objects at boot time.
This is logged to the serial console as:
| Boot-wrapper v0.2
| Entered at EL3
| Memory layout:
| [0000000080000000..0000000080001f90] => boot-wrapper
| [000000008000fff8..0000000080010000] => mbox
| [0000000080200000..00000000822af200] => kernel
| [0000000088000000..0000000088002857] => dtb
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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The majority of state that we initialize at Secure PL1 is necessary for
code at lower PLs to function, but isnt' necessary for the boot-wrapper
itself. Given that, it would be better to write this in C where it can
be written mode clearly, and where it will be possible to add
logging/debug logic.
This patch migrates the AArch32 Secure PL1 initialization to C.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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The majority of state that we initialize at EL3 is necessary for code at
lower ELs to function, but isnt' necessary for the boot-wrapper itself.
Given that, it would be better to write this in C where it can be
written mode clearly, and where it will be possible to add logging/debug
logic.
This patch migrates the AArch64 EL3 initialization to C.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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When something goes wrong within the boot-wrapper, it can be very
helpful to know where we started from. Add an arch_announce() function
to log this early in the boot process. More information can be added
here in future.
This is logged ot the serial console as:
| Boot-wrapper v0.2
| Entered at EL3
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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In init_platform() we initialize a UART and announce the presence of the
bootwrapper to the world. We do this relatively late in the boot-flow,
and prior to this will silently ignore errors (e.g. in gic_secure_init).
To make it possible to provide improved diagnostics, and to allow us to
move more initialization into C, this patch reworks the init code to
call a C function earlier, where we can announce the presence of the
boot-wrapper and perform other initialization.
In subsequent patches this will be expanded with more CPU
initialization.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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The SCTLR_ELx registers contain fields which are UNKNOWN or
IMPLEMENTATION DEFINED out of reset. This includes SCTLR_ELx.EE, which
defines the endianness of memory accesses (e.g. reads from literal
pools). Due to this, portions of boot-wrapper code are not guaranteed
to work correctly.
Rework the startup code to explicitly initialize SCTLR_ELx for the
exception level the boot-wrapper was entered at. When entered at EL2
it's necessary to first initialise HCR_EL2.E2H as this affects the RESx
behaviour of bits in SCTLR_EL2, and also aliases SCTLR_EL1 to SCTLR_EL2,
which would break the initialization performed in jump_kernel.
As we plan to eventually support the highest implemented EL being any of
EL3/EL2/EL1, code is added to handle all of these exception levels, even
though we do not currently support starting at EL1.
We'll initialize other registers in subsequent patches.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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In subsequent patches we'll need to load 64-bit values into GPRs before
the CPU is in a known endianness, where we cannot use literal pools.
In preparation for that, this patch adds a new `mov_64` macro to load a
64-bit value into a GPR using a sequence of MOV and MOVKs, which will
function the same regardless of the CPU's endianness.
At the same time, move the `cpuid` macro to use `mov_64` internally.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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We open code the use of mrc/mcr for specific registers, which is
somewhat tedious. Add macros to do this generically, along with a helper
to extract a specific register field. Existing C usage is converted to
the new helpers, and register definitions moved to a common location.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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We open code the use of mrs/msr for specific registers, which is
somewhat tedious. Add macros to do this generically, along with a helper
to extract a specific register field. Existing C usage is converted to
the new helpers, and register definitions moved to a common location.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Arm architectural documentation typically defines bit-fields as
`[msb,lsb]` and single-bit fields as `[bit]`. For clarity it would be
helpful if we could define fields in the same way.
Add helpers so that we can do so, along with helper to extract/insert
bit-field values.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Currently the boot-wrapper only supports some combinations of exception
levels, with other combinations not being supported.
While we generally expect the boot-wrapper to be entered at the highest
implemented exception level, the AArch32 boot-wrapper has a comment
implying it supports being entered with something else owning EL3. As
this would require such EL3 firmware to always be in sync with the
boot-wrapper's requirements, which change over time, we don't actually
support such a configuration.
Some CPU state (such as CNTFRQ/CNTFRQ_EL0) needs to be initialized at
the highest implemented exception level, but today the boot-wrapper only
does so when entered at EL3 / Secure-PL1. Thus, today the only
completely supported configurations are EL3 / Secure-PL1, and entering
in other configurations is not entirely supported.
The aarch64 `jump_kernel` function always writes to SCTLR_EL2, which is
UNDEFINED at EL1. Hence, the aarch64 boot-wrapper does not support being
entered at EL1.
The aarch32 code assumes that any non-hyp mode is Secure PL1, and
attempt to switch to monitor mode. If entered on a system without the
security extensions, where the highest privileged mode is Non-secure
PL1, this will not work. Hence the aarch32 boot-wrapper does not support
being entered at Non-secure PL1.
Actually supporting all of these configurations requires restructuring
much of the boot-wrapper. For now, document the supported configurations
in each architecture's boot.S, and remove the misleading comment from
arch/aarch32/boot.S. Subsequent patches will improve the support and add
support for additional configurations.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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Bits [31:0] of the AArch64 SCTLR_EL1 register are architecturally mapped
to bits [31:0] of the AArch32 SCTLR register. This means that any
individual bit always has the same value across the two registers.
Across the two registers, the same bit may have distinct meanings,
distinct RESx behaviour, and distinct reset behaviour. For example,
SCTLR_EL1[28] is nTLSMD, which we wich to initialize to 0b1, whereas
SCTLR[28] is TRE, which we wish to initialize to 0b0.
To avoid setting bits which we did not intend to, and in preparation for
configuring more AArch64 RES1 bits, this patch decouples the
SCTLR_EL1_KERNEL value used for AArch32 kernels from the SCTLR_EL1_RES1
definitions such that is does not inherit AArch64 SCTLR_EL1 bits which
would be problematic in the AArch32 SCTLR. For now we open-code a copy
of the bits defined in arch/aarch64/include/asm/cpu.h.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
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The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are
RAZ/WI, likely so that in future these can be used to extend LEN without
complicating the probing of the maximum available vector length.
Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN
field and the RAZ/WI bits.
To match the architecture as documented, reduce this down to 0xf, only
covering the bits currently allocated to the LEN field. We can extend
this in future if the LEN field is widened.
As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is
used as a value rather than as a bit mask.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Brown <broonie@kernel.org>
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As Vladimir Murzin reports in:
https://lore.kernel.org/linux-arm-kernel/706471d8-a0fd-35fb-4fa0-380bfb1b78e7@arm.com/
Older version of dtc don't support the options to suprress the warnings,
and so where people are stuck with said versions of dtc, using those
options results in a build failure rather than an ignoreable build
warning.
For now, let's revert the warning suppression. In future we can try to
do something smarter.
This reverts commit 1044c77062573985f7c994c3b6cef5695f57e955.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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MDCR_EL3.SBRBE resets to an UNKNOWN value. Configure it to allow the BRBE
buffer usage and direct register access in the non-secure world. But just
before that, check AA64DFR0_EL1.BRBE and make sure BRBE is implemented. We
still continue to reset MDCR_EL3 register to zero with the exception of
MDCR_EL3.NSPB, MDCR_EL3.NSTB and MDCR_EL3.SBRBE.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Our GCC invocation does not provide many parameters, which lets the
toolchain fill in its own default setup.
In case of a native build or when using a full-featured cross-compiler,
this probably means Linux userland, which is not what we want for a
bare-metal application like boot-wrapper.
Tell the compiler to forget about those standard settings, and only use
what we explicitly ask for. In particular that means to not use toolchain
provided libraries, since they might pull in more code than we want, and
might not run well in the boot-wrapper environment.
Disable the stack protector, as this relies on support code, e.g.
a __stack_chk_guard variable and __stack_chk_fail function, which the
boot-wrapper does not implement.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When we add the PSCI nodes to the provided DTB, we use dtc to de-compile
the blob first, then re-compile it with our nodes and properties added.
In our input DTB the proper phandle references have already been lost,
all we see in the DTB is phandle properties in the target node, and some
numbers in the clocks and gpios properties:
===========
clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0x00>;
clock-frequency = <0x16e3600>;
clock-output-names = "v2m:clk24mhz";
-> phandle = <0x05>;
};
...
serial@90000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0x90000 0x1000>;
interrupts = <0x05>;
-> clocks = <0x05 0x05>;
clock-names = "uartclk", "apb_pclk";
};
===========
dtc warns that those numbers might be wrong:
=========
<stdin>:177.6-27: Warning (clocks_property):
/bus@8000000/motherboard-bus@8000000/iofpga-bus@300000000/serial@90000:
clocks: cell 0 is not a phandle reference
....
=========
The proper solution would be to use references (&v2m_clk24mhz) instead,
as there are in the source .dts file, but we don't have that information
anymore, and cannot easily recover it.
To avoid the lengthy list of warnings, just drop those checks from the
dtc compilation run. This disables more checks than we want or need, but
we somewhat trust in the original DTB to be sane, so that should be
fine.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When checking for the pointer authentication feature, we actually look
for *four* different CPUID feature sets.
Add a comment to make it more obvious that the 0xff is not a typo.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The arm64 Linux kernel dropped support for the "earlyprintk" command line
parameter a long time ago[1], instead it uses the earlycon parameter
now.
Replace earlyprintk with earlycon on the default command line, to see
early kernel output.
Ideally we would just say "earlycon" (without specifying an MMIO
address), but this relies on the stdout-path property in the /chosen
node, which the model DTs do not carry.
[1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=8ef0ed95ee04
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The DTS files for Arm Ltd. boards and the fastmodel have long been moved
into the arm/ subdirectory of the arm64 kernel tree's DT folder.
Adjust the default path to make this build out of the box.
Also change the default DTB to the more modern FVP RevC model on the
way.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When the boot-wrapper was originally conceived, PSCI was a rather new
feature, so support in contemporary kernels wasn't guaranteed. The
boot-wrapper consequently defaulted to not using PSCI.
Fortunately the times have changed, and most people expect PSCI these
days, so let's enable PSCI by default.
We keep the --enable-psci/--disable-psci configure switch, so it can be
still turned off if needed.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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At the moment we build the boot-wrapper with the default toolchain
settings, which has issues if that is a toolchain targeted to Linux
userland, for instance. Since boot-wrapper is rather simple, we get away
with this, *mostly*, but there is at least one case where this breaks:
Many distributions enable PIE builds by default when building GCC, so by
just calling "gcc" we build the .o files for PIE (although we don't link
them accordingly, since we use "ld" directly).
When we moved the PSCI code from assembly to C, we also introduced
global variables, which a PIE enabled GCC will put into a .got section
(global offset table), to be able to easily relocate them at runtime
(if needed). This section happens to be outside of the memory region
we reserve, so can (and will be) overwritten by Linux at some point.
Doing PSCI calls afterwards does not end well then. "memtest=1" is one
way to trigger this.
To avoid the (in our case pointless) creation of the GOT, we specify
-fno-pic and -fno-pie, to override any potential toolchain default.
This fixes boot-wrapper builds on many distro compilers, for instance
as provided by Ubuntu and Arch Linux.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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To avoid any confusuion between the CNTFRQ/CNTFRQ_EL0 register and the
vallue it will be progrmamed with, rename the `CNTFRQ` constant to
`COUNTER_FREQ.
In future patches this will allow us to use `CNTFRQ` as a macro for the
AArch32 CP15 register encoding.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
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Our *_RESET constants are used to initalize state for the kernel rather
than the bootwrapper itself, so for clarity we should use a *_KERNEL
suffix rather than a _RESET suffix.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
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There's no need to perform an RMW sequence to initialize ICC_SRE_EL3, as
there are no bits that we need to preserve, and generally we should
reset registers to specific values such that RESx bits aren't configured
to UNKNOWN values that could be problematic in future architecture
versions.
Instead, let's initialize ICC_SRE_EL3 with a constant value. Since the
`DIB` and `DFB` fields are RAO/WI in some configurations and we have no
reason to initialize these to 0, we always initialize these to 1, in
addition to `SRE` and `SRE_Enable`.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
Cc: Alexandru Elisei <alexandru.elisei@arm.com>
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If we're lucky enough to have been booted into secure PL1, we can switch
to monitor mode with an exception return rather than an SMC call, which
avoids the need for boot-time vectors.
Note that while all Secure PL1 register state is accessible in Secure
SVC mode, we must switch to Monitor mode before we set SCR.NS=1.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
|
|
We removed the Set/Way cache maintenance in commit:
864182b26c20a39d ("Remove cache maintenance")
... but forgot to remove the arch helpers which are now unused.
Remove the unused helpers.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Marc Zyngier <maz@kernel.org>
|
|
In commit:
fcb8a82b91a39ce2 ("Cleanup `.globl` usage")
... we forgot to include <linkage.h> in asm/stack.S, and consequently
broke the build as the assembler has no idea what ASM_FUNC() and
ASM_DATA() mean.
Add the missing include.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
FEAT_PMUv1p2 adds a new register, PMSNEVFR_EL1, and a new MDCR_EL3 trap bit
for it, EnPMSN. Set the bit to 1 to allow lower exception levels direct
access to the register.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
[Mark: use ORR (Imm) to enable SPE, use 1f label, re-order comment]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
If the implemnentation supports ID_AA64MMFR0_EL1.ECV==2,
set SCR_EL3.ECVEn to allow EL2 access to CNTPOFF_EL2.
Signed-off-by: Marc Zyngier <maz@kernel.org>
[Mark: read id_aa64mmfr0_el1 separately, s/bne/b.lt/]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
The top-level directory is getting increasingly cluttered. For clarity
let's move the common source files into their own directory. At the same
time let's clean up the way we generate object lists so that it's
consistent for arch/common objects, and doesn't require special casing
each optional object.
Note that we also need to create a common/ directory for out-of-tree
builds.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
In `spin.h` we have function prototypes provided by `boot.c`. For
clarity, let's align the naming.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
For clarity, align aarch32 with aarch64, sending unexpected CPUs to an
`err_invalid_id` loop rather than `_spin_dead`.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
In some places we use `ENTRY()` to mark an assembly function, whereas in
others we just use `.globl`. Where we use `.globl` for functions or
data, we don't keep this close to the actual definition.
Further, `ENTRY()` is a keyword in linker script with a different
meaning, and so it would be nicer if we didn't use the same term in the
assembly files.
This patch adds `ASM_FUNC()` and `ASM_DATA()` markers, and uses them
consistently throughout the codebase.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
In some places we assume that the cpu with MPIDR_EL1.Aff* == 0 is the
same as logical CPU 0. While this is almost certainly true, it would be
best to consistently use the logical ID.
Add a new `this_cpu_logical_id()` helper, and use this in preference to
checking the MPIDR_EL1.Aff* bits directly.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
The boot-wrapper assumes that an AArch64 kernel's text offset is 0x80000
rather than reading the `text_offset` field from the Image header as the
documentation says it should.
Add a script to figure this out during the build process. As with FDT.pm
the parsing of the Image (and common logic associated with this) is
factored into a module that we may use in more scripts in future.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
The top-level directory is getting increasingly cluttered. For clarity
let's move the scripts into their own directory.
There should be no functional change as a result of this patch.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
There's no reason we need to test the PSCI function IDs in assembly;
move this to C so that it can be shared across AArch64 and AArch32. At
the same time, limit the PSCI_CPU_ON FIDs to match the register width of
the kernel.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
For models, we assume that out-of-reset caches are invalid and no cache
maintenance is required.
We added cache maintenance to the boot-wrapper in commit:
28ec269a22c8dc14 ("Add code to clean and invalidate caches")
... because the boot-wrapper would transiently use cacheable mappings,
and could allocate into caches. As we were using Set/Way operations, we
were on somewhat shaky ground (e.g. due to system-level caches, or
dirty line migration). Further, we never took FEAT_CCIDX into account,
and so would not necessarily invalidate all potential levels of cache
However, since commit:
0bb7b2545582accf ("Remove MMU identity map setup")
... we no longer enable the MMU within the boot-wrapper, and so no
longer have any reason to perform cache maintenance.
This patch removes the redundant and incomplete cache maintenance.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
Assembly files generally assume that .text is word-aligned, and don't
explciitly align the .text section. However, if we mix .text with data
sections at link time, we can output .text sections at less than word
alignment, resulting in boot-time hangs that are painful to debug.
Output all .text sections before .data sections to minimize this risk.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
We accidentally placed the `.align` directive after the `kernel_address`
label, meaning that the label itself isn't necessarily aligned. Place
the `.align` directive first to ensure this.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
|
|
As the comment states, the frequency of the Generic Timer in the model
is 24 MHz, and not the currently used 0x1800000, which is actually
25,165,824 (~5% higher).
Use the proper number, and not something power-of-2 based.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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|
An auto-detect switch is added to make it an option to enable/disable
'arm,vexpress-sysreg', because not all platforms support this feature.
But the auto-detection generates the side-effect of printing a warning
message about the missing node:
No matching devices found at ./findbase.pl line 37.
In this case, to drop the warning message, add "2> /dev/null" at the
end of the findbase.pl call.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Since we already have set up a stack above, there is no need to do it
again.
Also, in fact it's a bug: setup_stack expects the logical CPU ID in
w0, and here we always call it with w0 being 1.
Signed-off-by: Jaxson Han <jaxson.han@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
SCR_EL3.ATA must be set so that software can access the allocation
(in-memory) MTE tags.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
We have no intention of handling FGT traps to EL3, so let EL2
play with the feature directly.
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
MDCR_EL3.NSTB resets to an UNKNOWN value. Configure it to allow the trace
buffer to use non-secure memory and to permit direct register accesses from
the non-secure world. Before that, just check AA64DFR0_EL1.TraceBuffer and
make sure TRBE is implemented. We still continue to reset MDCR_EL3 register
to zero with the exception of MDCR_EL3.NSPB and MDCR_EL3.NSTB.
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
MDCR_EL3.NSPB resets to an UNKNOWN value. Configure it to allow the
profiling buffer to use non-secure memory and to permit direct register
accesses from the non-secure world.
So far, we haven't programmed MDCR_EL3 explicitly even though there are
other fields which reset to an UNKNOWN value. The majority of those, when
cleared, allow lower exception levels to use the features they control; for
the other fields we don't have support yet. Reset the register to zero
with the exception of MDCR_EL3.NSPB.
Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
By default, TME is not available to exception levels below EL3, so
enable it in SCR_EL3 if we detect that it is implemented.
Signed-off-by: Will Deacon <will@kernel.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
If we have a GICv3.1-capable system, configure the EPPI/ESPI ranges
to be accessible from the non-secure world.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
By default, use of pointer authentication functionality (either
instructions or access to keys) will trap to EL3.
This patch programs SCR_EL3 to enable pointer authentication for lower
exception levels.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Adding AArch32 support to the boot-wrapper changed the source layout and
broke out-of-tree build. This patch allows to put all generated files
into a separate directory again, and build multiple images in parallel:
mkdir build/ && cd build/
~/src/boot-wrapper-aarch64/configure ...
make
Make attempts to output object files into build/arch/aarchXX/, but fails
because that folder doesn't exist in the build directory. Add mkdir as
prerequisite for any *.o target in the arch folder.
So that Make doesn't confuse the destination folder with the source,
override VPATH to only affect .S and .c sources.
And set $(ARCH_SRC) as order-only-prerequisite (after a '|'). Otherwise
Make would rebuild all objects whenever the timestamp of $(ARCH_SRC)
changes, which is every time an object is rebuilt...
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
We hard code TEXT_LIMIT to check for image overflow, assuming the memory
is always at 0x80000000, which may not always be true. Instead use the
offset from the PHYS_OFFSET, which is actually dependent on the DT.
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
By default, SVE will trap to EL3. We also want to make sure that
lower ELs have access to the full SVE vector length before dropping
down.
This patch programs CPTR_EL3 and ZCR_EL3 appropriately to enable
SVE for lower exception levels and make sure that they can use the
full vector length provided by the hardware.
Signed-off-by: Dave Martin <Dave.Martin@arm.com>
Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Currently we hard-code the set of CPUs we expect, and we have some
strong expectations on the formatting of nodes.
As we can configure models with differing sets of CPUs, we added the
with-cpu-ids configure option to override this assumption, though in
practice it turns out this is very fragile.
Instead, we can parse the DTB to discover the set of CPU nodes (and
hence the set of CPU IDs, and the number of CPUs). This is far more
robust.
This patch changes the bootwrapper to do this, removing the newly
redundant --with-cpu-ids configure option.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This will be useful for subsequent patches where we want to
automatically configure properties for nodes which may have arbitrary
names.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
In some cases, we'll want to parse a reg property that cannot be
translated, e.g. for cpu nodes. Add a helper to extract the reg without
attempting translation, factoring this logic out of
Node::get_translated_reg().
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
In a few cases, we check not $var to check if a var has a defined value.
This also catches the case where $var has a defined value, but evaluates
to false (e.g. if $var is zero).
In FDT::Node::get_translated_reg(), this erroneous check means that reg
entries with an address zero will not be translated, even where there is
a valid set of ranges properties in parent nodes.
Elsewhere, this is simply inconsistent, but not otherwise harmful.
Fix the code to use defined($var) consistently.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Vladimir Murzin <vladimir.murzin@arm.com>
Tested-by: Vladimir Murzin <vladimir.murzin@arm.com>
|
|
When doing a make clean, only the output image currently configured to
build is being removed. However, one would expect all build artifacts
to be removed when doing a 'make clean' and when switching between Xen
and Linux builds, it is easy to accidentally run an older build than
intended. Simply hardcode the axf image file names.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
If Xen is enabled, tell Dom0 to use the 'hvc0' console, and fall back to
the usual ttyAMA0 otherwise.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Support adding xen,xen-bootargs node via --with-xen-cmdline to the
configure script and automatically add the Dom0 node to the DT as well.
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
[Mark: s/XEN_BOOTARGS/XEN_CHOSEN/]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Add support for building a Xen binary which includes a Dom0 image and
the Dom0 command-line.
If the user specifies --with-xen=<Xen>, where Xen is an appropriate
AArch64 Xen binary, the build system will generate a xen-system.axf
instead of a linux-system.axf.
Original patch from Ian Campbell, but I modified most of it so all bugs
are probably mine.
[Andre: adapt to newest boot-wrapper branch, increase load address,
fixup Xen image file test]
Cc: Ian Campbell <ijc@hellion.org.uk>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Tested-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Reviewed-by: Julien Grall <julien.grall@arm.com>
|
|
The autotools documentation states that AC_CHECK_FILE cannot be used when
cross-compiling [1], because it's meant to check files in the target
system, not on the build host. When just giving --host on the configure
command line, the script detects cross compilation rather late; and as the
file test just happens to execute earlier, this works anyway.
However if one gives both --host and --build, cross compilation is
detected very early and ./configure complains:
checking for /src/linux-arm64... configure: error: cannot check for file existence when cross compiling
So replace the checkfile macro usage with a simple "test -f" call (which
is the recommended way of checking for files on the build host) and output
proper error messages.
[1] https://www.gnu.org/software/autoconf/manual/autoconf.html#Files
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
[Mark: simplified error messages]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This patch allows to build a 32-bit boot-wrapper, and create a complete
linux-system.axf for models that start in AArch32. Most of the code is a
simple translation of the AArch64 side.
We add an --aarch32-bw argument to ./configure, and bump the version to
0.2, to welcome this new architecture.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This patch adds a guard in the linker script to abort the build when the
bootloader code overflows the 12k limit. Indeed, 32-bit Linux with LPAE
enabled puts its initial page tables between 0x80003000 and 0x80007fff.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This patch adds an --enable-aarch32-kernel parameter to ./configure,
which enables dropping into AArch32 state at EL2. Notable differences
with AArch64 boot are:
* SCR.RW is set to 0, to declare all lower levels as AArch32,
* SPSR_EL2 has a 32-bit M[4:0] field,
* kernel parameters are different, but we can still put them into x0-x2,
because those registers are mapped to r0-r2 (ARM ARM v8 D1.20.1)
* SCTLR.CP15BEN is set, to allow the Linux decompressor to keep using
its legacy CP15 barriers.
* We also need to make sure MMU is disabled at EL1: hyp-stub in arm64
resets SCTLR_EL1, but the 32-bit hyp-stub doesn't. Leaving SCTRL.M set
would break hotplug when no hypervisor is present.
* PSCI function ID for CPU_ON differs.
We don't plan to support spin method on 32-bit. PSCI is automatically
enabled by ./configure, and this patch forbids disabling it.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
The 32-bit DT parser in Linux doesn't understand 'reg' properties with
two cells, in a CPU node. Since the boot-wrapper always sets the upper
bits to 0, we can restrict that size to one cell.
The parser also requires the device_type property to be present. This is
the case for arm64 as well, but it only fails when the patched device-tree
doesn't have any CPU node to begin with. Add device_type unconditionally.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
There is no harm in initialising the platform from EL3, so we move the
call into the boot_common path of CPU0, and take the opportunity to
rename ns_init_system to init_platform. Caches and MMU are now disabled
at EL3, and we can also move cache maintenance in the initial boot path
of each CPU. This allows us to get rid of the EL2 layer, which makes
AArch32 kernel support possible.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
We have a few good reasons to leave MMU disabled at EL3:
* Translations defined by our static pages might alias with the kernel,
leading to mismatched memory attributes and all kinds of pains.
* For legacy reasons, boot-wrapper accesses are not cached at the
moment (SCTLR_EL3.C is unset)
* It feels cumbersome to enable the MMU for one small exclusive
operation.
* Removing the static page tables also frees 4k of memory, which is
quite welcome when loading a 32-bit kernel case, where we only have
12k of bootloader RAM to play with.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
The commit prepares the removal of the MMU identity map, which was only
used for exclusive accesses (ldxr/stxr) in psci_cpu_on.
Instead of relying on exclusives, we assume that when stage-1
translation is disabled, all EL3 memory accesses have Device type, with
non-gathering and non-reordering attributes. This guarantees single-copy
atomicity of aligned halfword accesses, as per the ARM ARM.
We can thus switch to a less constrained (albeit bulkier) locking
mechanism. This patch implements Lamport's bakery lock, which doesn't
rely on atomic compare-and-swap primitives.
For bisectability, we remove the call to switch_to_idmap here.
Otherwise, the assertions made by the bakery lock code, regarding order
of accesses, are invalid. The rest of the code will be removed in a
subsequent patch.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
GCC might generate implicit calls to standard functions, for example
memcpy when copying a struct. Implement these functions upfront, to
ensure that GCC never uses some optimized version, which could do
unaligned device memory accesses. We only implement memcpy and memset
for the moment. The others (memmove, memcmp, ...) can be added in the
future if required.
We also add flags "-ffunction-sections", "-fdata-sections" to GCC, and
"--gc-sections" to ld, in order to avoid linking those functions into
the final image when they aren't used.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
[Mark: fold GICv3 and GICv2 patches for bisectability]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Add two assembly helpers for 32-bit MMIO accesses, and translate
platform initialisation to C. Since we can now add features without too
much pain, also output a string describing the boot-wrapper version.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Remove macro drop_el since its only user is now boot.S, and move all
defines to cpu.h.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This patch brings the boot-wrapper into the twenty-first century, by
introducing it to the C language. This change, along with the next few
patches, will greatly simplify the AArch32 port and overall maintenance.
The assembly side of PSCI now only contains basic dispatchers, for both
boot and SMC entries.
Initial boot flow:
asm _start boot.S
start_(no_)el3 psci.S or spin.S
C first_spin boot_common.c
spin boot_common.c
asm jump_kernel if CPU0 boot.S
CPU_ON flow:
asm smc_entry psci.S
C psci_cpu_on psci.c
asm smc_exit psci.S
CPU_OFF flow:
asm smc_entry psci.S
C psci_cpu_off psci.c
spin boot_common.c
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
This patch adds a simple utility to read the current CPU ID from C or
assembly. The underlying objective of this seemingly useless change is
to provide a clean base for C helpers. It introduces two include paths:
include/ and arch/*/include/asm
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
When rewriting some bits of the boot-wrapper in C, we will need tiny
per-CPU stacks. This patch reserves 256 bytes of stack for each CPU
defined in the CPU_IDS macro.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
|
|
Helpers find_logical_id and setup_vector, as well as the number of
expected CPUs, will be needed outside of PSCI during future refactoring
work. This patch puts them into utils.S, and moves the number of CPUs
one level up, in a macro defined by the Makefile.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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This patch moves all assembly to arch/aarch64.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Attempt to make the linker script more flexible, by removing explicit
object names. We move boot code into a ".init" section, and let ld freely
reorganize the rest.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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This patch moves page tables and vectors to their own section, in order
to avoid big alignment gaps in the middle of .text or .data. We also
remove all .org directives, as they are not needed.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The 32-bit linker struggles with INPUT directives in linker scripts, and
tends to include the whole ELF files instead of merging their sections.
Remove INPUT for object files and pass them as arguments to ld instead.
Also sneakily remove the orphan "BOOTLOADER" variable from Makefile.am,
since we're cleaning things up. It hasn't been used for a while.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The boot-wrapper allows to boot secondary CPUs through a PSCI interface.
This implementation is incomplete, and only understands two SMC calls,
CPU_ON and CPU_OFF. Since PSCI versions >=0.2 require to implement a few
more functions (VERSION, SUSPEND, SYSTEM_OFF...), we implement PSCI 0.1,
which doesn't specify what SMC numbers to use. An implementation needs
to advertise its SMC numbers to the kernel through device-tree nodes.
Our current SMC numbers are inconsistent with the rest of the world:
| B-W (0.1) | U-boot (0.1) | v0.2
---------------+--------------+--------------+--------------
CPU_OFF | 0x84000001 | 0x95c1ba5f | 0x84000002
64-bit CPU_ON | 0x84000002 | 0x95c1ba60 | 0xc4000003
This is a problem when testing systems like Jailhouse, that currently
don't read the device-tree but hard-code PSCI IDs. To align with the
rest of the world, switch to PSCI 0.2 IDs.
Note: this patch does *not* add PSCI 0.2 compatibility to the
boot-wrapper. We still advertise as 0.1.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The PL011 spec requires that baud rate settings should be done by
writing both xBRD registers followed by a write to LCR_H (which we
skipped so far completely).[1]
So include the FBRD register write as well and set up the LCR_H
register to initialise the UART to 8N1.
Also skip the automatic RTS/CTS enablement, as this may not be
used by the peer (and the generic UART does not have it at all).
[1] ARM PL011 TRM, 3.3.7 (top of page 3-14)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
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Currently, sctlr_el2 is initialised only in the cold boot path, and even then
we didn't set the RES1 bits. So we're lucky the cold boot path ever worked
given most of the bits are UNKNOWN.
Lack of initialisation in the hot boot path leads to kernel crash while CPU is
hot-plugging and KVM is enabled:
root@genericarmv8:~# echo 0 > /sys/devices/system/cpu/cpu1/online
kvm: disabling virtualization on CPU1
CPU1: shutdown
root@genericarmv8:~# echo 1 > /sys/devices/system/cpu/cpu1/online
Kernel panic - not syncing: HYP panic:
PS:000003c9 PC:0000000080002394 ESR:0000000086000005
FAR:0000000080002394 HPFAR: (null) PAR: (null)
VCPU: (null)
CPU: 1 PID: 0 Comm: swapper/1 Not tainted 3.16.0-rc1+ #162
Call trace:
[<ffffffc0000880d8>] dump_backtrace+0x0/0x12c
[<ffffffc000088214>] show_stack+0x10/0x1c
[<ffffffc000472680>] dump_stack+0x74/0xc4
[<ffffffc00046f8ec>] panic+0xe4/0x21c
[<ffffffc00046f804>] mmu_memory_cache_alloc.part.25+0x34/0x38
[<ffffffc00008a26c>] cpu_psci_cpu_die+0x20/0x40
[<ffffffc00008e95c>] cpu_die+0x40/0x70
[<ffffffc0000852e0>] arch_cpu_idle_dead+0x8/0x14
[<ffffffc0000dca4c>] cpu_startup_entry+0x144/0x14c
[<ffffffc00008e7f0>] secondary_start_kernel+0x118/0x128
Initialise sctlr_el2 in the reset value just before dropping from EL3 for psci
and spin-table boot protocols.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Rather than exploding very early on, just skip the GICv3 initialization
if no GICv3 CPU interface is reported available.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
[Mark: amend comment]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When the --enable-psci=no or --enable-gicv3=no form of configure option
was passed our configure script was setting the option to yes. This
changes the logic slightly to fix the problem.
Signed-off-by: Geoff Levand <geoff@infradead.org>
[Mark: fit with exiting USE_FEATURE naming scheme, fix whitespace]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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We recently added perl scripting to our makefile, but omitted adding the include
path of the local modules in the invocation of perl. Fixes build errors like
these when building out of the source tree:
Can't locate FDT.pm in @INC (you may need to install the FDT module)
Signed-off-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Performs the minimal initialization required for GICv3 support.
Support can be enabled with --enable-gicv3.
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Seems that something in autotools spits out a `compile' script, so add
this to .gitignore.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Some platforms differ significantly enough from the RTSM VE platform
such the RTSM VE DTB is not a valid DTB for the platform. Now that we
have the appropriate logic for detecting device and memory base
addresses, there's no reason we can't allwo the user to arbittrarily
choose to use another DTB so long as the basics are present (memory, a
pl011, and V2M sysregs).
This patch adds a "--with-dtb" option to override the DTB to use. The
aformentioned base addresses are automatically dicovered at build time.
Where a required device is not present, the build will fail.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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In case the start of physical memory happens to be different on some
model variant, this patch adds the necessary tooling to detect the base
address of said memory and ensure that the kernel and wrapper get loaded
at appropriate addresses.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The base addresses of various components can differ from one model to
another. As these addresses are currently hard-coded in the bootwrapper,
it is necessary to manually alter the bootwrapper for each variation.
This patch adds scripting to extract the (absolute / CPU) addresses of
various system components. With this change the bootwrapper build system
will automatically discover the addresses that need to be used.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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There are various models (RTSM VE, FVP Base, Foundation) which the
booterapper is intended to function on, but differences between these
(be they static or configurable) are difficult to handle as the
bootwrapper currently has hard-coded base addresses.
We already have a platform description (the device tree blob) which must
contain the correct addresses for a real OS to function, and it would be
nice if we could extract the values out of the device tree rather than
redundantly describing them in the boot wrapper.
This patch adds a pure perl library for parsing and querying values from
a device tree blob. Scripts may use this library to extract addresses
and other values from the DT.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Add the missing MAINTAINERCLEANFILES to makefile.am.
Signed-off-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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A couple of comments in cache.S are misleading. While they do not affect
the correctness of the code they do make it somewhat difficult to reason
about it:
CSSIDR_EL1[12:3] contains the associativity field, which is enconded as
one less than the total number of ways, (matching the maximum way index)
so the comment on line 40 is wrong.
Counting the leading zeros on a 32-bit register with the extracted
associativity field results in 32 - ceil(log2(max way index)), rather
than log2(ways) rounded down. Thus the comment on line 41 is also wrong.
This patch adjusts both comments to better reflect the code.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Althought comment is aligned with ARMv8 ARM implentation is different. In
fact, "set" is shifted by "shift" and "way" is shifted by "line size".
Correct this missalignment.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When using PSCI, the enable-method property for each CPU node in the
DTB needs to be set to "psci". Add a script and Makefile.am rules so
that this is done automatically for the final pass through DTC.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[Mark: remove backticks, fix copyright date, use $(), fix indentation]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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PSCI requires a node to be inserted into the FDT. Do this for the user
automatically if PSCI is enabled.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[Mark: add missing "method" property, fix indentation]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Add the --with-cpu-ids switch to the configure script to allow the
user to manually set the CPU IDs that are passed to PSCI.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[Mark: fix indentation]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The dtc tool should also be checked for in the $KERN_DIR/scripts/dtc
directory as it is shipped with Linux.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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The boot-wrapper can be build with or without support for
PSCI. Therefore add that as a configure option (which defaults to not
using PSCI) and set the appropriate options in the makefile.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[Mark: fix indentation]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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This patch adds a basic auto-tools configuration environment for the
bootwrapper consisting of the configure.ac file and the Makefile.am
file.
The configure.ac file includes several options and checks:
- Ensure that an AArch64 compiler is used.
- Add the mandatory --with-kernel-dir option that sets KERN_DIR.
- Check that the correct base dtb file exists in KERN_DIR.
- Add an option, --with-initrd, that allows a user to specify an
initrd file to embed in the image.
- Check for a working dtc and set DTC to the full-path to the
executable.
- Create the necessary symbolic links to the relevant kernel files.
The Makefile.am file includes several changes:
- Use a prebuilt dtb rather than a dts, which is decompiled to inject
the chosen node.
- Use the configured compiler tool names.
- Use the configured SED program rather than assuming it is in PATH.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
[Mark: use dtb, add options, fix style issues, remove src/]
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/cmarinas/boot-wrapper-aarch64.git
Unify upstream build system updates and PSCI support.
Conflicts:
Makefile
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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From 8a5783e72029c1ecd26fb99130b48a470e13a8da Mon Sep 17 00:00:00 2001
From: Geoff Levand <geoff@infradead.org>
Date: Wed, 13 Nov 2013 12:26:01 -0800
Allow user to pass compiler flags on the make command line as
in 'make CFLAGS="-g"'.
Signed-off-by: Geoff Levand <geoff@infradead.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Due to incorrect operands for an and, we treat the value of the Ctype1
field of clidr_el1 as if it were the LoC field.
Fix up the operands so we use LoC corretly.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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This patch adds a simple PSCI implementation, only supporting CPU_ON and
CPU_OFF. As this does not communicate with any hardware power controller
(yet), CPUs spin in an internal pen, with a wfe to limit their polling
speed.
While the model brings up CPUs with caches invalidated, we enable caches
and the MMU to allow the use of exclusive operations in the bootwrapper,
and thus the cache may allocate entries while in EL3. As PSCI requires
that caches are invalid when executing from a CPU_ON entry point, the
caches must be cleaned and invalided when we drop to EL2. This cleaning
is performed in a shim in EL2 as this is simpler than enabling/disabling
caches and the MMU on each SMC.
The list of all CPU IDs (MPIDRS with non-aff bits masked out) in the
system must be provided in the Makefile as the comma-separated list
CPU_IDs, to enable the bootwrapper to differentiate CPUs and provide the
correct error messages if for example the OS attempts to power on a CPU
multiple times. If this list does not match the CPUs present, it may not
be possible to bring some CPUs online, and the PSCI implementation may
erroneously acknowledge power on requests for non-existent CPUs.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Linux expects to be handed a system with caches disabled and
invalidated. While the model currently brings CPUs up with caches
invalidated, we'll need to invalidate caches when leaving the
bootwrapper if we enable them within the bootwrapper (e.g. for the use
of exclusive operations), as lines may be allocated.
This patch adds code to invalidate the dcaches and icaches. It is not
yet called.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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This patch factors out the spin-table boot protocol into its own file,
leaving boot.S to do all of the required EL3 initialisation, and calling
upon ns_init to perform EL2 initialisation.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Currently the bootwrapper still lumps together logically distinct pieces
of hardware initialisation, making porting to new platforms or adding
new features difficult. It would be nicer if we could separate some of
the functional units to make the code clearer and easier to extend.
To this end, this patch factors the secure GIC initialisation into its
own file. Additionally, the code is modified to route all interrupts to
the non-secure side, not just the first 64.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When we add PSCI, we'll want to share the same non-secure sysetem
initialisation code. As we're going to want to put spin-table and PSCI
implementations in separate files, it would be nice to have the
initialisation code in its own file, to make clear the separation
between early boot, platform interface code, and non-secure system
initialisation.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Currently we only test the Aff0 bits of the MPIDR to determine the
'primary' CPU. In multi-cluster systems, MPIDR.Aff{3,2,1} may not be
zero, and there may by multiple CPUs where MPIDR.Aff0 is zero. In these
systems we might determine that two cpus are the primary CPU.
This patch adds a MPIDR_ID_BITS mask, and uses it in all cases we test
the MPIDR, making this safe for multi-cluster systems. This doesn't
bring full support for multi-cluster systems, however, as they may
require additional hardware to be set up (e.g. CCI).
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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To support more complex functionality, it would be nice if we could
separate bits of the boot code into separate files.
This patch refactors the Makefile, allowing us to add more source files
later without having to add a new rule for each file. The defines we
pass to each object are also factored into separate lines for easier
modification in future.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Add a CURRENTEL_EL3 #define to make tests against the value of CurrentEL
clearer.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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PSCI needs to be able to drop cores to EL2 repeatedly, and it doesn't
make sense to always throw CPUs through the original boot path.
This patch changes the EL drop into a macro, and moves it to a common
file that can be used by different boot protocol / service
implementations. While doing so, the SPSR value used is split out to be
more legible.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Currently. we don't ignore several files produced during the build in
the .gitignore, which can make the output of git status very noisy.
Let's ignore all of the external dependencies we might add to the source
directory (dtc, *.dts{i,}, *.cpio.gz), and all of the files we'll
produce during the build (*.o, *.axf). Ignoring the general case of all
of these files should produce less churn in .gitignore in future, and we
can always add special exemptions if required.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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When we set the GICD_IGROUPRn registers, we have a dangling
post-increment at the end which is never useful, being overwritten in
every path. As we're only writing to 3 registers, the offsets of which
can be represented in immediates, use movs with immediate offsets to
perform the writes.
Reported-by: Nigel Stephens <nigel.stephens@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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We currently do an ldr from GICC_CTLR to w0, then immediately overwrite
w0 with a mov. Reading the GICC_CTLR has no effect on the state of the
GIC, so there's no reason to do the ldr. It's also inconsistent with the
way we set the GICD_CTLR.
Fix this.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
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Signed-off-by: Christoffer Dall <cdall@cs.columbia.edu>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Change the DT files that are required as they have been re-named in
the kernel.
Signed-off-by: Matthew Leach <matthew.leach@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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This patch is to avoid setting the MUXFPGA configuration in the platform
code in the kernel. On real hardware, this function is handled by the
boot monitor.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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This boot wrapper contains the code for initialising the ARMv8 software
model before the Linux kernel can run (see
Documentation/arm64/booting.txt in the kernel tree for the Linux booting
requirements).
Running "make" creates a "linux-system.axf" ELF file that can be loaded
by the software model.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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