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authorMark Rutland <mark.rutland@arm.com>2021-08-23 11:42:47 +0100
committerMark Rutland <mark.rutland@arm.com>2021-08-25 10:48:39 +0100
commit28932c41e14d730b8b9a7310071384178611fb32 (patch)
tree85dc54fc22af1de849cd193025ab0f58d0e13f60
parentc96e46f4d24370202f4e1088f046537baacea0e8 (diff)
downloadboot-wrapper-aarch64-28932c41e14d730b8b9a7310071384178611fb32.tar.gz
Rename `CNTFRQ` -> `COUNTER_FREQ`
To avoid any confusuion between the CNTFRQ/CNTFRQ_EL0 register and the vallue it will be progrmamed with, rename the `CNTFRQ` constant to `COUNTER_FREQ. In future patches this will allow us to use `CNTFRQ` as a macro for the AArch32 CP15 register encoding. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Marc Zyngier <maz@kernel.org>
-rw-r--r--Makefile.am4
-rw-r--r--arch/aarch32/boot.S2
-rw-r--r--arch/aarch64/boot.S2
3 files changed, 4 insertions, 4 deletions
diff --git a/Makefile.am b/Makefile.am
index 3591d23..d0a68df 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -13,12 +13,12 @@ SCRIPT_DIR := $(top_srcdir)/scripts
PHYS_OFFSET := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findmem.pl $(KERNEL_DTB))
UART_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,pl011')
SYSREGS_BASE := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findbase.pl $(KERNEL_DTB) 0 'arm,vexpress-sysreg' 2> /dev/null)
-CNTFRQ := 24000000
+COUNTER_FREQ := 24000000
CPU_IDS := $(shell perl -I $(SCRIPT_DIR) $(SCRIPT_DIR)/findcpuids.pl $(KERNEL_DTB))
NR_CPUS := $(shell echo $(CPU_IDS) | tr ',' ' ' | wc -w)
-DEFINES = -DCNTFRQ=$(CNTFRQ)
+DEFINES = -DCOUNTER_FREQ=$(COUNTER_FREQ)
DEFINES += -DCPU_IDS=$(CPU_IDS)
DEFINES += -DNR_CPUS=$(NR_CPUS)
DEFINES += $(if $(SYSREGS_BASE), -DSYSREGS_BASE=$(SYSREGS_BASE), )
diff --git a/arch/aarch32/boot.S b/arch/aarch32/boot.S
index 08bf932..4add338 100644
--- a/arch/aarch32/boot.S
+++ b/arch/aarch32/boot.S
@@ -54,7 +54,7 @@ _monitor:
mov r0, #(1 << 10 | 1 << 11) @ Enable NS access to CPACR
mcr p15, 0, r0, c1, c1, 2 @ NSACR
- ldr r0, =CNTFRQ
+ ldr r0, =COUNTER_FREQ
mcr p15, 0, r0, c14, c0, 0 @ CNTFRQ
bl gic_secure_init
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S
index 587a25f..bfbb6ec 100644
--- a/arch/aarch64/boot.S
+++ b/arch/aarch64/boot.S
@@ -118,7 +118,7 @@ ASM_FUNC(_start)
msr ZCR_EL3, x0 // for EL2.
1:
- ldr x0, =CNTFRQ
+ ldr x0, =COUNTER_FREQ
msr cntfrq_el0, x0
bl gic_secure_init