diff options
| author | Jean-Philippe Brucker <jean-philippe.brucker@arm.com> | 2016-05-18 17:32:19 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2016-06-15 10:27:35 +0100 |
| commit | f01ed6c65ce267c37efc3d48fc68e36af2d00e62 (patch) | |
| tree | cc6e87873aa70574bf54ca55c24a4fac922741ba | |
| parent | 0bb7b2545582accfdc440c099d9ccba4b3108c26 (diff) | |
| download | boot-wrapper-aarch64-f01ed6c65ce267c37efc3d48fc68e36af2d00e62.tar.gz | |
AArch64: get rid of EL2 trampoline
There is no harm in initialising the platform from EL3, so we move the
call into the boot_common path of CPU0, and take the opportunity to
rename ns_init_system to init_platform. Caches and MMU are now disabled
at EL3, and we can also move cache maintenance in the initial boot path
of each CPU. This allows us to get rid of the EL2 layer, which makes
AArch32 kernel support possible.
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | Makefile.am | 2 | ||||
| -rw-r--r-- | arch/aarch64/boot.S | 26 | ||||
| -rw-r--r-- | boot_common.c | 7 | ||||
| -rw-r--r-- | platform.c (renamed from ns.c) | 4 |
4 files changed, 18 insertions, 21 deletions
diff --git a/Makefile.am b/Makefile.am index 9189470..af0d7a6 100644 --- a/Makefile.am +++ b/Makefile.am @@ -92,7 +92,7 @@ CFLAGS += -Wall -fomit-frame-pointer CFLAGS += -ffunction-sections -fdata-sections LDFLAGS += --gc-sections -OFILES += boot_common.o bakery_lock.o ns.o $(GIC) cache.o lib.o +OFILES += boot_common.o bakery_lock.o platform.o $(GIC) cache.o lib.o OFILES += $(addprefix $(ARCH_SRC),boot.o stack.o $(BOOTMETHOD) utils.o) all: $(IMAGE) diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 8bb536f..1602807 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -75,28 +75,18 @@ jump_kernel: ldr w0, flag_no_el3 cmp w0, #0 // Prepare Z flag - b.ne el2_trampoline // No EL3 - - mov x4, #SPSR_KERNEL - adr x5, el2_trampoline - msr elr_el3, x5 - msr spsr_el3, x4 - eret - -el2_trampoline: - bl flush_caches - - cpuid x0, x1 - b.ne 1f - bl ns_init_system - - /* Load kernel parameters */ -1: mov x0, x20 + mov x0, x20 mov x1, x21 mov x2, x22 mov x3, x23 - br x19 + b.eq 1f + br x19 // No EL3 + +1: mov x4, #SPSR_KERNEL + msr elr_el3, x19 + msr spsr_el3, x4 + eret .ltorg diff --git a/boot_common.c b/boot_common.c index 983c5d9..daf3198 100644 --- a/boot_common.c +++ b/boot_common.c @@ -12,6 +12,9 @@ extern unsigned long kernel; extern unsigned long dtb; +void init_platform(void); +void flush_caches(void); + void __noreturn jump_kernel(unsigned long address, unsigned long a0, unsigned long a1, @@ -55,7 +58,11 @@ void __noreturn spin(unsigned long *mbox, unsigned long invalid, int is_entry) void __noreturn first_spin(unsigned int cpu, unsigned long *mbox, unsigned long invalid) { + flush_caches(); + if (cpu == 0) { + init_platform(); + *mbox = (unsigned long)&kernel; sevl(); spin(mbox, invalid, 1); @@ -1,5 +1,5 @@ /* - * ns.c - code to initialise everything required when first booting. + * platform.c - code to initialise everything required when first booting. * * Copyright (C) 2015 ARM Limited. All rights reserved. * @@ -45,7 +45,7 @@ static void print_string(const char *str) } } -void ns_init_system(void) +void init_platform(void) { /* * UART initialisation (38400 8N1) |