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| author | Joey Gouly <joey.gouly@arm.com> | 2023-06-16 17:00:36 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2023-06-19 09:31:45 +0100 |
| commit | 44e25f43712597a75f1a5e547c66881b3750e0cf (patch) | |
| tree | 2f6e5919357e6947c8923a29d16b785ed9239209 | |
| parent | 226fddeaaa1295688ddbad563b67b1c90113efeb (diff) | |
| download | boot-wrapper-aarch64-44e25f43712597a75f1a5e547c66881b3750e0cf.tar.gz | |
aarch64: enable Permission Indirection Extension
Allow lower ELs to access the registers associated with the Permission
Indirection Extension.
Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 5 | ||||
| -rw-r--r-- | arch/aarch64/init.c | 13 |
2 files changed, 18 insertions, 0 deletions
diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 0213d53..d1f8fd9 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -55,6 +55,7 @@ #define SCR_EL3_HXEn BIT(38) #define SCR_EL3_EnTP2 BIT(41) #define SCR_EL3_TCR2EN BIT(43) +#define SCR_EL3_PIEN BIT(45) #define HCR_EL2_RES1 BIT(1) @@ -78,6 +79,10 @@ #define ID_AA64MMFR1_EL1_HCX BITS(43, 40) #define ID_AA64MMFR3_EL1_TCRX BITS(4, 0) +#define ID_AA64MMFR3_EL1_S1PIE BITS(11, 8) +#define ID_AA64MMFR3_EL1_S2PIE BITS(15, 12) +#define ID_AA64MMFR3_EL1_S1POE BITS(19, 16) +#define ID_AA64MMFR3_EL1_S2POE BITS(23, 20) #define ID_AA64PFR1_EL1_MTE BITS(11, 8) #define ID_AA64PFR1_EL1_SME BITS(27, 24) diff --git a/arch/aarch64/init.c b/arch/aarch64/init.c index e09e050..c4e91e4 100644 --- a/arch/aarch64/init.c +++ b/arch/aarch64/init.c @@ -42,6 +42,16 @@ static inline bool cpu_has_pauth(void) (mrs(ID_AA64ISAR2_EL1) & isar2_pauth); } +static inline bool cpu_has_permission_indirection(void) +{ + const unsigned long mask = ID_AA64MMFR3_EL1_S1PIE | + ID_AA64MMFR3_EL1_S2PIE | + ID_AA64MMFR3_EL1_S1POE | + ID_AA64MMFR3_EL1_S2POE; + + return mrs(ID_AA64MMFR3_EL1) & mask; +} + void cpu_init_el3(void) { unsigned long scr = SCR_EL3_RES1 | SCR_EL3_NS | SCR_EL3_HCE; @@ -70,6 +80,9 @@ void cpu_init_el3(void) msr(TCR2_EL1, 0); } + if (cpu_has_permission_indirection()) + scr |= SCR_EL3_PIEN; + if (mrs_field(ID_AA64PFR1_EL1, MTE) >= 2) scr |= SCR_EL3_ATA; |