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| author | Mark Rutland <mark.rutland@arm.com> | 2013-01-07 13:50:44 +0000 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2013-06-05 13:56:14 +0100 |
| commit | 85c331041d99a56c17a3723afa5d378acd2c82d6 (patch) | |
| tree | 8ad1a207d005af11635b5496720218d7e53e2585 | |
| parent | fc9e28de1da7c08886ee0cf46d5cbe74ea31b0fe (diff) | |
| download | boot-wrapper-aarch64-85c331041d99a56c17a3723afa5d378acd2c82d6.tar.gz | |
Use immediate offsets rather than post-increment
When we set the GICD_IGROUPRn registers, we have a dangling
post-increment at the end which is never useful, being overwritten in
every path. As we're only writing to 3 registers, the offsets of which
can be represented in immediates, use movs with immediate offsets to
perform the writes.
Reported-by: Nigel Stephens <nigel.stephens@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | boot.S | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -43,10 +43,10 @@ _start: 1: ldr x1, =GIC_DIST_BASE + 0x80 // GICD_IGROUPR mov w0, #~0 // Grp1 interrupts - str w0, [x1], #4 + str w0, [x1] b.ne 2f // Only local interrupts for secondary CPUs - str w0, [x1], #4 - str w0, [x1], #4 + str w0, [x1, #4] + str w0, [x1, #8] 2: ldr x1, =GIC_CPU_BASE // GICC_CTLR mov w0, #3 // EnableGrp0 | EnableGrp1 |