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| author | Mark Rutland <mark.rutland@arm.com> | 2021-07-23 10:44:36 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2022-01-27 16:13:59 +0000 |
| commit | df06a1f49df9f10542f308a2dba939ec16c0ec13 (patch) | |
| tree | af0aec69438c30f9fd6ce0d55befa9564fa9af98 | |
| parent | 65113684081560a958726e392f400fdb23e2ccd6 (diff) | |
| download | boot-wrapper-aarch64-df06a1f49df9f10542f308a2dba939ec16c0ec13.tar.gz | |
aarch64: add mov_64 macro
In subsequent patches we'll need to load 64-bit values into GPRs before
the CPU is in a known endianness, where we cannot use literal pools.
In preparation for that, this patch adds a new `mov_64` macro to load a
64-bit value into a GPR using a sequence of MOV and MOVKs, which will
function the same regardless of the CPU's endianness.
At the same time, move the `cpuid` macro to use `mov_64` internally.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | arch/aarch64/common.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/arch/aarch64/common.S b/arch/aarch64/common.S index c7171a9..3279fa9 100644 --- a/arch/aarch64/common.S +++ b/arch/aarch64/common.S @@ -9,9 +9,17 @@ #include <cpu.h> + /* Load a 64-bit value using immediates */ + .macro mov_64 dest, val + mov \dest, #(((\val) >> 0) & 0xffff) + movk \dest, #(((\val) >> 16) & 0xffff), lsl #16 + movk \dest, #(((\val) >> 32) & 0xffff), lsl #32 + movk \dest, #(((\val) >> 48) & 0xffff), lsl #48 + .endm + /* Put MPIDR into \dest, clobber \tmp and flags */ .macro cpuid dest, tmp mrs \dest, mpidr_el1 - ldr \tmp, =MPIDR_ID_BITS + mov_64 \tmp, MPIDR_ID_BITS ands \dest, \dest, \tmp .endm |