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2024-04-24ls-ecaps: Correct the link state reportingAlexey Kardashevskiy1-6/+6
2024-02-26ls-ecaps: Add decode support for IDE Extended CapabilityAlexey Kardashevskiy1-0/+346
2023-10-19Subject: lspci: Display PASID required attribute in Page Status Register.Ashok Raj1-0/+325
2023-04-29Add test case with multidomain Freescale P2020 PCIe hierarchyPali Rohár1-0/+1548
2022-11-16lspci: Add test case for CXL deviceJaxon Haws1-0/+258
2022-02-26pciutils: Add decode support for Data Object Exchange Extended CapabilityJonathan Cameron1-0/+302
2022-01-21lspci: Update tests files with VF 10-Bit Tag RequesterDongdong Liu3-6/+6
2020-09-02pciutils: Add decode support for RCECsSean V Kelley1-0/+299
2020-05-27CXL: Capability vendor ID changedSean V Kelley1-95/+108
2020-05-25lspci: Decode the (virtual) resizeble BAR capabilityMartin Mares1-0/+258
2020-05-25Tests: cap-dvsec was superseded by cap-dvsec-cxlMartin Mares1-340/+0
2020-05-25Tests: cap-dvsec-cxl had tabs erroneously expanded to spacesMartin Mares1-83/+83
2020-05-25pciutils: Decode Compute eXpress Link DVSECSean V Kelley1-0/+340
2020-05-25pciutils: Decode available DVSEC detailsSean V Kelley1-0/+340
2020-05-25lspci: Decode PCIe Link Capabilities 2, expand Link Status 2Bjorn Helgaas1-0/+1317
2019-02-22lspci: Decode all defined fields in the Device Capabilities 2 registerFrederick Lawler1-11/+17
2018-11-12lspci: Decode Multicast Extended CapabilityBjorn Helgaas1-0/+257
2018-08-12Added test cases for topology computationMartin Mares2-0/+7350
2018-03-24lspci: Avoid "%1$c" style format strings in HT capabilityMartin Mares1-0/+99
2017-12-31lspci: Decode "VGA 16-bit decode" in bridge control registerBjorn Helgaas1-0/+129
2017-04-29lspci: Decode only supported ASPM exit latenciesBjorn Helgaas1-0/+327
2017-04-29lspci: Decode "Slot Implemented" for PCI/PCI-X to PCIe BridgesBjorn Helgaas1-0/+288
2017-04-29lspci: Indent PCIe Capability DevCap2 & DevCtl2 correctlyBjorn Helgaas1-0/+327
2017-04-29lspci: Include "ECRC" in the ECRC generate/check labelsBjorn Helgaas1-0/+327
2017-04-29lspci: Decode AER Root Error Command, Root Error Status, Error SourceBjorn Helgaas1-0/+626
2017-04-29lspci: Dump AER Header LogBjorn Helgaas1-0/+323
2017-04-29lspci: Decode AER Multiple Header and TLP Prefix Log bitsBjorn Helgaas1-0/+322
2017-02-15pciutils: Add test case for pci atomic opsSatanand Burla1-0/+54
2016-10-03pciutils: Update the tests/cap-l1-pm with actual device dataRajat Jain1-24/+303
2016-05-19lspci: Add test case for PTMYong, Jonathan2-0/+576
2016-05-14Add support for Downstream Port ContainmentKeith Busch1-0/+91
2016-01-03Add lspci support for Enhanced Allocation Capability.David Daney1-0/+324
2015-10-27Decode PASID and PRI extended capabilitiesDavid Woodhouse1-0/+293
2015-01-22Added test case for virtioMartin Mares1-0/+41
2013-06-11Added a test case for the L1 PM capabilityMartin Mares1-0/+26
2010-01-31Added a test case for the VC capability with a port arbitration tableMartin Mares1-0/+257
2010-01-23Added a test case for Virtual Channel and Root Complex Link capsMartin Mares1-0/+2317
2010-01-19Added a test case for broken extended capabilitiesMartin Mares1-0/+257
2009-08-21Fix spelling of surpriseEd Swierk2-3/+3
2009-07-04Added a test case for the PCI AF capabilityYu Zhao1-0/+29
2008-12-30Updated test cases from Yu Zhao.Martin Mares2-67/+71
2008-12-12lspci: fix "suprise" typoBjorn Helgaas3-3/+3
2008-11-12Added a test case for the ATS capability.Yu Zhao1-0/+298
2008-11-09Fix spelling of MSI.Martin Mares2-2/+2
2008-08-26Added test cases for new PCIE capabilities.Martin Mares2-0/+622
2007-10-19Added a couple of test cases.Martin Mares2-0/+575
2007-08-14Added decoding of HT MSI capability.Martin Mares1-0/+17
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