diff options
author | Jean Delvare <jdelvare@suse.de> | 2012-10-25 12:02:15 +0000 |
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committer | Jean Delvare <jdelvare@suse.de> | 2012-10-25 12:02:15 +0000 |
commit | 6c2df5dec87b113d9c44e7de9af98f538a8ed12c (patch) | |
tree | 1290860f1b743468c8b41f59c6049258b88fa100 | |
parent | b14a4cbd84b7f5dd8dd74b95414873a4dace8953 (diff) | |
download | i2c-tools-6c2df5dec87b113d9c44e7de9af98f538a8ed12c.tar.gz |
decode-dimms: Print DDR2 core timings for all supported CAS values, as
we do for DDR modules.
git-svn-id: http://lm-sensors.org/svn/i2c-tools/trunk@6082 7894878c-1315-0410-8ee3-d5d059ff63e0
-rwxr-xr-x | eeprom/decode-dimms | 32 |
1 files changed, 23 insertions, 9 deletions
diff --git a/eeprom/decode-dimms b/eeprom/decode-dimms index 9d1ed3e..31307e8 100755 --- a/eeprom/decode-dimms +++ b/eeprom/decode-dimms @@ -1069,6 +1069,14 @@ sub ddr2_refresh_rate($) ($byte & 0x80 ? " - Self Refresh" : ""); } +sub ddr2_core_timings($$$$$) +{ + my ($cas, $ctime, $trcd, $trp, $tras) = @_; + + return $cas . "-" . ceil($trcd/$ctime) . "-" . ceil($trp/$ctime) . + "-" . ceil($tras/$ctime) . " as DDR2-" . int(2000 / $ctime); +} + # Parameter: EEPROM bytes 0-127 (using 3-62) sub decode_ddr2_sdram($) { @@ -1152,38 +1160,44 @@ sub decode_ddr2_sdram($) $trp = ($bytes->[27] >> 2) + (($bytes->[27] & 3) * 0.25); $tras = $bytes->[30]; - printl("tCL-tRCD-tRP-tRAS", - $highestCAS . "-" . - ceil($trcd/$ctime) . "-" . - ceil($trp/$ctime) . "-" . - ceil($tras/$ctime)); - # latencies printl("Supported CAS Latencies (tCL)", cas_latencies(keys %cas)); # timings - my ($cycle_time, $access_time); + my ($cycle_time, $access_time, $core_timings); if (exists $cas{$highestCAS}) { + $core_timings = ddr2_core_timings($highestCAS, $ctime, + $trcd, $trp, $tras); + $cycle_time = tns($ctime) . " at CAS $highestCAS (tCK min)"; $access_time = tns(ddr2_sdram_atime($bytes->[10])) . " at CAS $highestCAS (tAC)"; } if (exists $cas{$highestCAS-1} && spd_written(@$bytes[23..24])) { - $cycle_time .= "\n".tns(ddr2_sdram_ctime($bytes->[23])) + $ctime = ddr2_sdram_ctime($bytes->[23]); + $core_timings .= "\n".ddr2_core_timings($highestCAS-1, $ctime, + $trcd, $trp, $tras); + + $cycle_time .= "\n".tns($ctime) . " at CAS ".($highestCAS-1); $access_time .= "\n".tns(ddr2_sdram_atime($bytes->[24])) . " at CAS ".($highestCAS-1); } if (exists $cas{$highestCAS-2} && spd_written(@$bytes[25..26])) { - $cycle_time .= "\n".tns(ddr2_sdram_ctime($bytes->[25])) + $ctime = ddr2_sdram_ctime($bytes->[25]); + $core_timings .= "\n".ddr2_core_timings($highestCAS-2, $ctime, + $trcd, $trp, $tras); + + $cycle_time .= "\n".tns($ctime) . " at CAS ".($highestCAS-2); $access_time .= "\n".tns(ddr2_sdram_atime($bytes->[26])) . " at CAS ".($highestCAS-2); } + printl_cond(defined $core_timings, "tCL-tRCD-tRP-tRAS", $core_timings); printl_cond(defined $cycle_time, "Minimum Cycle Time", $cycle_time); printl_cond(defined $access_time, "Maximum Access Time", $access_time); $temp = ddr2_sdram_ctime($bytes->[43]); |