mcelog: Add decoding for Optane DC persistent memory mode

Recognise the new MCACOD for errors in DDR memory in use as a cache
for Optane DC persistent memory.

In binary the new code looks similar to the old memory controller
compound error code. The only difference is that bit 9 is set in
addition to bit 7:

	000F 0010 1MMM CCCC

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/p4.c b/p4.c
index adb4c5e..8e1ec2f 100644
--- a/p4.c
+++ b/p4.c
@@ -199,6 +199,9 @@ static int decode_mca(u64 status, u64 misc, u64 track, int cpu, int *ismemerr, i
 					      CACHE_RRRR_SHIFT));
 		if (track == 2)
 			run_yellow_trigger(cpu, typenum, levelnum, type, level,socket);
+	} else if (test_prefix(9, mca) && EXTRACT(mca, 7, 8) == 1) {
+		Wprintf("Memory as cache: ");
+		decode_memory_controller(mca, bank);
 	} else if (test_prefix(10, mca)) {
 		if (mca == 0x400)
 			Wprintf("Internal Timer error\n");