diff options
author | Tony Luck <tony.luck@intel.com> | 2020-09-15 16:22:47 -0700 |
---|---|---|
committer | Andi Kleen <ak@linux.intel.com> | 2020-09-17 12:37:38 -0700 |
commit | ccb4cecfc6156e017a86af23f69785822c3100e1 (patch) | |
tree | 810968a10204bb3125a38182b0a18655246be5ce | |
parent | 391abaac9bdff385934b18134789bcc98b0adeb7 (diff) | |
download | mcelog-ccb4cecfc6156e017a86af23f69785822c3100e1.tar.gz |
mcelog: Add Tigerlake, Rocketlake, Alderlake, Lakefieldv171
-----------------
Client models, just do the default decoding.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
-rw-r--r-- | intel.c | 12 | ||||
-rw-r--r-- | intel.h | 6 | ||||
-rw-r--r-- | mcelog.c | 12 | ||||
-rw-r--r-- | mcelog.h | 4 |
4 files changed, 31 insertions, 3 deletions
@@ -41,7 +41,9 @@ void intel_cpu_init(enum cputype cpu) cpu == CPU_SKYLAKE || cpu == CPU_SKYLAKE_XEON || cpu == CPU_KABYLAKE || cpu == CPU_DENVERTON || cpu == CPU_ICELAKE || cpu == CPU_ICELAKE_XEON || cpu == CPU_ICELAKE_DE || - cpu == CPU_TREMONT_D || cpu == CPU_COMETLAKE) + cpu == CPU_TREMONT_D || cpu == CPU_COMETLAKE || + cpu == CPU_TIGERLAKE || cpu == CPU_ROCKETLAKE || + cpu == CPU_ALDERLAKE || cpu == CPU_LAKEFIELD) memory_error_support = 1; } @@ -112,6 +114,14 @@ enum cputype select_intel_cputype(int family, int model) return CPU_TREMONT_D; else if (model == 0xa5 || model == 0xa6) return CPU_COMETLAKE; + else if (model == 0x8C || model == 0x8D) + return CPU_TIGERLAKE; + else if (model == 0xA7) + return CPU_ROCKETLAKE; + else if (model == 0x97) + return CPU_ALDERLAKE; + else if (model == 0x8A) + return CPU_LAKEFIELD; if (model > 0x1a) { Eprintf("Family 6 Model %u CPU: only decoding architectural errors\n", model); @@ -33,5 +33,9 @@ extern int memory_error_support; case CPU_ICELAKE_XEON: \ case CPU_ICELAKE_DE: \ case CPU_TREMONT_D: \ - case CPU_COMETLAKE + case CPU_COMETLAKE: \ + case CPU_TIGERLAKE: \ + case CPU_ROCKETLAKE: \ + case CPU_ALDERLAKE: \ + case CPU_LAKEFIELD @@ -250,6 +250,10 @@ static char *cputype_name[] = { [CPU_ICELAKE_DE] = "Icelake server D Family", [CPU_TREMONT_D] = "Tremont microserver", [CPU_COMETLAKE] = "Cometlake", + [CPU_TIGERLAKE] = "Tigerlake", + [CPU_ROCKETLAKE] = "Rocketlake", + [CPU_ALDERLAKE] = "Alderlake", + [CPU_LAKEFIELD] = "Lakefield", }; static struct config_choice cpu_choices[] = { @@ -307,6 +311,10 @@ static struct config_choice cpu_choices[] = { { "icelake-d", CPU_ICELAKE_DE }, { "snowridge", CPU_TREMONT_D }, { "cometlake", CPU_COMETLAKE }, + { "tigerlake", CPU_TIGERLAKE }, + { "rocketlake", CPU_ROCKETLAKE }, + { "alderlake", CPU_ALDERLAKE }, + { "lakefield", CPU_LAKEFIELD }, { NULL } }; @@ -481,7 +489,9 @@ static void dump_mce(struct mce *m, unsigned recordlen) cputype != CPU_SKYLAKE && cputype != CPU_SKYLAKE_XEON && cputype != CPU_KABYLAKE && cputype != CPU_DENVERTON && cputype != CPU_ICELAKE_XEON && cputype != CPU_ICELAKE_DE && - cputype != CPU_TREMONT_D && cputype != CPU_COMETLAKE) + cputype != CPU_TREMONT_D && cputype != CPU_COMETLAKE && + cputype != CPU_TIGERLAKE && cputype != CPU_ROCKETLAKE && + cputype != CPU_ALDERLAKE && cputype != CPU_LAKEFIELD) resolveaddr(m->addr); } @@ -145,6 +145,10 @@ enum cputype { CPU_ICELAKE_DE, CPU_TREMONT_D, CPU_COMETLAKE, + CPU_TIGERLAKE, + CPU_ROCKETLAKE, + CPU_ALDERLAKE, + CPU_LAKEFIELD, }; enum option_ranges { |