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| author | Tony Luck <tony.luck@intel.com> | 2019-02-05 10:10:40 -0800 |
|---|---|---|
| committer | Andi Kleen <ak@linux.intel.com> | 2019-02-05 11:57:07 -0800 |
| commit | 0062f7cb3ff0f94709087ac302d502f5e39f6e60 (patch) | |
| tree | c17dc25d1839a30913c814ce4bc03d5e75654cac | |
| parent | ad87d7304471a7f93a10acd2d5522486b511689a (diff) | |
| download | mcelog-0062f7cb3ff0f94709087ac302d502f5e39f6e60.tar.gz | |
mcelog: Fix memory controller bank channel mappings for Skylakev162
Skylake doesn't use banks 13-15 for IMC0 and 16-18 for IMC1 as I
thought. The ordering is less obvious:
channel
IMC 0 1 2
----+---------------------
0 | 13 14 17
1 | 15 16 18
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
| -rw-r--r-- | skylake_xeon.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/skylake_xeon.c b/skylake_xeon.c index b02f8ac..3dad48c 100644 --- a/skylake_xeon.c +++ b/skylake_xeon.c @@ -256,13 +256,23 @@ void skylake_memerr_misc(struct mce *m, int *channel, int *dimm) /* Home agent 1 */ chan += 3; break; - case 13: case 14: case 15: - /* Memory controller 0 */ - chan = m->bank - 13; + case 13: /* Memory controller 0, channel 0 */ + chan = 0; break; - case 16: case 17: case 18: - /* Memory controller 1 */ - chan = (m->bank - 16) + 3; + case 14: /* Memory controller 0, channel 1 */ + chan = 1; + break; + case 15: /* Memory controller 1, channel 0 */ + chan = 3; + break; + case 16: /* Memory controller 1, channel 1 */ + chan = 4; + break; + case 17: /* Memory controller 0, channel 2 */ + chan = 2; + break; + case 18: /* Memory controller 1, channel 2 */ + chan = 5; break; default: return; |