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| author | Tony Luck <tony.luck@intel.com> | 2024-04-24 11:15:00 -0700 |
|---|---|---|
| committer | Dave Hansen <dave.hansen@linux.intel.com> | 2024-04-25 09:04:32 -0700 |
| commit | 0011a51d73d57866c8d7ee8be2ff1e5baa17f6ca (patch) | |
| tree | d08567ea4cbea0edac9426cd7c29b2f83a5b557a | |
| parent | 5ee800945a3466c3b126020c8f4ffc6b54d6986f (diff) | |
| download | tip-0011a51d73d57866c8d7ee8be2ff1e5baa17f6ca.tar.gz | |
perf/x86/lbr: Switch to new Intel CPU model defines
New CPU #defines encode vendor and family as well as model.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>
Link: https://lore.kernel.org/all/20240424181500.41519-1-tony.luck%40intel.com
| -rw-r--r-- | arch/x86/events/intel/lbr.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c index 78cd5084104e9c..86277196ffadda 100644 --- a/arch/x86/events/intel/lbr.c +++ b/arch/x86/events/intel/lbr.c @@ -2,6 +2,7 @@ #include <linux/perf_event.h> #include <linux/types.h> +#include <asm/cpu_device_id.h> #include <asm/perf_event.h> #include <asm/msr.h> @@ -1457,7 +1458,7 @@ void __init intel_pmu_lbr_init_atom(void) * to have an operational LBR which can freeze * on PMU interrupt */ - if (boot_cpu_data.x86_model == 28 + if (boot_cpu_data.x86_vfm == INTEL_ATOM_BONNELL && boot_cpu_data.x86_stepping < 10) { pr_cont("LBR disabled due to erratum"); return; |