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| author | Catalin Marinas <catalin.marinas@arm.com> | 2013-12-05 16:56:50 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2013-12-06 17:21:52 +0000 |
| commit | 2f7dc6027522499582a520807cb9ffda589de47e (patch) | |
| tree | a66a8bbd89cea0bb39e98638d0d805d72dd4a45d | |
| parent | 85cc00eaa81dfa0f5bf8076c48f3ee2c2c4a77ba (diff) | |
| download | mfd-fixes-2f7dc6027522499582a520807cb9ffda589de47e.tar.gz | |
arm64: Fix memory shareability attribute for ioremap_wc/cache
Write-combine and cacheable mappings use Normal memory on arm64. On SMP
systems, the pte needs the shareability bit which is set in
pgprot_default. Use this for defining PROT_DEFAULT used by ioremap_wc
and ioremap_cache (Device memory is shareable by default, does not need
additional attributes).
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
| -rw-r--r-- | arch/arm64/include/asm/io.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index 4cc813eddacbe..5727697272276 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -229,7 +229,7 @@ extern void __iomem *__ioremap(phys_addr_t phys_addr, size_t size, pgprot_t prot extern void __iounmap(volatile void __iomem *addr); extern void __iomem *ioremap_cache(phys_addr_t phys_addr, size_t size); -#define PROT_DEFAULT (PTE_TYPE_PAGE | PTE_AF | PTE_DIRTY) +#define PROT_DEFAULT (pgprot_default | PTE_DIRTY) #define PROT_DEVICE_nGnRE (PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE)) #define PROT_NORMAL_NC (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL_NC)) #define PROT_NORMAL (PROT_DEFAULT | PTE_ATTRINDX(MT_NORMAL)) |