diff options
| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-07-24 12:03:51 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:06:50 +0100 |
| commit | da7da368d2838c50894139749cb959129159b436 (patch) | |
| tree | aa7743998373e9f7db0a9a47e8fb7e2229551cc5 | |
| parent | 9e0437b068eb62676612da915416e3cb4c7509e2 (diff) | |
| download | linux-cip-da7da368d2838c50894139749cb959129159b436.tar.gz | |
ARM: dts: r8a7745: Add CAN[01] SoC support
Add the definitions for can0 and can1 to the SoC .dtsi.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 85d3122659be310c632ef1908532157ce82900ee)
(moved nodes to a better location to allow for better sorting.
modified clocks and power-domains properties. removed resets
properties)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 34 |
1 files changed, 34 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 6fdd3c2c4902a..c2e38ae254d62 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -32,6 +32,14 @@ spi3 = &msiof2; }; + /* External CAN clock */ + can_clk: can { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board. */ + clock-frequency = <0>; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -844,6 +852,32 @@ status = "disabled"; }; + can0: can@e6e80000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e80000 0 0x1000>; + interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7745_CLK_RCAN0>, + <&cpg_clocks R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + + can1: can@e6e88000 { + compatible = "renesas,can-r8a7745", + "renesas,rcar-gen2-can"; + reg = <0 0xe6e88000 0 0x1000>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&mstp9_clks R8A7745_CLK_RCAN1>, + <&cpg_clocks R8A7745_CLK_RCAN>, + <&can_clk>; + clock-names = "clkp1", "clkp2", "can_clk"; + power-domains = <&cpg_clocks>; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7745", "renesas,pci-rcar-gen2"; |