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| author | Paul Gortmaker <paul.gortmaker@windriver.com> | 2020-09-16 14:47:30 -0400 |
|---|---|---|
| committer | Paul Gortmaker <paul.gortmaker@windriver.com> | 2020-09-16 14:47:30 -0400 |
| commit | 979db6aa93f9f2e1392a0e9a8657d424bbab95ec (patch) | |
| tree | 4179664b729e4e21d435034016b71d56edc9e260 | |
| parent | 06c1e237d52e542b3c6d4a683a31a579fd9d183a (diff) | |
| download | longterm-queue-5.2-979db6aa93f9f2e1392a0e9a8657d424bbab95ec.tar.gz | |
PCI: qcom: ctxt refresh
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
| -rw-r--r-- | queue/PCI-qcom-Add-support-for-tx-term-offset-for-rev-2.1..patch | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/queue/PCI-qcom-Add-support-for-tx-term-offset-for-rev-2.1..patch b/queue/PCI-qcom-Add-support-for-tx-term-offset-for-rev-2.1..patch index 9c15a07b..a25ccc49 100644 --- a/queue/PCI-qcom-Add-support-for-tx-term-offset-for-rev-2.1..patch +++ b/queue/PCI-qcom-Add-support-for-tx-term-offset-for-rev-2.1..patch @@ -1,4 +1,4 @@ -From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001 +From 7c9d5d15b713f94102aaf82ad79b54f725c2a875 Mon Sep 17 00:00:00 2001 From: Ansuel Smith <ansuelsmth@gmail.com> Date: Mon, 15 Jun 2020 23:06:04 +0200 Subject: [PATCH] PCI: qcom: Add support for tx term offset for rev 2.1.0 @@ -17,7 +17,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> Cc: stable@vger.kernel.org # v4.5+ diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c -index 69c7b119e81a..34d961e492fd 100644 +index 8611760c9501..a16994e59776 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -45,7 +45,13 @@ @@ -34,7 +34,7 @@ index 69c7b119e81a..34d961e492fd 100644 #define PCIE20_PARF_DBI_BASE_ADDR 0x168 #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x16C #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174 -@@ -371,9 +377,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) +@@ -343,9 +349,18 @@ static int qcom_pcie_init_2_1_0(struct qcom_pcie *pcie) writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS); } @@ -53,7 +53,7 @@ index 69c7b119e81a..34d961e492fd 100644 + val |= PHY_REFCLK_SSP_EN; writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); - /* wait for clock acquisition */ + ret = reset_control_deassert(res->phy_reset); -- 2.27.0 |