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| author | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-29 10:50:35 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-04-29 10:50:35 -0700 |
| commit | 3a5d34ad7e34955b8a8e6c0cbbd1e8341fb2de99 (patch) | |
| tree | 6fcba737857daa6cafbd2325f1a761ad98e0118f | |
| parent | bdf3e7cfa1f58df99685a7fdf1b89e5587be030d (diff) | |
| parent | 58661a30f1bcc748475ffd9be6d2fc9e4e6be679 (diff) | |
| download | linux-fixes.tar.gz | |
Merge commit '58661a30f1bcc748475ffd9be6d2fc9e4e6be679' into fixesfixes
This single fix is part of a larger series with a handful of new
features, but I'm pulling the fix ahead into fixes so it can be aimed at
6.9.
* commit '58661a30f1bcc748475ffd9be6d2fc9e4e6be679':
riscv: Flush the instruction cache during SMP bringup
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | arch/riscv/kernel/smpboot.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index d41090fc320353..4b3c50da48ba1e 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -26,7 +26,7 @@ #include <linux/sched/task_stack.h> #include <linux/sched/mm.h> -#include <asm/cpufeature.h> +#include <asm/cacheflush.h> #include <asm/cpu_ops.h> #include <asm/irq.h> #include <asm/mmu_context.h> @@ -234,9 +234,10 @@ asmlinkage __visible void smp_callin(void) riscv_user_isa_enable(); /* - * Remote TLB flushes are ignored while the CPU is offline, so emit - * a local TLB flush right now just in case. + * Remote cache and TLB flushes are ignored while the CPU is offline, + * so flush them both right now just in case. */ + local_flush_icache_all(); local_flush_tlb_all(); complete(&cpu_running); /* |