diff options
| author | Stephen Rothwell <sfr@canb.auug.org.au> | 2024-05-02 11:43:29 +1000 |
|---|---|---|
| committer | Stephen Rothwell <sfr@canb.auug.org.au> | 2024-05-02 11:43:29 +1000 |
| commit | 2739072caaedc1431f619739af08bebcccf1ae31 (patch) | |
| tree | 8c5d2979fdaf79a988ad22195744fa6ae49e808e | |
| parent | 8242152f38fe7d86e89ae18236dfd67bc6c3ecff (diff) | |
| parent | 6f1923f54d77942376f47d05b08cddca19fc397f (diff) | |
| download | linux-next-history-2739072caaedc1431f619739af08bebcccf1ae31.tar.gz | |
Merge branch 'for-linux-next' of git://anongit.freedesktop.org/drm-intel
Notice: this object is not reachable from any branch.
Notice: this object is not reachable from any branch.
31 files changed, 1406 insertions, 1457 deletions
diff --git a/drivers/gpu/drm/drm_client.c b/drivers/gpu/drm/drm_client.c index 77fe217aeaf36..2803ac111bbd8 100644 --- a/drivers/gpu/drm/drm_client.c +++ b/drivers/gpu/drm/drm_client.c @@ -172,6 +172,18 @@ void drm_client_release(struct drm_client_dev *client) } EXPORT_SYMBOL(drm_client_release); +/** + * drm_client_dev_unregister - Unregister clients + * @dev: DRM device + * + * This function releases all clients by calling each client's + * &drm_client_funcs.unregister callback. The callback function + * is responsibe for releaseing all resources including the client + * itself. + * + * The helper drm_dev_unregister() calls this function. Drivers + * that use it don't need to call this function themselves. + */ void drm_client_dev_unregister(struct drm_device *dev) { struct drm_client_dev *client, *tmp; @@ -191,6 +203,7 @@ void drm_client_dev_unregister(struct drm_device *dev) } mutex_unlock(&dev->clientlist_mutex); } +EXPORT_SYMBOL(drm_client_dev_unregister); /** * drm_client_dev_hotplug - Send hotplug event to clients diff --git a/drivers/gpu/drm/i915/display/intel_audio_regs.h b/drivers/gpu/drm/i915/display/intel_audio_regs.h index 616e7b1275c4c..88ea2740365d6 100644 --- a/drivers/gpu/drm/i915/display/intel_audio_regs.h +++ b/drivers/gpu/drm/i915/display/intel_audio_regs.h @@ -148,4 +148,20 @@ #define HBLANK_START_COUNT_96 4 #define HBLANK_START_COUNT_128 5 +/* LPE Audio */ +#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) +#define I915_HDMI_LPE_AUDIO_SIZE 0x1000 + +#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) +#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) + +#define _VLV_AUD_PORT_EN_B_DBG 0x62F20 +#define _VLV_AUD_PORT_EN_C_DBG 0x62F30 +#define _VLV_AUD_PORT_EN_D_DBG 0x62F34 +#define VLV_AUD_PORT_EN_DBG(port) _MMIO_BASE_PORT3(VLV_DISPLAY_BASE, (port) - PORT_B, \ + _VLV_AUD_PORT_EN_B_DBG, \ + _VLV_AUD_PORT_EN_C_DBG, \ + _VLV_AUD_PORT_EN_D_DBG) +#define VLV_AMP_MUTE (1 << 1) + #endif /* __INTEL_AUDIO_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c index ca7112b32cb3e..d23163dc64d4a 100644 --- a/drivers/gpu/drm/i915/display/intel_color.c +++ b/drivers/gpu/drm/i915/display/intel_color.c @@ -616,19 +616,19 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc, struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); enum pipe pipe = crtc->pipe; - intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe), csc->coeff[1] << 16 | csc->coeff[0]); - intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe), csc->coeff[2]); - intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe), csc->coeff[4] << 16 | csc->coeff[3]); - intel_de_write_fw(dev_priv, PIPE_WGC_C12(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe), csc->coeff[5]); - intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe), csc->coeff[7] << 16 | csc->coeff[6]); - intel_de_write_fw(dev_priv, PIPE_WGC_C22(pipe), + intel_de_write_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe), csc->coeff[8]); } @@ -639,25 +639,25 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; u32 tmp; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe)); csc->coeff[0] = tmp & 0xffff; csc->coeff[1] = tmp >> 16; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe)); csc->coeff[2] = tmp & 0xffff; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(dev_priv, pipe)); csc->coeff[3] = tmp & 0xffff; csc->coeff[4] = tmp >> 16; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C12(dev_priv, pipe)); csc->coeff[5] = tmp & 0xffff; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C21_C20(dev_priv, pipe)); csc->coeff[6] = tmp & 0xffff; csc->coeff[7] = tmp >> 16; - tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(pipe)); + tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C22(dev_priv, pipe)); csc->coeff[8] = tmp & 0xffff; } @@ -1227,7 +1227,7 @@ static void i9xx_load_lut_8(struct intel_crtc *crtc, lut = blob->data; for (i = 0; i < 256; i++) - intel_de_write_fw(dev_priv, PALETTE(pipe, i), + intel_de_write_fw(dev_priv, PALETTE(dev_priv, pipe, i), i9xx_lut_8(&lut[i])); } @@ -1240,9 +1240,11 @@ static void i9xx_load_lut_10(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size - 1; i++) { - intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), + intel_de_write_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 0), i9xx_lut_10_ldw(&lut[i])); - intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), + intel_de_write_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 1), i9xx_lut_10_udw(&lut[i])); } } @@ -1274,9 +1276,11 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc, enum pipe pipe = crtc->pipe; for (i = 0; i < lut_size - 1; i++) { - intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 0), + intel_de_write_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 0), i965_lut_10p6_ldw(&lut[i])); - intel_de_write_fw(dev_priv, PALETTE(pipe, 2 * i + 1), + intel_de_write_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 1), i965_lut_10p6_udw(&lut[i])); } @@ -3150,7 +3154,8 @@ static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc) lut = blob->data; for (i = 0; i < LEGACY_LUT_LENGTH; i++) { - u32 val = intel_de_read_fw(dev_priv, PALETTE(pipe, i)); + u32 val = intel_de_read_fw(dev_priv, + PALETTE(dev_priv, pipe, i)); i9xx_lut_8_pack(&lut[i], val); } @@ -3176,8 +3181,10 @@ static struct drm_property_blob *i9xx_read_lut_10(struct intel_crtc *crtc) lut = blob->data; for (i = 0; i < lut_size - 1; i++) { - ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); - udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); + ldw = intel_de_read_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 0)); + udw = intel_de_read_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 1)); i9xx_lut_10_pack(&lut[i], ldw, udw); } @@ -3224,8 +3231,10 @@ static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc) lut = blob->data; for (i = 0; i < lut_size - 1; i++) { - u32 ldw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 0)); - u32 udw = intel_de_read_fw(dev_priv, PALETTE(pipe, 2 * i + 1)); + u32 ldw = intel_de_read_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 0)); + u32 udw = intel_de_read_fw(dev_priv, + PALETTE(dev_priv, pipe, 2 * i + 1)); i965_lut_10p6_pack(&lut[i], ldw, udw); } diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h index 9f4ae58f3e7e9..bb99ea5338429 100644 --- a/drivers/gpu/drm/i915/display/intel_color_regs.h +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h @@ -8,7 +8,35 @@ #include "intel_display_reg_defs.h" -/* legacy palette */ +/* GMCH palette */ +#define _PALETTE_A 0xa000 +#define _PALETTE_B 0xa800 +#define _CHV_PALETTE_C 0xc000 +/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ +#define PALETTE_RED_MASK REG_GENMASK(23, 16) +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0) +/* pre-i965 10bit interpolated mode ldw */ +#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) +#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) +#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) +/* pre-i965 10bit interpolated mode udw */ +#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) +#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) +#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) +#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) +#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) +#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) +#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) +#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) +#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) +#define PALETTE(dev_priv, pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ + _PICK_EVEN_2RANGES(pipe, 2, \ + _PALETTE_A, _PALETTE_B, \ + _CHV_PALETTE_C, _CHV_PALETTE_C) + \ + (i) * 4) + +/* ilk+ palette */ #define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_B 0x4a800 /* see PALETTE_* for the bits */ @@ -228,12 +256,12 @@ #define _PIPE_A_WGC_C21_C20 0x600C0 /* s2.10 */ #define _PIPE_A_WGC_C22 0x600C4 /* s2.10 */ -#define PIPE_WGC_C01_C00(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C01_C00) -#define PIPE_WGC_C02(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C02) -#define PIPE_WGC_C11_C10(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C11_C10) -#define PIPE_WGC_C12(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C12) -#define PIPE_WGC_C21_C20(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C21_C20) -#define PIPE_WGC_C22(pipe) _MMIO_TRANS2(pipe, _PIPE_A_WGC_C22) +#define PIPE_WGC_C01_C00(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00) +#define PIPE_WGC_C02(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02) +#define PIPE_WGC_C11_C10(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10) +#define PIPE_WGC_C12(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12) +#define PIPE_WGC_C21_C20(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20) +#define PIPE_WGC_C22(dev_priv, pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C22) /* pipe CSC & degamma/gamma LUTs on CHV */ #define _CGM_PIPE_A_CSC_COEFF01 (VLV_DISPLAY_BASE + 0x67900) diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c index b9434465d3a71..273323f30ae29 100644 --- a/drivers/gpu/drm/i915/display/intel_display.c +++ b/drivers/gpu/drm/i915/display/intel_display.c @@ -85,7 +85,6 @@ #include "intel_dvo.h" #include "intel_fb.h" #include "intel_fbc.h" -#include "intel_fbdev.h" #include "intel_fdi.h" #include "intel_fifo_underrun.h" #include "intel_frontbuffer.h" @@ -120,6 +119,7 @@ #include "skl_scaler.h" #include "skl_universal_plane.h" #include "skl_watermark.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_dsi.h" #include "vlv_dsi_pll.h" #include "vlv_dsi_regs.h" diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c index 1b24339e4ab66..89bd032ed995e 100644 --- a/drivers/gpu/drm/i915/display/intel_display_driver.c +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c @@ -11,6 +11,7 @@ #include <acpi/video.h> #include <drm/display/drm_dp_mst_helper.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_client.h> #include <drm/drm_mode_config.h> #include <drm/drm_privacy_screen_consumer.h> #include <drm/drm_probe_helper.h> @@ -98,7 +99,6 @@ void intel_display_driver_init_hw(struct drm_i915_private *i915) static const struct drm_mode_config_funcs intel_mode_funcs = { .fb_create = intel_user_framebuffer_create, .get_format_info = intel_fb_get_format_info, - .output_poll_changed = intel_fbdev_output_poll_changed, .mode_valid = intel_mode_valid, .atomic_check = intel_atomic_check, .atomic_commit = intel_atomic_commit, @@ -516,10 +516,6 @@ int intel_display_driver_probe(struct drm_i915_private *i915) intel_overlay_setup(i915); - ret = intel_fbdev_init(&i915->drm); - if (ret) - return ret; - /* Only enable hotplug handling once the fbdev is fully set up. */ intel_hpd_init(i915); @@ -547,16 +543,6 @@ void intel_display_driver_register(struct drm_i915_private *i915) intel_display_debugfs_register(i915); /* - * Some ports require correctly set-up hpd registers for - * detection to work properly (leading to ghost connected - * connector status), e.g. VGA on gm45. Hence we can only set - * up the initial fbdev config after hpd irqs are fully - * enabled. We do it last so that the async config cannot run - * before the connectors are registered. - */ - intel_fbdev_initial_config_async(i915); - - /* * We need to coordinate the hotplugs with the asynchronous * fbdev configuration, for which we use the * fbdev->async_cookie. @@ -564,6 +550,8 @@ void intel_display_driver_register(struct drm_i915_private *i915) drm_kms_helper_poll_init(&i915->drm); intel_hpd_poll_disable(i915); + intel_fbdev_setup(i915); + intel_display_device_info_print(DISPLAY_INFO(i915), DISPLAY_RUNTIME_INFO(i915), &p); } @@ -599,9 +587,6 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915) */ intel_hpd_poll_fini(i915); - /* poll work can call into fbdev, hence clean that up afterwards */ - intel_fbdev_fini(i915); - intel_unregister_dsm_handler(); /* flush any delayed tasks or pending work */ @@ -640,7 +625,8 @@ void intel_display_driver_unregister(struct drm_i915_private *i915) if (!HAS_DISPLAY(i915)) return; - intel_fbdev_unregister(i915); + drm_client_dev_unregister(&i915->drm); + /* * After flushing the fbdev (incl. a late async config which * will have delayed queuing of a hotplug event), then flush diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c index e8a6e53fd5511..83f616097a29a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c @@ -27,6 +27,7 @@ #include "intel_tc.h" #include "intel_vga.h" #include "skl_watermark.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" #include "vlv_sideband_reg.h" @@ -1442,9 +1443,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, vlv_dpio_write(dev_priv, phy, CHV_CMN_DW28, tmp); if (id == VLV_DISP_PW_DPIO_CMN_BC) { - tmp = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW6_CH1); + tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW6_CH1); tmp |= DPIO_DYNPWRDOWNEN_CH1; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW6_CH1, tmp); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW6_CH1, tmp); } else { /* * Force the non-existing CL2 off. BXT does this @@ -1520,9 +1521,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi return; if (ch == DPIO_CH0) - reg = _CHV_CMN_DW0_CH0; + reg = CHV_CMN_DW0_CH0; else - reg = _CHV_CMN_DW6_CH1; + reg = CHV_CMN_DW6_CH1; vlv_dpio_get(dev_priv); val = vlv_dpio_read(dev_priv, phy, reg); @@ -1553,10 +1554,11 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi } if (ch == DPIO_CH0) - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0; + actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH0 | + DPIO_ALLDL_POWERDOWN_CH0, val); else - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1; - actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN; + actual = REG_FIELD_GET(DPIO_ANYDL_POWERDOWN_CH1 | + DPIO_ALLDL_POWERDOWN_CH1, val); drm_WARN(&dev_priv->drm, actual != expected, "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n", diff --git a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h index 2f07b7afa3bfe..b83ad06f2ea7a 100644 --- a/drivers/gpu/drm/i915/display/intel_display_reg_defs.h +++ b/drivers/gpu/drm/i915/display/intel_display_reg_defs.h @@ -29,21 +29,21 @@ #define _MMIO_PLL(pll, a, b) _MMIO(_PLL(pll, a, b)) #define _MMIO_PHY(phy, a, b) _MMIO(_PHY(phy, a, b)) -#define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) -#define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) +#define _MMIO_BASE_PIPE3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) +#define _MMIO_BASE_PORT3(base, pipe, a, b, c) _MMIO((base) + _PICK_EVEN_2RANGES(pipe, 1, a, a, b, c)) /* * Device info offset array based helpers for groups of registers with unevenly * spaced base offsets. */ -#define _MMIO_PIPE2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->pipe_offsets[(pipe)] - \ - DISPLAY_INFO(dev_priv)->pipe_offsets[PIPE_A] + \ - DISPLAY_MMIO_BASE(dev_priv) + (reg)) -#define _MMIO_TRANS2(tran, reg) _MMIO(DISPLAY_INFO(dev_priv)->trans_offsets[(tran)] - \ - DISPLAY_INFO(dev_priv)->trans_offsets[TRANSCODER_A] + \ - DISPLAY_MMIO_BASE(dev_priv) + (reg)) -#define _MMIO_CURSOR2(pipe, reg) _MMIO(DISPLAY_INFO(dev_priv)->cursor_offsets[(pipe)] - \ - DISPLAY_INFO(dev_priv)->cursor_offsets[PIPE_A] + \ - DISPLAY_MMIO_BASE(dev_priv) + (reg)) +#define _MMIO_PIPE2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->pipe_offsets[(pipe)] - \ + DISPLAY_INFO(display)->pipe_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE(display) + (reg)) +#define _MMIO_TRANS2(display, tran, reg) _MMIO(DISPLAY_INFO(display)->trans_offsets[(tran)] - \ + DISPLAY_INFO(display)->trans_offsets[TRANSCODER_A] + \ + DISPLAY_MMIO_BASE(display) + (reg)) +#define _MMIO_CURSOR2(display, pipe, reg) _MMIO(DISPLAY_INFO(display)->cursor_offsets[(pipe)] - \ + DISPLAY_INFO(display)->cursor_offsets[PIPE_A] + \ + DISPLAY_MMIO_BASE(display) + (reg)) #endif /* __INTEL_DISPLAY_REG_DEFS_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c index c72b76b61dff8..d20e4e9cf7f7b 100644 --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c @@ -30,6 +30,7 @@ #include "intel_display_types.h" #include "intel_dp.h" #include "intel_dpio_phy.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" /** @@ -719,9 +720,8 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; int i; @@ -758,7 +758,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, for (i = 0; i < crtc_state->lane_count; i++) { val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW4(ch, i)); val &= ~DPIO_SWING_DEEMPH9P5_MASK; - val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; + val |= DPIO_SWING_DEEMPH9P5(deemph_reg_value); vlv_dpio_write(dev_priv, phy, CHV_TX_DW4(ch, i), val); } @@ -767,15 +767,15 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder, val = vlv_dpio_read(dev_priv, phy, CHV_TX_DW2(ch, i)); val &= ~DPIO_SWING_MARGIN000_MASK; - val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; + val |= DPIO_SWING_MARGIN000(margin_reg_value); /* * Supposedly this value shouldn't matter when unique transition * scale is disabled, but in fact it does matter. Let's just * always program the same value and hope it's OK. */ - val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); - val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; + val &= ~DPIO_UNIQ_TRANS_SCALE_MASK; + val |= DPIO_UNIQ_TRANS_SCALE(0x9a); vlv_dpio_write(dev_priv, phy, CHV_TX_DW2(ch, i), val); } @@ -814,9 +814,9 @@ void chv_data_lane_soft_reset(struct intel_encoder *encoder, bool reset) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + struct intel_digital_port *dig_port = enc_to_dig_port(encoder); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); u32 val; val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW0(ch)); @@ -861,7 +861,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); enum pipe pipe = crtc->pipe; unsigned int lane_mask = intel_dp_unused_lane_mask(crtc_state->lane_count); @@ -884,39 +884,39 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, /* program left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA1_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA1_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); if (ch == DPIO_CH0) val |= CHV_BUFLEFTENA2_FORCE; if (ch == DPIO_CH1) val |= CHV_BUFRIGHTENA2_FORCE; - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } /* program clock channel usage */ val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(ch)); - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; - if (pipe != PIPE_B) - val &= ~CHV_PCS_USEDCLKCHANNEL; + val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; + if (pipe == PIPE_B) + val |= DPIO_PCS_USEDCLKCHANNEL; else - val |= CHV_PCS_USEDCLKCHANNEL; + val &= ~DPIO_PCS_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, VLV_PCS01_DW8(ch), val); if (crtc_state->lane_count > 2) { val = vlv_dpio_read(dev_priv, phy, VLV_PCS23_DW8(ch)); - val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; - if (pipe != PIPE_B) - val &= ~CHV_PCS_USEDCLKCHANNEL; + val |= DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; + if (pipe == PIPE_B) + val |= DPIO_PCS_USEDCLKCHANNEL; else - val |= CHV_PCS_USEDCLKCHANNEL; + val &= ~DPIO_PCS_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, VLV_PCS23_DW8(ch), val); } @@ -926,10 +926,10 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder, * pick the CL based on the port. */ val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW19(ch)); - if (pipe != PIPE_B) - val &= ~CHV_CMN_USEDCLKCHANNEL; - else + if (pipe == PIPE_B) val |= CHV_CMN_USEDCLKCHANNEL; + else + val &= ~CHV_CMN_USEDCLKCHANNEL; vlv_dpio_write(dev_priv, phy, CHV_CMN_DW19(ch), val); vlv_dpio_put(dev_priv); @@ -941,9 +941,8 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, struct intel_dp *intel_dp = enc_to_intel_dp(encoder); struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); int data, i, stagger; u32 val; @@ -964,11 +963,10 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, for (i = 0; i < crtc_state->lane_count; i++) { /* Set the upar bit */ if (crtc_state->lane_count == 1) - data = 0x0; + data = 0; else - data = (i == 1) ? 0x0 : 0x1; - vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), - data << DPIO_UPAR_SHIFT); + data = (i == 1) ? 0 : DPIO_UPAR; + vlv_dpio_write(dev_priv, phy, CHV_TX_DW14(ch, i), data); } /* Data lane stagger programming */ @@ -1030,21 +1028,21 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder, const struct intel_crtc_state *old_crtc_state) { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); + enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder)); enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; - enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; vlv_dpio_get(dev_priv); /* disable left/right clock distribution */ if (pipe != PIPE_B) { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW5_CH0); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW5_CH0); val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW5_CH0, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW5_CH0, val); } else { - val = vlv_dpio_read(dev_priv, phy, _CHV_CMN_DW1_CH1); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW1_CH1); val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); - vlv_dpio_write(dev_priv, phy, _CHV_CMN_DW1_CH1, val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW1_CH1, val); } vlv_dpio_put(dev_priv); @@ -1068,24 +1066,23 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder, { struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_digital_port *dig_port = enc_to_dig_port(encoder); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(port), demph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW2(port), + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), 0x00000000); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4_GRP(ch), demph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW2_GRP(ch), uniqtranscale_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW3(port), 0x0C782040); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW3_GRP(ch), 0x0C782040); if (tx3_demph) - vlv_dpio_write(dev_priv, phy, VLV_TX3_DW4(port), tx3_demph); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW4(ch, 3), tx3_demph); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11(port), 0x00030000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9(port), preemph_reg_value); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW11_GRP(ch), 0x00030000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW9_GRP(ch), preemph_reg_value); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW5_GRP(ch), DPIO_TX_OCALINIT_EN); vlv_dpio_put(dev_priv); } @@ -1095,26 +1092,25 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); /* Program Tx lane resets to default */ vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), - DPIO_PCS_TX_LANE2_RESET | - DPIO_PCS_TX_LANE1_RESET); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), - DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | - DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | - (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | - DPIO_PCS_CLK_SOFT_RESET); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), + DPIO_PCS_TX_LANE2_RESET | + DPIO_PCS_TX_LANE1_RESET); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), + DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | + DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | + DPIO_PCS_CLK_DATAWIDTH_8_10 | + DPIO_PCS_CLK_SOFT_RESET); /* Fix up inter-pair skew failure */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12(port), 0x00750f00); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW11(port), 0x00001500); - vlv_dpio_write(dev_priv, phy, VLV_TX_DW14(port), 0x40400000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW12_GRP(ch), 0x00750f00); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW11_GRP(ch), 0x00001500); + vlv_dpio_write(dev_priv, phy, VLV_TX_DW14_GRP(ch), 0x40400000); vlv_dpio_put(dev_priv); } @@ -1126,26 +1122,23 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); enum pipe pipe = crtc->pipe; - enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; vlv_dpio_get(dev_priv); /* Enable clock channels for this port */ - val = vlv_dpio_read(dev_priv, phy, VLV_PCS01_DW8(port)); - val = 0; - if (pipe) - val |= (1<<21); - else - val &= ~(1<<21); - val |= 0x001000c4; - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8(port), val); + val = DPIO_PCS_USEDCLKCHANNEL_OVRRIDE; + if (pipe == PIPE_B) + val |= DPIO_PCS_USEDCLKCHANNEL; + val |= 0xc4; + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW8_GRP(ch), val); /* Program lane clock */ - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14(port), 0x00760018); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23(port), 0x00400888); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW14_GRP(ch), 0x00760018); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW23_GRP(ch), 0x00400888); vlv_dpio_put(dev_priv); } @@ -1155,12 +1148,11 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder, { struct intel_digital_port *dig_port = enc_to_dig_port(encoder); struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); - struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); - enum dpio_channel port = vlv_dig_port_to_channel(dig_port); - enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); + enum dpio_phy phy = vlv_dig_port_to_phy(dig_port); vlv_dpio_get(dev_priv); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0(port), 0x00000000); - vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1(port), 0x00e00060); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW0_GRP(ch), 0x00000000); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW1_GRP(ch), 0x00e00060); vlv_dpio_put(dev_priv); } diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 49274d6327160..a981f45facb3e 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -20,6 +20,7 @@ #include "intel_panel.h" #include "intel_pps.h" #include "intel_snps_phy.h" +#include "vlv_dpio_phy_regs.h" #include "vlv_sideband.h" struct intel_dpll_funcs { @@ -512,25 +513,26 @@ void vlv_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - struct dpll clock; - u32 mdiv; int refclk = 100000; + struct dpll clock; + u32 tmp; /* In case of DSI, DPLL will not be used */ if ((hw_state->dpll & DPLL_VCO_ENABLE) == 0) return; vlv_dpio_get(dev_priv); - mdiv = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(crtc->pipe)); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW3(ch)); vlv_dpio_put(dev_priv); - clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; - clock.m2 = mdiv & DPIO_M2DIV_MASK; - clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; - clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; - clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; + clock.m1 = REG_FIELD_GET(DPIO_M1_DIV_MASK, tmp); + clock.m2 = REG_FIELD_GET(DPIO_M2_DIV_MASK, tmp); + clock.n = REG_FIELD_GET(DPIO_N_DIV_MASK, tmp); + clock.p1 = REG_FIELD_GET(DPIO_P1_DIV_MASK, tmp); + clock.p2 = REG_FIELD_GET(DPIO_P2_DIV_MASK, tmp); crtc_state->port_clock = vlv_calc_dpll_params(refclk, &clock); } @@ -539,7 +541,7 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum dpio_channel port = vlv_pipe_to_channel(crtc->pipe); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; struct dpll clock; @@ -551,20 +553,20 @@ void chv_crtc_clock_get(struct intel_crtc_state *crtc_state) return; vlv_dpio_get(dev_priv); - cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(port)); - pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(port)); - pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(port)); - pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(port)); - pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); + cmn_dw13 = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW13(ch)); + pll_dw0 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW0(ch)); + pll_dw1 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW1(ch)); + pll_dw2 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW2(ch)); + pll_dw3 = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); vlv_dpio_put(dev_priv); - clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; - clock.m2 = (pll_dw0 & 0xff) << 22; + clock.m1 = REG_FIELD_GET(DPIO_CHV_M1_DIV_MASK, pll_dw1) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; + clock.m2 = REG_FIELD_GET(DPIO_CHV_M2_DIV_MASK, pll_dw0) << 22; if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN) - clock.m2 |= pll_dw2 & 0x3fffff; - clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; - clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; - clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; + clock.m2 |= REG_FIELD_GET(DPIO_CHV_M2_FRAC_DIV_MASK, pll_dw2); + clock.n = REG_FIELD_GET(DPIO_CHV_N_DIV_MASK, pll_dw1); + clock.p1 = REG_FIELD_GET(DPIO_CHV_P1_DIV_MASK, cmn_dw13); + clock.p2 = REG_FIELD_GET(DPIO_CHV_P2_DIV_MASK, cmn_dw13); crtc_state->port_clock = chv_calc_dpll_params(refclk, &clock); } @@ -1867,121 +1869,117 @@ void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) } static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, - enum dpio_phy phy) + enum dpio_phy phy, enum dpio_channel ch) { - u32 reg_val; + u32 tmp; /* * PLLB opamp always calibrates to max value of 0x3f, force enable it * and set it to a reasonable value instead. */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); - reg_val &= 0xffffff00; - reg_val |= 0x00000030; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); + tmp &= 0xffffff00; + tmp |= 0x00000030; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); - reg_val &= 0x00ffffff; - reg_val |= 0x8c000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp &= 0x00ffffff; + tmp |= 0x8c000000; + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1)); - reg_val &= 0xffffff00; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW17(ch)); + tmp &= 0xffffff00; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW17(ch), tmp); - reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13); - reg_val &= 0x00ffffff; - reg_val |= 0xb0000000; - vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11); + tmp &= 0x00ffffff; + tmp |= 0xb0000000; + vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, tmp); } static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); + const struct dpll *clock = &crtc_state->dpll; + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); enum pipe pipe = crtc->pipe; - u32 mdiv; - u32 bestn, bestm1, bestm2, bestp1, bestp2; - u32 coreclk, reg_val; + u32 tmp, coreclk; vlv_dpio_get(dev_priv); - bestn = crtc_state->dpll.n; - bestm1 = crtc_state->dpll.m1; - bestm2 = crtc_state->dpll.m2; - bestp1 = crtc_state->dpll.p1; - bestp2 = crtc_state->dpll.p2; - /* See eDP HDMI DPIO driver vbios notes doc */ /* PLL B needs special handling */ if (pipe == PIPE_B) - vlv_pllb_recal_opamp(dev_priv, phy); + vlv_pllb_recal_opamp(dev_priv, phy, ch); /* Set up Tx target for periodic Rcomp update */ - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9_BCAST, 0x0100000f); + vlv_dpio_write(dev_priv, phy, VLV_PCS_DW17_BCAST, 0x0100000f); /* Disable target IRef on PLL */ - reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW8(pipe)); - reg_val &= 0x00ffffff; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW8(pipe), reg_val); + tmp = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW16(ch)); + tmp &= 0x00ffffff; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW16(ch), tmp); /* Disable fast lock */ vlv_dpio_write(dev_priv, phy, VLV_CMN_DW0, 0x610); /* Set idtafcrecal before PLL is enabled */ - mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); - mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); - mdiv |= ((bestn << DPIO_N_SHIFT)); - mdiv |= (1 << DPIO_K_SHIFT); + tmp = DPIO_M1_DIV(clock->m1) | + DPIO_M2_DIV(clock->m2) | + DPIO_P1_DIV(clock->p1) | + DPIO_P2_DIV(clock->p2) | + DPIO_N_DIV(clock->n) | + DPIO_K_DIV(1); /* * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, * but we don't support that). * Note: don't use the DAC post divider as it seems unstable. */ - mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); + tmp |= DPIO_S1_DIV(DPIO_S1_DIV_HDMIDP); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); - mdiv |= DPIO_ENABLE_CALIBRATION; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(pipe), mdiv); + tmp |= DPIO_ENABLE_CALIBRATION; + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW3(ch), tmp); /* Set HBR and RBR LPF coefficients */ if (crtc_state->port_clock == 162000 || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), 0x009f0003); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW10(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW18(ch), 0x00d0000f); if (intel_crtc_has_dp_encoder(crtc_state)) { /* Use SSC source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df40000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df70000); } else { /* HDMI or VGA */ /* Use bend source */ if (pipe == PIPE_A) - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df70000); else - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(pipe), + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW5(ch), 0x0df40000); } - coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(pipe)); + coreclk = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW7(ch)); coreclk = (coreclk & 0x0000ff00) | 0x01c00000; if (intel_crtc_has_dp_encoder(crtc_state)) coreclk |= 0x01000000; - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(pipe), coreclk); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW7(ch), coreclk); - vlv_dpio_write(dev_priv, phy, VLV_PLL_DW11(pipe), 0x87871000); + vlv_dpio_write(dev_priv, phy, VLV_PLL_DW19(ch), 0x87871000); vlv_dpio_put(dev_priv); } @@ -2030,93 +2028,87 @@ static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); - enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); + const struct dpll *clock = &crtc_state->dpll; + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); - u32 loopfilter, tribuf_calcntr; - u32 bestm2, bestp1, bestp2, bestm2_frac; - u32 dpio_val; - int vco; - - bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; - bestm2 = crtc_state->dpll.m2 >> 22; - bestp1 = crtc_state->dpll.p1; - bestp2 = crtc_state->dpll.p2; - vco = crtc_state->dpll.vco; - dpio_val = 0; - loopfilter = 0; + u32 tmp, loopfilter, tribuf_calcntr; + u32 m2_frac; + + m2_frac = clock->m2 & 0x3fffff; vlv_dpio_get(dev_priv); /* p1 and p2 divider */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(port), - 5 << DPIO_CHV_S1_DIV_SHIFT | - bestp1 << DPIO_CHV_P1_DIV_SHIFT | - bestp2 << DPIO_CHV_P2_DIV_SHIFT | - 1 << DPIO_CHV_K_DIV_SHIFT); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW13(ch), + DPIO_CHV_S1_DIV(5) | + DPIO_CHV_P1_DIV(clock->p1) | + DPIO_CHV_P2_DIV(clock->p2) | + DPIO_CHV_K_DIV(1)); /* Feedback post-divider - m2 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(port), bestm2); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW0(ch), + DPIO_CHV_M2_DIV(clock->m2 >> 22)); /* Feedback refclk divider - n and m1 */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(port), - DPIO_CHV_M1_DIV_BY_2 | - 1 << DPIO_CHV_N_DIV_SHIFT); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW1(ch), + DPIO_CHV_M1_DIV(DPIO_CHV_M1_DIV_BY_2) | + DPIO_CHV_N_DIV(1)); /* M2 fraction division */ - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(port), bestm2_frac); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW2(ch), + DPIO_CHV_M2_FRAC_DIV(m2_frac)); /* M2 fraction division enable */ - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(port)); - dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); - dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); - if (bestm2_frac) - dpio_val |= DPIO_CHV_FRAC_DIV_EN; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(port), dpio_val); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW3(ch)); + tmp &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); + tmp |= DPIO_CHV_FEEDFWD_GAIN(2); + if (m2_frac) + tmp |= DPIO_CHV_FRAC_DIV_EN; + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW3(ch), tmp); /* Program digital lock detect threshold */ - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(port)); - dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | - DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); - dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); - if (!bestm2_frac) - dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(port), dpio_val); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW9(ch)); + tmp &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | + DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); + tmp |= DPIO_CHV_INT_LOCK_THRESHOLD(0x5); + if (!m2_frac) + tmp |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW9(ch), tmp); /* Loop filter */ - if (vco == 5400000) { - loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); + if (clock->vco == 5400000) { + loopfilter = DPIO_CHV_PROP_COEFF(0x3) | + DPIO_CHV_INT_COEFF(0x8) | + DPIO_CHV_GAIN_CTRL(0x1); tribuf_calcntr = 0x9; - } else if (vco <= 6200000) { - loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + } else if (clock->vco <= 6200000) { + loopfilter = DPIO_CHV_PROP_COEFF(0x5) | + DPIO_CHV_INT_COEFF(0xB) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0x9; - } else if (vco <= 6480000) { - loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + } else if (clock->vco <= 6480000) { + loopfilter = DPIO_CHV_PROP_COEFF(0x4) | + DPIO_CHV_INT_COEFF(0x9) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0x8; } else { /* Not supported. Apply the same limits as in the max case */ - loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); - loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); - loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); + loopfilter = DPIO_CHV_PROP_COEFF(0x4) | + DPIO_CHV_INT_COEFF(0x9) | + DPIO_CHV_GAIN_CTRL(0x3); tribuf_calcntr = 0; } - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(port), loopfilter); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW6(ch), loopfilter); - dpio_val = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(port)); - dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; - dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); - vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(port), dpio_val); + tmp = vlv_dpio_read(dev_priv, phy, CHV_PLL_DW8(ch)); + tmp &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; + tmp |= DPIO_CHV_TDC_TARGET_CNT(tribuf_calcntr); + vlv_dpio_write(dev_priv, phy, CHV_PLL_DW8(ch), tmp); /* AFC Recal */ - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), - vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)) | - DPIO_AFC_RECAL); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), + vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)) | + DPIO_AFC_RECAL); vlv_dpio_put(dev_priv); } @@ -2126,17 +2118,17 @@ static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); const struct i9xx_dpll_hw_state *hw_state = &crtc_state->dpll_hw_state.i9xx; - enum pipe pipe = crtc->pipe; - enum dpio_channel port = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(crtc->pipe); enum dpio_phy phy = vlv_pipe_to_phy(crtc->pipe); + enum pipe pipe = crtc->pipe; u32 tmp; vlv_dpio_get(dev_priv); /* Enable back the 10bit clock to display controller */ - tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); + tmp = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); tmp |= DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), tmp); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), tmp); vlv_dpio_put(dev_priv); @@ -2255,7 +2247,7 @@ void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) { - enum dpio_channel port = vlv_pipe_to_channel(pipe); + enum dpio_channel ch = vlv_pipe_to_channel(pipe); enum dpio_phy phy = vlv_pipe_to_phy(pipe); u32 val; @@ -2273,9 +2265,9 @@ void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) vlv_dpio_get(dev_priv); /* Disable 10bit clock to display controller */ - val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(port)); + val = vlv_dpio_read(dev_priv, phy, CHV_CMN_DW14(ch)); val &= ~DPIO_DCLKP_EN; - vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(port), val); + vlv_dpio_write(dev_priv, phy, CHV_CMN_DW14(ch), val); vlv_dpio_put(dev_priv); } diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c index 7c4d2b2bf20b1..151dcd0c45b60 100644 --- a/drivers/gpu/drm/i915/display/intel_fbc.c +++ b/drivers/gpu/drm/i915/display/intel_fbc.c @@ -54,6 +54,7 @@ #include "intel_display_trace.h" #include "intel_display_types.h" #include "intel_fbc.h" +#include "intel_fbc_regs.h" #include "intel_frontbuffer.h" #define for_each_fbc_id(__dev_priv, __fbc_id) \ diff --git a/drivers/gpu/drm/i915/display/intel_fbc_regs.h b/drivers/gpu/drm/i915/display/intel_fbc_regs.h new file mode 100644 index 0000000000000..ae0699c3c2fea --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_fbc_regs.h @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2024 Intel Corporation */ + +#ifndef __INTEL_FBC_REGS__ +#define __INTEL_FBC_REGS__ + +#include "intel_display_reg_defs.h" + +#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ +#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ +#define FBC_CONTROL _MMIO(0x3208) +#define FBC_CTL_EN REG_BIT(31) +#define FBC_CTL_PERIODIC REG_BIT(30) +#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) +#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) +#define FBC_CTL_STOP_ON_MOD REG_BIT(15) +#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ +#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ +#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) +#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) +#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) +#define FBC_COMMAND _MMIO(0x320c) +#define FBC_CMD_COMPRESS REG_BIT(0) +#define FBC_STATUS _MMIO(0x3210) +#define FBC_STAT_COMPRESSING REG_BIT(31) +#define FBC_STAT_COMPRESSED REG_BIT(30) +#define FBC_STAT_MODIFIED REG_BIT(29) +#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) +#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ +#define FBC_CTL_FENCE_DBL REG_BIT(4) +#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) +#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) +#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) +#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) +#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) +#define FBC_CTL_CPU_FENCE_EN REG_BIT(1) +#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) +#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) +#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ +#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ +#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) +#define FBC_MOD_NUM_VALID REG_BIT(0) +#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ +#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ +#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) +#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) +#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) +#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) + +#define FBC_LL_SIZE (1536) + +#define DPFC_CB_BASE _MMIO(0x3200) +#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) +#define DPFC_CONTROL _MMIO(0x3208) +#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) +#define DPFC_CTL_EN REG_BIT(31) +#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ +#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ +#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ +#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) +#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ +#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ +#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ +#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) +#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ +#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ +#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ +#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) +#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) +#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) +#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) +#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) +#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) +#define DPFC_RECOMP_CTL _MMIO(0x320c) +#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) +#define DPFC_RECOMP_STALL_EN REG_BIT(27) +#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) +#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) +#define DPFC_STATUS _MMIO(0x3210) +#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) +#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) +#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) +#define DPFC_STATUS2 _MMIO(0x3214) +#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) +#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) +#define DPFC_FENCE_YOFF _MMIO(0x3218) +#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) +#define DPFC_CHICKEN _MMIO(0x3224) +#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) +#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ +#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ +#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ +#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ +#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ + +#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) +#define FBC_STRIDE_OVERRIDE REG_BIT(15) +#define FBC_STRIDE_MASK REG_GENMASK(14, 0) +#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) + +#define ILK_FBC_RT_BASE _MMIO(0x2128) +#define ILK_FBC_RT_VALID REG_BIT(0) +#define SNB_FBC_FRONT_BUFFER REG_BIT(1) + +#define SNB_DPFC_CTL_SA _MMIO(0x100100) +#define SNB_DPFC_FENCE_EN REG_BIT(29) +#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) +#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) +#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) + +#define IVB_FBC_RT_BASE _MMIO(0x7020) +#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) + +#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) +#define FBC_REND_NUKE REG_BIT(2) +#define FBC_REND_CACHE_CLEAN REG_BIT(1) + +#endif /* __INTEL_FBC_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.c b/drivers/gpu/drm/i915/display/intel_fbdev.c index 43855c6c35099..bda702c2cab8e 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.c +++ b/drivers/gpu/drm/i915/display/intel_fbdev.c @@ -24,7 +24,6 @@ * David Airlie */ -#include <linux/async.h> #include <linux/console.h> #include <linux/delay.h> #include <linux/errno.h> @@ -39,6 +38,7 @@ #include <linux/vga_switcheroo.h> #include <drm/drm_crtc.h> +#include <drm/drm_crtc_helper.h> #include <drm/drm_fb_helper.h> #include <drm/drm_fourcc.h> #include <drm/drm_gem_framebuffer_helper.h> @@ -58,7 +58,6 @@ struct intel_fbdev { struct intel_framebuffer *fb; struct i915_vma *vma; unsigned long vma_flags; - async_cookie_t cookie; int preferred_bpp; /* Whether or not fbdev hpd processing is temporarily suspended */ @@ -135,6 +134,26 @@ static int intel_fbdev_mmap(struct fb_info *info, struct vm_area_struct *vma) return i915_gem_fb_mmap(obj, vma); } +static void intel_fbdev_fb_destroy(struct fb_info *info) +{ + struct drm_fb_helper *fb_helper = info->par; + struct intel_fbdev *ifbdev = container_of(fb_helper, struct intel_fbdev, helper); + + drm_fb_helper_fini(&ifbdev->helper); + + /* + * We rely on the object-free to release the VMA pinning for + * the info->screen_base mmaping. Leaking the VMA is simpler than + * trying to rectify all the possible error paths leading here. + */ + intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags); + drm_framebuffer_remove(&ifbdev->fb->base); + + drm_client_release(&fb_helper->client); + drm_fb_helper_unprepare(&ifbdev->helper); + kfree(ifbdev); +} + __diag_push(); __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for fb ops"); @@ -147,6 +166,7 @@ static const struct fb_ops intelfb_ops = { .fb_pan_display = intel_fbdev_pan_display, __FB_DEFAULT_DEFERRED_OPS_DRAW(intel_fbdev), .fb_mmap = intel_fbdev_mmap, + .fb_destroy = intel_fbdev_fb_destroy, }; __diag_pop(); @@ -158,7 +178,6 @@ static int intelfb_create(struct drm_fb_helper *helper, struct intel_framebuffer *intel_fb = ifbdev->fb; struct drm_device *dev = helper->dev; struct drm_i915_private *dev_priv = to_i915(dev); - struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev); const struct i915_gtt_view view = { .type = I915_GTT_VIEW_NORMAL, }; @@ -250,7 +269,7 @@ static int intelfb_create(struct drm_fb_helper *helper, ifbdev->vma_flags = flags; intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref); - vga_switcheroo_client_fb_set(pdev, info); + return 0; out_unpin: @@ -276,25 +295,6 @@ static const struct drm_fb_helper_funcs intel_fb_helper_funcs = { .fb_dirty = intelfb_dirty, }; -static void intel_fbdev_destroy(struct intel_fbdev *ifbdev) -{ - /* We rely on the object-free to release the VMA pinning for - * the info->screen_base mmaping. Leaking the VMA is simpler than - * trying to rectify all the possible error paths leading here. - */ - - drm_fb_helper_fini(&ifbdev->helper); - - if (ifbdev->vma) - intel_unpin_fb_vma(ifbdev->vma, ifbdev->vma_flags); - - if (ifbdev->fb) - drm_framebuffer_remove(&ifbdev->fb->base); - - drm_fb_helper_unprepare(&ifbdev->helper); - kfree(ifbdev); -} - /* * Build an intel_fbdev struct using a BIOS allocated framebuffer, if possible. * The core display code will have read out the current plane configuration, @@ -458,93 +458,6 @@ static void intel_fbdev_suspend_worker(struct work_struct *work) true); } -int intel_fbdev_init(struct drm_device *dev) -{ - struct drm_i915_private *dev_priv = to_i915(dev); - struct intel_fbdev *ifbdev; - int ret; - - if (drm_WARN_ON(dev, !HAS_DISPLAY(dev_priv))) - return -ENODEV; - - ifbdev = kzalloc(sizeof(struct intel_fbdev), GFP_KERNEL); - if (ifbdev == NULL) - return -ENOMEM; - - mutex_init(&ifbdev->hpd_lock); - drm_fb_helper_prepare(dev, &ifbdev->helper, 32, &intel_fb_helper_funcs); - - if (intel_fbdev_init_bios(dev, ifbdev)) - ifbdev->helper.preferred_bpp = ifbdev->preferred_bpp; - else - ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp; - - ret = drm_fb_helper_init(dev, &ifbdev->helper); - if (ret) { - kfree(ifbdev); - return ret; - } - - dev_priv->display.fbdev.fbdev = ifbdev; - INIT_WORK(&dev_priv->display.fbdev.suspend_work, intel_fbdev_suspend_worker); - - return 0; -} - -static void intel_fbdev_initial_config(void *data, async_cookie_t cookie) -{ - struct intel_fbdev *ifbdev = data; - - /* Due to peculiar init order wrt to hpd handling this is separate. */ - if (drm_fb_helper_initial_config(&ifbdev->helper)) - intel_fbdev_unregister(to_i915(ifbdev->helper.dev)); -} - -void intel_fbdev_initial_config_async(struct drm_i915_private *dev_priv) -{ - struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev; - - if (!ifbdev) - return; - - ifbdev->cookie = async_schedule(intel_fbdev_initial_config, ifbdev); -} - -static void intel_fbdev_sync(struct intel_fbdev *ifbdev) -{ - if (!ifbdev->cookie) - return; - - /* Only serialises with all preceding async calls, hence +1 */ - async_synchronize_cookie(ifbdev->cookie + 1); - ifbdev->cookie = 0; -} - -void intel_fbdev_unregister(struct drm_i915_private *dev_priv) -{ - struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev; - - if (!ifbdev) - return; - - intel_fbdev_set_suspend(&dev_priv->drm, FBINFO_STATE_SUSPENDED, true); - - if (!current_is_async()) - intel_fbdev_sync(ifbdev); - - drm_fb_helper_unregister_info(&ifbdev->helper); -} - -void intel_fbdev_fini(struct drm_i915_private *dev_priv) -{ - struct intel_fbdev *ifbdev = fetch_and_zero(&dev_priv->display.fbdev.fbdev); - - if (!ifbdev) - return; - - intel_fbdev_destroy(ifbdev); -} - /* Suspends/resumes fbdev processing of incoming HPD events. When resuming HPD * processing, fbdev will perform a full connector reprobe if a hotplug event * was received while HPD was suspended. @@ -627,15 +540,13 @@ set_suspend: intel_fbdev_hpd_set_suspend(dev_priv, state); } -void intel_fbdev_output_poll_changed(struct drm_device *dev) +static int intel_fbdev_output_poll_changed(struct drm_device *dev) { struct intel_fbdev *ifbdev = to_i915(dev)->display.fbdev.fbdev; bool send_hpd; if (!ifbdev) - return; - - intel_fbdev_sync(ifbdev); + return -EINVAL; mutex_lock(&ifbdev->hpd_lock); send_hpd = !ifbdev->hpd_suspended; @@ -644,21 +555,137 @@ void intel_fbdev_output_poll_changed(struct drm_device *dev) if (send_hpd && (ifbdev->vma || ifbdev->helper.deferred_setup)) drm_fb_helper_hotplug_event(&ifbdev->helper); + + return 0; } -void intel_fbdev_restore_mode(struct drm_i915_private *dev_priv) +static int intel_fbdev_restore_mode(struct drm_i915_private *dev_priv) { struct intel_fbdev *ifbdev = dev_priv->display.fbdev.fbdev; + int ret; if (!ifbdev) - return; + return -EINVAL; - intel_fbdev_sync(ifbdev); if (!ifbdev->vma) + return -ENOMEM; + + ret = drm_fb_helper_restore_fbdev_mode_unlocked(&ifbdev->helper); + if (ret) + return ret; + + intel_fbdev_invalidate(ifbdev); + + return 0; +} + +/* + * Fbdev client and struct drm_client_funcs + */ + +static void intel_fbdev_client_unregister(struct drm_client_dev *client) +{ + struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); + struct drm_device *dev = fb_helper->dev; + struct pci_dev *pdev = to_pci_dev(dev->dev); + + if (fb_helper->info) { + vga_switcheroo_client_fb_set(pdev, NULL); + drm_fb_helper_unregister_info(fb_helper); + } else { + drm_fb_helper_unprepare(fb_helper); + drm_client_release(&fb_helper->client); + kfree(fb_helper); + } +} + +static int intel_fbdev_client_restore(struct drm_client_dev *client) +{ + struct drm_i915_private *dev_priv = to_i915(client->dev); + int ret; + + ret = intel_fbdev_restore_mode(dev_priv); + if (ret) + return ret; + + vga_switcheroo_process_delayed_switch(); + + return 0; +} + +static int intel_fbdev_client_hotplug(struct drm_client_dev *client) +{ + struct drm_fb_helper *fb_helper = drm_fb_helper_from_client(client); + struct drm_device *dev = client->dev; + struct pci_dev *pdev = to_pci_dev(dev->dev); + int ret; + + if (dev->fb_helper) + return intel_fbdev_output_poll_changed(dev); + + ret = drm_fb_helper_init(dev, fb_helper); + if (ret) + goto err_drm_err; + + ret = drm_fb_helper_initial_config(fb_helper); + if (ret) + goto err_drm_fb_helper_fini; + + vga_switcheroo_client_fb_set(pdev, fb_helper->info); + + return 0; + +err_drm_fb_helper_fini: + drm_fb_helper_fini(fb_helper); +err_drm_err: + drm_err(dev, "Failed to setup i915 fbdev emulation (ret=%d)\n", ret); + return ret; +} + +static const struct drm_client_funcs intel_fbdev_client_funcs = { + .owner = THIS_MODULE, + .unregister = intel_fbdev_client_unregister, + .restore = intel_fbdev_client_restore, + .hotplug = intel_fbdev_client_hotplug, +}; + +void intel_fbdev_setup(struct drm_i915_private *i915) +{ + struct drm_device *dev = &i915->drm; + struct intel_fbdev *ifbdev; + int ret; + + if (!HAS_DISPLAY(i915)) return; - if (drm_fb_helper_restore_fbdev_mode_unlocked(&ifbdev->helper) == 0) - intel_fbdev_invalidate(ifbdev); + ifbdev = kzalloc(sizeof(*ifbdev), GFP_KERNEL); + if (!ifbdev) + return; + drm_fb_helper_prepare(dev, &ifbdev->helper, 32, &intel_fb_helper_funcs); + + i915->display.fbdev.fbdev = ifbdev; + INIT_WORK(&i915->display.fbdev.suspend_work, intel_fbdev_suspend_worker); + mutex_init(&ifbdev->hpd_lock); + if (intel_fbdev_init_bios(dev, ifbdev)) + ifbdev->helper.preferred_bpp = ifbdev->preferred_bpp; + else + ifbdev->preferred_bpp = ifbdev->helper.preferred_bpp; + + ret = drm_client_init(dev, &ifbdev->helper.client, "intel-fbdev", + &intel_fbdev_client_funcs); + if (ret) { + drm_err(dev, "Failed to register client: %d\n", ret); + goto err_drm_fb_helper_unprepare; + } + + drm_client_register(&ifbdev->helper.client); + + return; + +err_drm_fb_helper_unprepare: + drm_fb_helper_unprepare(&ifbdev->helper); + mutex_destroy(&ifbdev->hpd_lock); + kfree(ifbdev); } struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) diff --git a/drivers/gpu/drm/i915/display/intel_fbdev.h b/drivers/gpu/drm/i915/display/intel_fbdev.h index 04fd523a50232..08de2d5b34338 100644 --- a/drivers/gpu/drm/i915/display/intel_fbdev.h +++ b/drivers/gpu/drm/i915/display/intel_fbdev.h @@ -14,29 +14,11 @@ struct intel_fbdev; struct intel_framebuffer; #ifdef CONFIG_DRM_FBDEV_EMULATION -int intel_fbdev_init(struct drm_device *dev); -void intel_fbdev_initial_config_async(struct drm_i915_private *dev_priv); -void intel_fbdev_unregister(struct drm_i915_private *dev_priv); -void intel_fbdev_fini(struct drm_i915_private *dev_priv); +void intel_fbdev_setup(struct drm_i915_private *dev_priv); void intel_fbdev_set_suspend(struct drm_device *dev, int state, bool synchronous); -void intel_fbdev_output_poll_changed(struct drm_device *dev); -void intel_fbdev_restore_mode(struct drm_i915_private *dev_priv); struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev); #else -static inline int intel_fbdev_init(struct drm_device *dev) -{ - return 0; -} - -static inline void intel_fbdev_initial_config_async(struct drm_i915_private *dev_priv) -{ -} - -static inline void intel_fbdev_unregister(struct drm_i915_private *dev_priv) -{ -} - -static inline void intel_fbdev_fini(struct drm_i915_private *dev_priv) +static inline void intel_fbdev_setup(struct drm_i915_private *dev_priv) { } @@ -44,13 +26,6 @@ static inline void intel_fbdev_set_suspend(struct drm_device *dev, int state, bo { } -static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) -{ -} - -static inline void intel_fbdev_restore_mode(struct drm_i915_private *i915) -{ -} static inline struct intel_framebuffer *intel_fbdev_framebuffer(struct intel_fbdev *fbdev) { return NULL; diff --git a/drivers/gpu/drm/i915/display/intel_lpe_audio.c b/drivers/gpu/drm/i915/display/intel_lpe_audio.c index 5863763de5306..93e6cac9a4eda 100644 --- a/drivers/gpu/drm/i915/display/intel_lpe_audio.c +++ b/drivers/gpu/drm/i915/display/intel_lpe_audio.c @@ -72,7 +72,7 @@ #include "i915_drv.h" #include "i915_irq.h" -#include "i915_reg.h" +#include "intel_audio_regs.h" #include "intel_de.h" #include "intel_lpe_audio.h" #include "intel_pci_config.h" diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h index b004672d1deb4..ebc22999572cf 100644 --- a/drivers/gpu/drm/i915/display/intel_psr_regs.h +++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h @@ -9,7 +9,7 @@ #include "intel_display_reg_defs.h" #include "intel_dp_aux_regs.h" -#define TRANS_EXITLINE(trans) _MMIO_TRANS2((trans), _TRANS_EXITLINE_A) +#define TRANS_EXITLINE(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_EXITLINE_A) #define EXITLINE_ENABLE REG_BIT(31) #define EXITLINE_MASK REG_GENMASK(12, 0) #define EXITLINE_SHIFT 0 @@ -23,7 +23,7 @@ #define HSW_SRD_CTL _MMIO(0x64800) #define _SRD_CTL_A 0x60800 #define _SRD_CTL_EDP 0x6f800 -#define EDP_PSR_CTL(tran) _MMIO_TRANS2(tran, _SRD_CTL_A) +#define EDP_PSR_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_CTL_A) #define EDP_PSR_ENABLE REG_BIT(31) #define BDW_PSR_SINGLE_FRAME REG_BIT(30) #define EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK REG_BIT(29) /* SW can't modify */ @@ -66,8 +66,8 @@ #define EDP_PSR_IIR _MMIO(0x64838) #define _PSR_IMR_A 0x60814 #define _PSR_IIR_A 0x60818 -#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(tran, _PSR_IMR_A) -#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(tran, _PSR_IIR_A) +#define TRANS_PSR_IMR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IMR_A) +#define TRANS_PSR_IIR(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_IIR_A) #define _EDP_PSR_TRANS_SHIFT(trans) ((trans) == TRANSCODER_EDP ? \ 0 : ((trans) - TRANSCODER_A + 1) * 8) #define TGL_PSR_MASK REG_GENMASK(2, 0) @@ -86,7 +86,7 @@ #define HSW_SRD_AUX_CTL _MMIO(0x64810) #define _SRD_AUX_CTL_A 0x60810 #define _SRD_AUX_CTL_EDP 0x6f810 -#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(tran, _SRD_AUX_CTL_A) +#define EDP_PSR_AUX_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_CTL_A) #define EDP_PSR_AUX_CTL_TIME_OUT_MASK DP_AUX_CH_CTL_TIME_OUT_MASK #define EDP_PSR_AUX_CTL_MESSAGE_SIZE_MASK DP_AUX_CH_CTL_MESSAGE_SIZE_MASK #define EDP_PSR_AUX_CTL_PRECHARGE_2US_MASK DP_AUX_CH_CTL_PRECHARGE_2US_MASK @@ -96,12 +96,12 @@ #define HSW_SRD_AUX_DATA(i) _MMIO(0x64814 + (i) * 4) /* 5 registers */ #define _SRD_AUX_DATA_A 0x60814 #define _SRD_AUX_DATA_EDP 0x6f814 -#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ +#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(dev_priv, tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */ #define HSW_SRD_STATUS _MMIO(0x64840) #define _SRD_STATUS_A 0x60840 #define _SRD_STATUS_EDP 0x6f840 -#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(tran, _SRD_STATUS_A) +#define EDP_PSR_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_STATUS_A) #define EDP_PSR_STATUS_STATE_MASK REG_GENMASK(31, 29) #define EDP_PSR_STATUS_STATE_IDLE REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 0) #define EDP_PSR_STATUS_STATE_SRDONACK REG_FIELD_PREP(EDP_PSR_STATUS_STATE_MASK, 1) @@ -126,14 +126,14 @@ #define HSW_SRD_PERF_CNT _MMIO(0x64844) #define _SRD_PERF_CNT_A 0x60844 #define _SRD_PERF_CNT_EDP 0x6f844 -#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(tran, _SRD_PERF_CNT_A) +#define EDP_PSR_PERF_CNT(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_PERF_CNT_A) #define EDP_PSR_PERF_CNT_MASK REG_GENMASK(23, 0) /* PSR_MASK on SKL+ */ #define HSW_SRD_DEBUG _MMIO(0x64860) #define _SRD_DEBUG_A 0x60860 #define _SRD_DEBUG_EDP 0x6f860 -#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(tran, _SRD_DEBUG_A) +#define EDP_PSR_DEBUG(tran) _MMIO_TRANS2(dev_priv, tran, _SRD_DEBUG_A) #define EDP_PSR_DEBUG_MASK_MAX_SLEEP REG_BIT(28) #define EDP_PSR_DEBUG_MASK_LPSP REG_BIT(27) #define EDP_PSR_DEBUG_MASK_MEMUP REG_BIT(26) @@ -153,7 +153,7 @@ #define _PSR2_CTL_A 0x60900 #define _PSR2_CTL_EDP 0x6f900 -#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(tran, _PSR2_CTL_A) +#define EDP_PSR2_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_CTL_A) #define EDP_PSR2_ENABLE REG_BIT(31) #define EDP_SU_TRACK_ENABLE REG_BIT(30) /* up to adl-p */ #define TGL_EDP_PSR2_BLOCK_COUNT_MASK REG_BIT(28) @@ -195,7 +195,7 @@ #define _PSR_EVENT_TRANS_C 0x62848 #define _PSR_EVENT_TRANS_D 0x63848 #define _PSR_EVENT_TRANS_EDP 0x6f848 -#define PSR_EVENT(tran) _MMIO_TRANS2(tran, _PSR_EVENT_TRANS_A) +#define PSR_EVENT(tran) _MMIO_TRANS2(dev_priv, tran, _PSR_EVENT_TRANS_A) #define PSR_EVENT_PSR2_WD_TIMER_EXPIRE REG_BIT(17) #define PSR_EVENT_PSR2_DISABLED REG_BIT(16) #define PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN REG_BIT(15) @@ -215,13 +215,13 @@ #define _PSR2_STATUS_A 0x60940 #define _PSR2_STATUS_EDP 0x6f940 -#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(tran, _PSR2_STATUS_A) +#define EDP_PSR2_STATUS(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_STATUS_A) #define EDP_PSR2_STATUS_STATE_MASK REG_GENMASK(31, 28) #define EDP_PSR2_STATUS_STATE_DEEP_SLEEP REG_FIELD_PREP(EDP_PSR2_STATUS_STATE_MASK, 0x8) #define _PSR2_SU_STATUS_A 0x60914 #define _PSR2_SU_STATUS_EDP 0x6f914 -#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4) +#define _PSR2_SU_STATUS(tran, index) _MMIO_TRANS2(dev_priv, tran, _PSR2_SU_STATUS_A + (index) * 4) #define PSR2_SU_STATUS(tran, frame) (_PSR2_SU_STATUS(tran, (frame) / 3)) #define PSR2_SU_STATUS_SHIFT(frame) (((frame) % 3) * 10) #define PSR2_SU_STATUS_MASK(frame) (0x3ff << PSR2_SU_STATUS_SHIFT(frame)) @@ -229,7 +229,7 @@ #define _PSR2_MAN_TRK_CTL_A 0x60910 #define _PSR2_MAN_TRK_CTL_EDP 0x6f910 -#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(tran, _PSR2_MAN_TRK_CTL_A) +#define PSR2_MAN_TRK_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PSR2_MAN_TRK_CTL_A) #define PSR2_MAN_TRK_CTL_ENABLE REG_BIT(31) #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK REG_GENMASK(30, 21) #define PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR(val) REG_FIELD_PREP(PSR2_MAN_TRK_CTL_SU_REGION_START_ADDR_MASK, val) @@ -249,7 +249,7 @@ /* PSR2 Early transport */ #define _PIPE_SRCSZ_ERLY_TPT_A 0x70074 -#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(trans, _PIPE_SRCSZ_ERLY_TPT_A) +#define PIPE_SRCSZ_ERLY_TPT(trans) _MMIO_TRANS2(dev_priv, trans, _PIPE_SRCSZ_ERLY_TPT_A) #define _SEL_FETCH_PLANE_BASE_1_A 0x70890 #define _SEL_FETCH_PLANE_BASE_2_A 0x708B0 @@ -297,7 +297,7 @@ _SEL_FETCH_PLANE_BASE_1_A) #define _ALPM_CTL_A 0x60950 -#define ALPM_CTL(tran) _MMIO_TRANS2(tran, _ALPM_CTL_A) +#define ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL_A) #define ALPM_CTL_ALPM_ENABLE REG_BIT(31) #define ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(30) #define ALPM_CTL_LOBF_ENABLE REG_BIT(29) @@ -321,7 +321,7 @@ #define ALPM_CTL_AUX_LESS_WAKE_TIME(val) REG_FIELD_PREP(ALPM_CTL_AUX_LESS_WAKE_TIME_MASK, val) #define _ALPM_CTL2_A 0x60954 -#define ALPM_CTL2(tran) _MMIO_TRANS2(tran, _ALPM_CTL2_A) +#define ALPM_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _ALPM_CTL2_A) #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK REG_GENMASK(28, 24) #define ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY(val) REG_FIELD_PREP(ALPM_CTL2_SWITCH_TO_ACTIVE_LATENCY_MASK, val) #define ALPM_CTL2_AUX_LESS_WAKE_TIME_EXTENSION_MASK REG_GENMASK(19, 16) @@ -335,7 +335,7 @@ #define ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES(val) REG_FIELD_PREP(ALPM_CTL2_NUMBER_AUX_LESS_ML_PHY_SLEEP_SEQUENCES_MASK, val) #define _PORT_ALPM_CTL_A 0x16fa2c -#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_CTL_A) +#define PORT_ALPM_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_CTL_A) #define PORT_ALPM_CTL_ALPM_AUX_LESS_ENABLE REG_BIT(31) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK REG_GENMASK(23, 20) #define PORT_ALPM_CTL_MAX_PHY_SWING_SETUP(val) REG_FIELD_PREP(PORT_ALPM_CTL_MAX_PHY_SWING_SETUP_MASK, val) @@ -345,7 +345,7 @@ #define PORT_ALPM_CTL_SILENCE_PERIOD(val) REG_FIELD_PREP(PORT_ALPM_CTL_SILENCE_PERIOD_MASK, val) #define _PORT_ALPM_LFPS_CTL_A 0x16fa30 -#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(tran, _PORT_ALPM_LFPS_CTL_A) +#define PORT_ALPM_LFPS_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _PORT_ALPM_LFPS_CTL_A) #define PORT_ALPM_LFPS_CTL_LFPS_START_POLARITY REG_BIT(31) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MASK REG_GENMASK(27, 24) #define PORT_ALPM_LFPS_CTL_LFPS_CYCLE_COUNT_MIN 7 diff --git a/drivers/gpu/drm/i915/display/intel_sprite.c b/drivers/gpu/drm/i915/display/intel_sprite.c index d7b440c8caefe..36a253a19c74f 100644 --- a/drivers/gpu/drm/i915/display/intel_sprite.c +++ b/drivers/gpu/drm/i915/display/intel_sprite.c @@ -47,6 +47,7 @@ #include "intel_fb.h" #include "intel_frontbuffer.h" #include "intel_sprite.h" +#include "intel_sprite_regs.h" static char sprite_name(struct drm_i915_private *i915, enum pipe pipe, int sprite) { diff --git a/drivers/gpu/drm/i915/display/intel_sprite_regs.h b/drivers/gpu/drm/i915/display/intel_sprite_regs.h new file mode 100644 index 0000000000000..bb67705652b2a --- /dev/null +++ b/drivers/gpu/drm/i915/display/intel_sprite_regs.h @@ -0,0 +1,348 @@ +/* SPDX-License-Identifier: MIT */ +/* Copyright © 2024 Intel Corporation */ + +#ifndef __INTEL_SPRITE_REGS__ +#define __INTEL_SPRITE_REGS__ + +#include "intel_display_reg_defs.h" + +#define _DVSACNTR 0x72180 +#define DVS_ENABLE REG_BIT(31) +#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) +#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) +#define DVS_FORMAT_MASK REG_GENMASK(26, 25) +#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) +#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) +#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) +#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) +#define DVS_PIPE_CSC_ENABLE REG_BIT(24) +#define DVS_SOURCE_KEY REG_BIT(22) +#define DVS_RGB_ORDER_XBGR REG_BIT(20) +#define DVS_YUV_FORMAT_BT709 REG_BIT(18) +#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) +#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) +#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) +#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) +#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) +#define DVS_ROTATE_180 REG_BIT(15) +#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) +#define DVS_TILED REG_BIT(10) +#define DVS_DEST_KEY REG_BIT(2) +#define _DVSALINOFF 0x72184 +#define _DVSASTRIDE 0x72188 +#define _DVSAPOS 0x7218c +#define DVS_POS_Y_MASK REG_GENMASK(31, 16) +#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) +#define DVS_POS_X_MASK REG_GENMASK(15, 0) +#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) +#define _DVSASIZE 0x72190 +#define DVS_HEIGHT_MASK REG_GENMASK(31, 16) +#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) +#define DVS_WIDTH_MASK REG_GENMASK(15, 0) +#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) +#define _DVSAKEYVAL 0x72194 +#define _DVSAKEYMSK 0x72198 +#define _DVSASURF 0x7219c +#define DVS_ADDR_MASK REG_GENMASK(31, 12) +#define _DVSAKEYMAXVAL 0x721a0 +#define _DVSATILEOFF 0x721a4 +#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) +#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) +#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) +#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) +#define _DVSASURFLIVE 0x721ac +#define _DVSAGAMC_G4X 0x721e0 /* g4x */ +#define _DVSASCALE 0x72204 +#define DVS_SCALE_ENABLE REG_BIT(31) +#define DVS_FILTER_MASK REG_GENMASK(30, 29) +#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) +#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) +#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) +#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ +#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) +#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) +#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) +#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) +#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) +#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ +#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ + +#define _DVSBCNTR 0x73180 +#define _DVSBLINOFF 0x73184 +#define _DVSBSTRIDE 0x73188 +#define _DVSBPOS 0x7318c +#define _DVSBSIZE 0x73190 +#define _DVSBKEYVAL 0x73194 +#define _DVSBKEYMSK 0x73198 +#define _DVSBSURF 0x7319c +#define _DVSBKEYMAXVAL 0x731a0 +#define _DVSBTILEOFF 0x731a4 +#define _DVSBSURFLIVE 0x731ac +#define _DVSBGAMC_G4X 0x731e0 /* g4x */ +#define _DVSBSCALE 0x73204 +#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ +#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ + +#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) +#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) +#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) +#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) +#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) +#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) +#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) +#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) +#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) +#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) +#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) +#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) +#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ +#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ +#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ + +#define _SPRA_CTL 0x70280 +#define SPRITE_ENABLE REG_BIT(31) +#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) +#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) +#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) +#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) +#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) +#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) +#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) +#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) +#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ +#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) +#define SPRITE_SOURCE_KEY REG_BIT(22) +#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ +#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) +#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ +#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) +#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) +#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) +#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) +#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) +#define SPRITE_ROTATE_180 REG_BIT(15) +#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) +#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) +#define SPRITE_TILED REG_BIT(10) +#define SPRITE_DEST_KEY REG_BIT(2) +#define _SPRA_LINOFF 0x70284 +#define _SPRA_STRIDE 0x70288 +#define _SPRA_POS 0x7028c +#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) +#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) +#define SPRITE_POS_X_MASK REG_GENMASK(15, 0) +#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) +#define _SPRA_SIZE 0x70290 +#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) +#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) +#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) +#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) +#define _SPRA_KEYVAL 0x70294 +#define _SPRA_KEYMSK 0x70298 +#define _SPRA_SURF 0x7029c +#define SPRITE_ADDR_MASK REG_GENMASK(31, 12) +#define _SPRA_KEYMAX 0x702a0 +#define _SPRA_TILEOFF 0x702a4 +#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) +#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) +#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) +#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) +#define _SPRA_OFFSET 0x702a4 +#define _SPRA_SURFLIVE 0x702ac +#define _SPRA_SCALE 0x70304 +#define SPRITE_SCALE_ENABLE REG_BIT(31) +#define SPRITE_FILTER_MASK REG_GENMASK(30, 29) +#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) +#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) +#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) +#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ +#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) +#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) +#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) +#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) +#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) +#define _SPRA_GAMC 0x70400 +#define _SPRA_GAMC16 0x70440 +#define _SPRA_GAMC17 0x7044c + +#define _SPRB_CTL 0x71280 +#define _SPRB_LINOFF 0x71284 +#define _SPRB_STRIDE 0x71288 +#define _SPRB_POS 0x7128c +#define _SPRB_SIZE 0x71290 +#define _SPRB_KEYVAL 0x71294 +#define _SPRB_KEYMSK 0x71298 +#define _SPRB_SURF 0x7129c +#define _SPRB_KEYMAX 0x712a0 +#define _SPRB_TILEOFF 0x712a4 +#define _SPRB_OFFSET 0x712a4 +#define _SPRB_SURFLIVE 0x712ac +#define _SPRB_SCALE 0x71304 +#define _SPRB_GAMC 0x71400 +#define _SPRB_GAMC16 0x71440 +#define _SPRB_GAMC17 0x7144c + +#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) +#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) +#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) +#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) +#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) +#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) +#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) +#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) +#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) +#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) +#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) +#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) +#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ +#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ +#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ +#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) + +#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) +#define SP_ENABLE REG_BIT(31) +#define SP_PIPE_GAMMA_ENABLE REG_BIT(30) +#define SP_FORMAT_MASK REG_GENMASK(29, 26) +#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) +#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) +#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) +#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) +#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) +#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) +#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) +#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ +#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ +#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) +#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) +#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ +#define SP_SOURCE_KEY REG_BIT(22) +#define SP_YUV_FORMAT_BT709 REG_BIT(18) +#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) +#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) +#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) +#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) +#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) +#define SP_ROTATE_180 REG_BIT(15) +#define SP_TILED REG_BIT(10) +#define SP_MIRROR REG_BIT(8) /* CHV pipe B */ +#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) +#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) +#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) +#define SP_POS_Y_MASK REG_GENMASK(31, 16) +#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) +#define SP_POS_X_MASK REG_GENMASK(15, 0) +#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) +#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) +#define SP_HEIGHT_MASK REG_GENMASK(31, 16) +#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) +#define SP_WIDTH_MASK REG_GENMASK(15, 0) +#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) +#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) +#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) +#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) +#define SP_ADDR_MASK REG_GENMASK(31, 12) +#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) +#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) +#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) +#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) +#define SP_OFFSET_X_MASK REG_GENMASK(15, 0) +#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) +#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) +#define SP_CONST_ALPHA_ENABLE REG_BIT(31) +#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) +#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) +#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) +#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) +#define SP_CONTRAST_MASK REG_GENMASK(26, 18) +#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ +#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) +#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ +#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) +#define SP_SH_SIN_MASK REG_GENMASK(26, 16) +#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ +#define SP_SH_COS_MASK REG_GENMASK(9, 0) +#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ +#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) + +#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) +#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) +#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) +#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) +#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) +#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) +#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) +#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) +#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) +#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) +#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) +#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) +#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) +#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) +#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) + +#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ + _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) +#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ + _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) + +#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) +#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) +#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) +#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) +#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) +#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) +#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) +#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) +#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) +#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) +#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) +#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) +#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) +#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) +#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ + +/* + * CHV pipe B sprite CSC + * + * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| + * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| + * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| + */ +#define _MMIO_CHV_SPCSC(plane_id, reg) \ + _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) + +#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) +#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) +#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) +#define SPCSC_OOFF_MASK REG_GENMASK(26, 16) +#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ +#define SPCSC_IOFF_MASK REG_GENMASK(10, 0) +#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ + +#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) +#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) +#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) +#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) +#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) +#define SPCSC_C1_MASK REG_GENMASK(30, 16) +#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ +#define SPCSC_C0_MASK REG_GENMASK(14, 0) +#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ + +#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) +#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) +#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) +#define SPCSC_IMAX_MASK REG_GENMASK(26, 16) +#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ +#define SPCSC_IMIN_MASK REG_GENMASK(10, 0) +#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ + +#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) +#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) +#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) +#define SPCSC_OMAX_MASK REG_GENMASK(25, 16) +#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ +#define SPCSC_OMIN_MASK REG_GENMASK(9, 0) +#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ + +#endif /* __INTEL_SPRITE_REGS__ */ diff --git a/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h new file mode 100644 index 0000000000000..2b83f334b1ffe --- /dev/null +++ b/drivers/gpu/drm/i915/display/vlv_dpio_phy_regs.h @@ -0,0 +1,309 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2023 Intel Corporation + */ + +#ifndef __VLV_DPIO_PHY_REGS_H__ +#define __VLV_DPIO_PHY_REGS_H__ + +#include "intel_display_reg_defs.h" + +#define _VLV_CMN(dw) (0x8100 + (dw) * 4) +#define _CHV_CMN(cl, dw) (0x8100 - (cl) * 0x80 + (dw) * 4) +#define _VLV_PLL(ch, dw) (0x8000 + (ch) * 0x20 + (dw) * 4) /* dw 0-7,16-23 */ +#define _CHV_PLL(ch, dw) (0x8000 + (ch) * 0x180 + (dw) * 4) +#define _VLV_REF(dw) (0x80a0 + ((dw) - 8) * 4) /* dw 8-15 */ +#define _VLV_PCS(ch, spline, dw) (0x200 + (ch) * 0x2400 + (spline) * 0x200 + (dw) * 4) +#define _VLV_PCS_GRP(ch, dw) (0x8200 + (ch) * 0x200 + (dw) * 4) +#define _VLV_PCS_BCAST(dw) (0xc000 + (dw) * 4) +#define _VLV_TX(ch, lane, dw) (0x80 + (ch) * 0x2400 + (lane) * 0x200 + (dw) * 4) +#define _VLV_TX_GRP(ch, dw) (0x8280 + (ch) * 0x200 + (dw) * 4) +#define _VLV_TX_BCAST(dw) (0xc080 + (dw) * 4) + +/* + * Per pipe/PLL DPIO regs + */ +#define VLV_PLL_DW3(ch) _VLV_PLL((ch), 3) +#define DPIO_S1_DIV_MASK REG_GENMASK(30, 28) +#define DPIO_S1_DIV(s1) REG_FIELD_PREP(DPIO_S1_DIV_MASK, (s1)) +#define DPIO_S1_DIV_DAC 0 /* 10, DAC 25-225M rate */ +#define DPIO_S1_DIV_HDMIDP 1 /* 5, DAC 225-400M rate */ +#define DPIO_S1_DIV_LVDS1 2 /* 14 */ +#define DPIO_S1_DIV_LVDS2 3 /* 7 */ +#define DPIO_K_DIV_MASK REG_GENMASK(27, 24) +#define DPIO_K_DIV(k) REG_FIELD_PREP(DPIO_K_DIV_MASK, (k)) +#define DPIO_P1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_P1_DIV(p1) REG_FIELD_PREP(DPIO_P1_DIV_MASK, (p1)) +#define DPIO_P2_DIV_MASK REG_GENMASK(20, 16) +#define DPIO_P2_DIV(p2) REG_FIELD_PREP(DPIO_P2_DIV_MASK, (p2)) +#define DPIO_N_DIV_MASK REG_GENMASK(15, 12) +#define DPIO_N_DIV(n) REG_FIELD_PREP(DPIO_N_DIV_MASK, (n)) +#define DPIO_ENABLE_CALIBRATION REG_BIT(11) +#define DPIO_M1_DIV_MASK REG_GENMASK(10, 8) +#define DPIO_M1_DIV(m1) REG_FIELD_PREP(DPIO_M1_DIV_MASK, (m1)) +#define DPIO_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_M2_DIV(m2) REG_FIELD_PREP(DPIO_M2_DIV_MASK, (m2)) + +#define VLV_PLL_DW5(ch) _VLV_PLL((ch), 5) +#define DPIO_REFSEL_OVERRIDE REG_BIT(27) +#define DPIO_PLL_MODESEL_MASK REG_GENMASK(26, 24) +#define DPIO_BIAS_CURRENT_CTL_MASK REG_GENMASK(22, 20) /* always 0x7 */ +#define DPIO_PLL_REFCLK_SEL_MASK REG_GENMASK(17, 16) +#define DPIO_DRIVER_CTL_MASK REG_GENMASK(15, 12) /* always set to 0x8 */ +#define DPIO_CLK_BIAS_CTL_MASK REG_GENMASK(11, 8) /* always set to 0x5 */ + +#define VLV_PLL_DW7(ch) _VLV_PLL((ch), 7) + +#define VLV_PLL_DW16(ch) _VLV_PLL((ch), 16) + +#define VLV_PLL_DW17(ch) _VLV_PLL((ch), 17) + +#define VLV_PLL_DW18(ch) _VLV_PLL((ch), 18) + +#define VLV_PLL_DW19(ch) _VLV_PLL((ch), 19) + +#define VLV_REF_DW11 _VLV_REF(11) + +#define VLV_CMN_DW0 _VLV_CMN(0) + +/* + * Per DDI channel DPIO regs + */ +#define VLV_PCS_DW0_GRP(ch) _VLV_PCS_GRP((ch), 0) +#define VLV_PCS01_DW0(ch) _VLV_PCS((ch), 0, 0) +#define VLV_PCS23_DW0(ch) _VLV_PCS((ch), 1, 0) +#define DPIO_PCS_TX_LANE2_RESET REG_BIT(16) +#define DPIO_PCS_TX_LANE1_RESET REG_BIT(7) +#define DPIO_LEFT_TXFIFO_RST_MASTER2 REG_BIT(4) +#define DPIO_RIGHT_TXFIFO_RST_MASTER2 REG_BIT(3) + +#define VLV_PCS_DW1_GRP(ch) _VLV_PCS_GRP((ch), 1) +#define VLV_PCS01_DW1(ch) _VLV_PCS((ch), 0, 1) +#define VLV_PCS23_DW1(ch) _VLV_PCS((ch), 1, 1) +#define CHV_PCS_REQ_SOFTRESET_EN REG_BIT(23) +#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN REG_BIT(22) +#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN REG_BIT(21) +#define DPIO_PCS_CLK_DATAWIDTH_MASK REG_GENMASK(7, 6) +#define DPIO_PCS_CLK_DATAWIDTH_8_10 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 1) +#define DPIO_PCS_CLK_DATAWIDTH_16_20 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 2) +#define DPIO_PCS_CLK_DATAWIDTH_32_40 REG_FIELD_PREP(DPIO_PCS_CLK_DATAWIDTH_MASK, 3) +#define DPIO_PCS_CLK_SOFT_RESET REG_BIT(5) + +#define VLV_PCS_DW8_GRP(ch) _VLV_PCS_GRP((ch), 8) +#define VLV_PCS01_DW8(ch) _VLV_PCS((ch), 0, 8) +#define VLV_PCS23_DW8(ch) _VLV_PCS((ch), 1, 8) +#define DPIO_PCS_USEDCLKCHANNEL REG_BIT(21) +#define DPIO_PCS_USEDCLKCHANNEL_OVRRIDE REG_BIT(20) + +#define VLV_PCS_DW9_GRP(ch) _VLV_PCS_GRP((ch), 9) +#define VLV_PCS01_DW9(ch) _VLV_PCS((ch), 0, 9) +#define VLV_PCS23_DW9(ch) _VLV_PCS((ch), 1, 9) +#define DPIO_PCS_TX2MARGIN_MASK REG_GENMASK(15, 13) +#define DPIO_PCS_TX2MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 0) +#define DPIO_PCS_TX2MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX2MARGIN_MASK, 1) +#define DPIO_PCS_TX1MARGIN_MASK REG_GENMASK(12, 10) +#define DPIO_PCS_TX1MARGIN_000 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 0) +#define DPIO_PCS_TX1MARGIN_101 REG_FIELD_PREP(DPIO_PCS_TX1MARGIN_MASK, 1) + +#define VLV_PCS_DW10_GRP(ch) _VLV_PCS_GRP((ch), 10) +#define VLV_PCS01_DW10(ch) _VLV_PCS((ch), 0, 10) +#define VLV_PCS23_DW10(ch) _VLV_PCS((ch), 1, 10) +#define DPIO_PCS_SWING_CALC_TX1_TX3 REG_BIT(31) +#define DPIO_PCS_SWING_CALC_TX0_TX2 REG_BIT(30) +#define DPIO_PCS_TX2DEEMP_MASK REG_GENMASK(27, 24) +#define DPIO_PCS_TX2DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 0) +#define DPIO_PCS_TX2DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX2DEEMP_MASK, 2) +#define DPIO_PCS_TX1DEEMP_MASK REG_GENMASK(19, 16) +#define DPIO_PCS_TX1DEEMP_9P5 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 0) +#define DPIO_PCS_TX1DEEMP_6P0 REG_FIELD_PREP(DPIO_PCS_TX1DEEMP_MASK, 2) + +#define VLV_PCS_DW11_GRP(ch) _VLV_PCS_GRP((ch), 11) +#define VLV_PCS01_DW11(ch) _VLV_PCS((ch), 0, 11) +#define VLV_PCS23_DW11(ch) _VLV_PCS((ch), 1, 11) +#define DPIO_TX2_STAGGER_MASK_MASK REG_GENMASK(28, 24) +#define DPIO_TX2_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MASK_MASK, (x)) +#define DPIO_LANEDESKEW_STRAP_OVRD REG_BIT(3) +#define DPIO_LEFT_TXFIFO_RST_MASTER REG_BIT(1) +#define DPIO_RIGHT_TXFIFO_RST_MASTER REG_BIT(0) + +#define VLV_PCS_DW12_GRP(ch) _VLV_PCS_GRP((ch), 12) +#define VLV_PCS01_DW12(ch) _VLV_PCS((ch), 0, 12) +#define VLV_PCS23_DW12(ch) _VLV_PCS((ch), 1, 12) +#define DPIO_TX2_STAGGER_MULT_MASK REG_GENMASK(22, 20) +#define DPIO_TX2_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX2_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MULT_MASK REG_GENMASK(20, 16) +#define DPIO_TX1_STAGGER_MULT(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MULT_MASK, (x)) +#define DPIO_TX1_STAGGER_MASK_MASK REG_GENMASK(12, 8) +#define DPIO_TX1_STAGGER_MASK(x) REG_FIELD_PREP(DPIO_TX1_STAGGER_MASK_MASK, (x)) +#define DPIO_LANESTAGGER_STRAP_OVRD REG_BIT(6) +#define DPIO_LANESTAGGER_STRAP_MASK REG_GENMASK(4, 0) +#define DPIO_LANESTAGGER_STRAP(x) REG_FIELD_PREP(DPIO_LANESTAGGER_STRAP_MASK, (x)) + +#define VLV_PCS_DW14_GRP(ch) _VLV_PCS_GRP((ch), 14) +#define VLV_PCS01_DW14(ch) _VLV_PCS((ch), 0, 14) +#define VLV_PCS23_DW14(ch) _VLV_PCS((ch), 1, 14) + +#define VLV_PCS_DW17_BCAST _VLV_PCS_BCAST(17) +#define VLV_PCS_DW17_GRP(ch) _VLV_PCS_GRP((ch), 17) +#define VLV_PCS01_DW17(ch) _VLV_PCS((ch), 0, 17) +#define VLV_PCS23_DW17(ch) _VLV_PCS((ch), 1, 17) + +#define VLV_PCS_DW23_GRP(ch) _VLV_PCS_GRP((ch), 23) +#define VLV_PCS01_DW23(ch) _VLV_PCS((ch), 0, 23) +#define VLV_PCS23_DW23(ch) _VLV_PCS((ch), 1, 23) + +#define VLV_TX_DW2_GRP(ch) _VLV_TX_GRP((ch), 2) +#define VLV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) +#define DPIO_SWING_MARGIN000_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN000(x) REG_FIELD_PREP(DPIO_SWING_MARGIN000_MASK, (x)) +#define DPIO_UNIQ_TRANS_SCALE_MASK REG_GENMASK(15, 8) +#define DPIO_UNIQ_TRANS_SCALE(x) REG_FIELD_PREP(DPIO_UNIQ_TRANS_SCALE_MASK, (x)) + +#define VLV_TX_DW3_GRP(ch) _VLV_TX_GRP((ch), 3) +#define VLV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) +/* The following bit for CHV phy */ +#define DPIO_TX_UNIQ_TRANS_SCALE_EN REG_BIT(27) +#define DPIO_SWING_MARGIN101_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_MARGIN101(x) REG_FIELD_PREP(DPIO_SWING_MARGIN101_MASK, (x)) + +#define VLV_TX_DW4_GRP(ch) _VLV_TX_GRP((ch), 4) +#define VLV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) +#define DPIO_SWING_DEEMPH9P5_MASK REG_GENMASK(31, 24) +#define DPIO_SWING_DEEMPH9P5(x) REG_FIELD_PREP(DPIO_SWING_DEEMPH9P5_MASK, (x)) +#define DPIO_SWING_DEEMPH6P0_MASK REG_GENMASK(23, 16) +#define DPIO_SWING_DEEMPH6P0_SHIFT REG_FIELD_PREP(DPIO_SWING_DEEMPH6P0_MASK, (x)) + +#define VLV_TX_DW5_GRP(ch) _VLV_TX_GRP((ch), 5) +#define VLV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) +#define DPIO_TX_OCALINIT_EN REG_BIT(31) + +#define VLV_TX_DW11_GRP(ch) _VLV_TX_GRP((ch), 11) +#define VLV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) + +#define VLV_TX_DW14_GRP(ch) _VLV_TX_GRP((ch), 14) +#define VLV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) + +/* CHV dpPhy registers */ +#define CHV_PLL_DW0(ch) _CHV_PLL((ch), 0) +#define DPIO_CHV_M2_DIV_MASK REG_GENMASK(7, 0) +#define DPIO_CHV_M2_DIV(m2) REG_FIELD_PREP(DPIO_CHV_M2_DIV_MASK, (m2)) + +#define CHV_PLL_DW1(ch) _CHV_PLL((ch), 1) +#define DPIO_CHV_N_DIV_MASK REG_GENMASK(11, 8) +#define DPIO_CHV_N_DIV(n) REG_FIELD_PREP(DPIO_CHV_N_DIV_MASK, (n)) +#define DPIO_CHV_M1_DIV_MASK REG_GENMASK(2, 0) +#define DPIO_CHV_M1_DIV(m1) REG_FIELD_PREP(DPIO_CHV_M1_DIV_MASK, (m1)) +#define DPIO_CHV_M1_DIV_BY_2 0 + +#define CHV_PLL_DW2(ch) _CHV_PLL((ch), 2) +#define DPIO_CHV_M2_FRAC_DIV_MASK REG_GENMASK(21, 0) +#define DPIO_CHV_M2_FRAC_DIV(m2_frac) REG_FIELD_PREP(DPIO_CHV_M2_FRAC_DIV_MASK, (m2_frac)) + +#define CHV_PLL_DW3(ch) _CHV_PLL((ch), 3) +#define DPIO_CHV_FRAC_DIV_EN REG_BIT(16) +#define DPIO_CHV_SECOND_MOD REG_BIT(8) +#define DPIO_CHV_FEEDFWD_GAIN_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_FEEDFWD_GAIN(x) REG_FIELD_PREP(DPIO_CHV_FEEDFWD_GAIN_MASK, (x)) + +#define CHV_PLL_DW6(ch) _CHV_PLL((ch), 6) +#define DPIO_CHV_GAIN_CTRL_MASK REG_GENMASK(18, 16) +#define DPIO_CHV_GAIN_CTRL(x) REG_FIELD_PREP(DPIO_CHV_GAIN_CTRL_MASK, (x)) +#define DPIO_CHV_INT_COEFF_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_INT_COEFF(x) REG_FIELD_PREP(DPIO_CHV_INT_COEFF_MASK, (x)) +#define DPIO_CHV_PROP_COEFF_MASK REG_GENMASK(3, 0) +#define DPIO_CHV_PROP_COEFF(x) REG_FIELD_PREP(DPIO_CHV_PROP_COEFF_MASK, (x)) + +#define CHV_PLL_DW8(ch) _CHV_PLL((ch), 8) +#define DPIO_CHV_TDC_TARGET_CNT_MASK REG_GENMASK(9, 0) +#define DPIO_CHV_TDC_TARGET_CNT(x) REG_FIELD_PREP(DPIO_CHV_TDC_TARGET_CNT_MASK, (x)) + +#define CHV_PLL_DW9(ch) _CHV_PLL((ch), 9) +#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK REG_GENMASK(3, 1) +#define DPIO_CHV_INT_LOCK_THRESHOLD(x) REG_FIELD_PREP(DPIO_CHV_INT_LOCK_THRESHOLD_MASK, (x)) +#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE REG_BIT(0) /* 1: coarse & 0 : fine */ + +#define CHV_CMN_DW0_CH0 _CHV_CMN(0, 0) +#define DPIO_ALLDL_POWERDOWN_CH0 REG_BIT(19) +#define DPIO_ANYDL_POWERDOWN_CH0 REG_BIT(18) +#define DPIO_ALLDL_POWERDOWN BIT(1) +#define DPIO_ANYDL_POWERDOWN BIT(0) + +#define CHV_CMN_DW5_CH0 _CHV_CMN(0, 5) +#define CHV_BUFRIGHTENA1_MASK REG_GENMASK(21, 20) +#define CHV_BUFRIGHTENA1_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 0) +#define CHV_BUFRIGHTENA1_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 1) +#define CHV_BUFRIGHTENA1_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA1_MASK, 3) +#define CHV_BUFLEFTENA1_MASK REG_GENMASK(23, 22) +#define CHV_BUFLEFTENA1_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 0) +#define CHV_BUFLEFTENA1_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 1) +#define CHV_BUFLEFTENA1_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA1_MASK, 3) + +#define CHV_CMN_DW13_CH0 _CHV_CMN(0, 13) +#define CHV_CMN_DW0_CH1 _CHV_CMN(1, 0) +#define DPIO_CHV_S1_DIV_MASK REG_GENMASK(23, 21) +#define DPIO_CHV_S1_DIV(s1) REG_FIELD_PREP(DPIO_CHV_S1_DIV_MASK, (s1)) +#define DPIO_CHV_P1_DIV_MASK REG_GENMASK(15, 13) +#define DPIO_CHV_P1_DIV(p1) REG_FIELD_PREP(DPIO_CHV_P1_DIV_MASK, (p1)) +#define DPIO_CHV_P2_DIV_MASK REG_GENMASK(12, 8) +#define DPIO_CHV_P2_DIV(p2) REG_FIELD_PREP(DPIO_CHV_P2_DIV_MASK, (p2)) +#define DPIO_CHV_K_DIV_MASK REG_GENMASK(7, 4) +#define DPIO_CHV_K_DIV(k) REG_FIELD_PREP(DPIO_CHV_K_DIV_MASK, (k)) +#define DPIO_PLL_FREQLOCK REG_BIT(1) +#define DPIO_PLL_LOCK REG_BIT(0) +#define CHV_CMN_DW13(ch) _PIPE(ch, CHV_CMN_DW13_CH0, CHV_CMN_DW0_CH1) + +#define CHV_CMN_DW14_CH0 _CHV_CMN(0, 14) +#define CHV_CMN_DW1_CH1 _CHV_CMN(1, 1) +#define DPIO_AFC_RECAL REG_BIT(14) +#define DPIO_DCLKP_EN REG_BIT(13) +#define CHV_BUFLEFTENA2_MASK REG_GENMASK(18, 17) /* CL2 DW1 only */ +#define CHV_BUFLEFTENA2_DISABLE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 0) +#define CHV_BUFLEFTENA2_NORMAL REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 1) +#define CHV_BUFLEFTENA2_FORCE REG_FIELD_PREP(CHV_BUFLEFTENA2_MASK, 3) +#define CHV_BUFRIGHTENA2_MASK REG_GENMASK(20, 19) /* CL2 DW1 only */ +#define CHV_BUFRIGHTENA2_DISABLE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 0) +#define CHV_BUFRIGHTENA2_NORMAL REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 1) +#define CHV_BUFRIGHTENA2_FORCE REG_FIELD_PREP(CHV_BUFRIGHTENA2_MASK, 3) +#define CHV_CMN_DW14(ch) _PIPE(ch, CHV_CMN_DW14_CH0, CHV_CMN_DW1_CH1) + +#define CHV_CMN_DW19_CH0 _CHV_CMN(0, 19) +#define CHV_CMN_DW6_CH1 _CHV_CMN(1, 6) +#define DPIO_ALLDL_POWERDOWN_CH1 REG_BIT(30) /* CL2 DW6 only */ +#define DPIO_ANYDL_POWERDOWN_CH1 REG_BIT(29) /* CL2 DW6 only */ +#define DPIO_DYNPWRDOWNEN_CH1 REG_BIT(28) /* CL2 DW6 only */ +#define CHV_CMN_USEDCLKCHANNEL REG_BIT(13) +#define CHV_CMN_DW19(ch) _PIPE(ch, CHV_CMN_DW19_CH0, CHV_CMN_DW6_CH1) + +#define CHV_CMN_DW28 _CHV_CMN(0, 28) +#define DPIO_CL1POWERDOWNEN REG_BIT(23) +#define DPIO_DYNPWRDOWNEN_CH0 REG_BIT(22) +#define DPIO_SUS_CLK_CONFIG_MASK REG_GENMASK(1, 0) +#define DPIO_SUS_CLK_CONFIG_ON REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 0) +#define DPIO_SUS_CLK_CONFIG_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 1) +#define DPIO_SUS_CLK_CONFIG_GATE REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 2) +#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ REG_FIELD_PREP(DPIO_SUS_CLK_CONFIG_MASK, 3) + +#define CHV_CMN_DW30 _CHV_CMN(0, 30) +#define DPIO_CL2_LDOFUSE_PWRENB REG_BIT(6) +#define DPIO_LRC_BYPASS REG_BIT(3) + +#define CHV_TX_DW0(ch, lane) _VLV_TX((ch), (lane), 0) +#define CHV_TX_DW1(ch, lane) _VLV_TX((ch), (lane), 1) +#define CHV_TX_DW2(ch, lane) _VLV_TX((ch), (lane), 2) +#define CHV_TX_DW3(ch, lane) _VLV_TX((ch), (lane), 3) +#define CHV_TX_DW4(ch, lane) _VLV_TX((ch), (lane), 4) +#define CHV_TX_DW5(ch, lane) _VLV_TX((ch), (lane), 5) +#define CHV_TX_DW6(ch, lane) _VLV_TX((ch), (lane), 6) +#define CHV_TX_DW7(ch, lane) _VLV_TX((ch), (lane), 7) +#define CHV_TX_DW8(ch, lane) _VLV_TX((ch), (lane), 8) +#define CHV_TX_DW9(ch, lane) _VLV_TX((ch), (lane), 9) +#define CHV_TX_DW10(ch, lane) _VLV_TX((ch), (lane), 10) + +#define CHV_TX_DW11(ch, lane) _VLV_TX((ch), (lane), 11) +#define DPIO_FRC_LATENCY_MASK REG_GENMASK(10, 8) +#define DPIO_FRC_LATENCY(x) REG_FIELD_PREP(DPIO_FRC_LATENCY_MASK, (x)) + +#define CHV_TX_DW14(ch, lane) _VLV_TX((ch), (lane), 14) +#define DPIO_UPAR REG_BIT(30) + +#endif /* __VLV_DPIO_PHY_REGS_H__ */ diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c index 68b6aa11bcf7d..40e79f0dc2570 100644 --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c @@ -17,6 +17,8 @@ #include "intel_ring.h" #include "intel_workarounds.h" +#include "display/intel_fbc_regs.h" + /** * DOC: Hardware workarounds * diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c index d4a3f3e093b0b..4be8cb65fb7e7 100644 --- a/drivers/gpu/drm/i915/gvt/cmd_parser.c +++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c @@ -50,6 +50,7 @@ #include "trace.h" #include "display/intel_display.h" +#include "display/intel_sprite_regs.h" #include "gem/i915_gem_context.h" #include "gem/i915_gem_pm.h" #include "gt/intel_context.h" diff --git a/drivers/gpu/drm/i915/gvt/display.c b/drivers/gpu/drm/i915/gvt/display.c index a0381fd230c01..2b7df7fcf369c 100644 --- a/drivers/gpu/drm/i915/gvt/display.c +++ b/drivers/gpu/drm/i915/gvt/display.c @@ -39,6 +39,7 @@ #include "display/bxt_dpio_phy_regs.h" #include "display/intel_display.h" #include "display/intel_dpio_phy.h" +#include "display/intel_sprite_regs.h" static int get_edp_pipe(struct intel_vgpu *vgpu) { diff --git a/drivers/gpu/drm/i915/gvt/fb_decoder.c b/drivers/gpu/drm/i915/gvt/fb_decoder.c index 313efdabee572..4140da68aabb2 100644 --- a/drivers/gpu/drm/i915/gvt/fb_decoder.c +++ b/drivers/gpu/drm/i915/gvt/fb_decoder.c @@ -34,11 +34,14 @@ */ #include <uapi/drm/drm_fourcc.h> -#include "i915_drv.h" + #include "gvt.h" +#include "i915_drv.h" #include "i915_pvinfo.h" #include "i915_reg.h" +#include "display/intel_sprite_regs.h" + #define PRIMARY_FORMAT_NUM 16 struct pixel_format { int drm_format; /* Pixel format in DRM definition */ diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c index 627327deaa2c9..22fbddbe3e239 100644 --- a/drivers/gpu/drm/i915/gvt/handlers.c +++ b/drivers/gpu/drm/i915/gvt/handlers.c @@ -50,6 +50,7 @@ #include "display/intel_fdi_regs.h" #include "display/intel_pps_regs.h" #include "display/intel_psr_regs.h" +#include "display/intel_sprite_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" #include "gt/intel_gt_regs.h" diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c index 622a24305bc21..161b21eff6943 100644 --- a/drivers/gpu/drm/i915/i915_driver.c +++ b/drivers/gpu/drm/i915/i915_driver.c @@ -920,27 +920,6 @@ static int i915_driver_open(struct drm_device *dev, struct drm_file *file) return 0; } -/** - * i915_driver_lastclose - clean up after all DRM clients have exited - * @dev: DRM device - * - * Take care of cleaning up after all DRM clients have exited. In the - * mode setting case, we want to restore the kernel's initial mode (just - * in case the last client left us in a bad state). - * - * Additionally, in the non-mode setting case, we'll tear down the GTT - * and DMA structures, since the kernel won't be using them, and clea - * up any GEM state. - */ -static void i915_driver_lastclose(struct drm_device *dev) -{ - struct drm_i915_private *i915 = to_i915(dev); - - intel_fbdev_restore_mode(i915); - - vga_switcheroo_process_delayed_switch(); -} - static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file) { struct drm_i915_file_private *file_priv = file->driver_priv; @@ -1831,7 +1810,6 @@ static const struct drm_driver i915_drm_driver = { DRIVER_SYNCOBJ_TIMELINE, .release = i915_driver_release, .open = i915_driver_open, - .lastclose = i915_driver_lastclose, .postclose = i915_driver_postclose, .show_fdinfo = PTR_IF(IS_ENABLED(CONFIG_PROC_FS), i915_drm_client_fdinfo), diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8eb6c2bf45570..e22a82a5ddd75 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -195,349 +195,6 @@ #define DPIO_SFR_BYPASS (1 << 1) #define DPIO_CMNRST (1 << 0) -/* - * Per pipe/PLL DPIO regs - */ -#define _VLV_PLL_DW3_CH0 0x800c -#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ -#define DPIO_POST_DIV_DAC 0 -#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ -#define DPIO_POST_DIV_LVDS1 2 -#define DPIO_POST_DIV_LVDS2 3 -#define DPIO_K_SHIFT (24) /* 4 bits */ -#define DPIO_P1_SHIFT (21) /* 3 bits */ -#define DPIO_P2_SHIFT (16) /* 5 bits */ -#define DPIO_N_SHIFT (12) /* 4 bits */ -#define DPIO_ENABLE_CALIBRATION (1 << 11) -#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ -#define DPIO_M2DIV_MASK 0xff -#define _VLV_PLL_DW3_CH1 0x802c -#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1) - -#define _VLV_PLL_DW5_CH0 0x8014 -#define DPIO_REFSEL_OVERRIDE 27 -#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ -#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ -#define DPIO_PLL_REFCLK_SEL_SHIFT 16 /* 2 bits */ -#define DPIO_PLL_REFCLK_SEL_MASK 3 -#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ -#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ -#define _VLV_PLL_DW5_CH1 0x8034 -#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1) - -#define _VLV_PLL_DW7_CH0 0x801c -#define _VLV_PLL_DW7_CH1 0x803c -#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1) - -#define _VLV_PLL_DW8_CH0 0x8040 -#define _VLV_PLL_DW8_CH1 0x8060 -#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1) - -#define VLV_PLL_DW9_BCAST 0xc044 -#define _VLV_PLL_DW9_CH0 0x8044 -#define _VLV_PLL_DW9_CH1 0x8064 -#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1) - -#define _VLV_PLL_DW10_CH0 0x8048 -#define _VLV_PLL_DW10_CH1 0x8068 -#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1) - -#define _VLV_PLL_DW11_CH0 0x804c -#define _VLV_PLL_DW11_CH1 0x806c -#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1) - -/* Spec for ref block start counts at DW10 */ -#define VLV_REF_DW13 0x80ac - -#define VLV_CMN_DW0 0x8100 - -/* - * Per DDI channel DPIO regs - */ - -#define _VLV_PCS_DW0_CH0 0x8200 -#define _VLV_PCS_DW0_CH1 0x8400 -#define DPIO_PCS_TX_LANE2_RESET (1 << 16) -#define DPIO_PCS_TX_LANE1_RESET (1 << 7) -#define DPIO_LEFT_TXFIFO_RST_MASTER2 (1 << 4) -#define DPIO_RIGHT_TXFIFO_RST_MASTER2 (1 << 3) -#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1) - -#define _VLV_PCS01_DW0_CH0 0x200 -#define _VLV_PCS23_DW0_CH0 0x400 -#define _VLV_PCS01_DW0_CH1 0x2600 -#define _VLV_PCS23_DW0_CH1 0x2800 -#define VLV_PCS01_DW0(ch) _PORT(ch, _VLV_PCS01_DW0_CH0, _VLV_PCS01_DW0_CH1) -#define VLV_PCS23_DW0(ch) _PORT(ch, _VLV_PCS23_DW0_CH0, _VLV_PCS23_DW0_CH1) - -#define _VLV_PCS_DW1_CH0 0x8204 -#define _VLV_PCS_DW1_CH1 0x8404 -#define CHV_PCS_REQ_SOFTRESET_EN (1 << 23) -#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1 << 22) -#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1 << 21) -#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) -#define DPIO_PCS_CLK_SOFT_RESET (1 << 5) -#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1) - -#define _VLV_PCS01_DW1_CH0 0x204 -#define _VLV_PCS23_DW1_CH0 0x404 -#define _VLV_PCS01_DW1_CH1 0x2604 -#define _VLV_PCS23_DW1_CH1 0x2804 -#define VLV_PCS01_DW1(ch) _PORT(ch, _VLV_PCS01_DW1_CH0, _VLV_PCS01_DW1_CH1) -#define VLV_PCS23_DW1(ch) _PORT(ch, _VLV_PCS23_DW1_CH0, _VLV_PCS23_DW1_CH1) - -#define _VLV_PCS_DW8_CH0 0x8220 -#define _VLV_PCS_DW8_CH1 0x8420 -#define CHV_PCS_USEDCLKCHANNEL_OVRRIDE (1 << 20) -#define CHV_PCS_USEDCLKCHANNEL (1 << 21) -#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1) - -#define _VLV_PCS01_DW8_CH0 0x0220 -#define _VLV_PCS23_DW8_CH0 0x0420 -#define _VLV_PCS01_DW8_CH1 0x2620 -#define _VLV_PCS23_DW8_CH1 0x2820 -#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1) -#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1) - -#define _VLV_PCS_DW9_CH0 0x8224 -#define _VLV_PCS_DW9_CH1 0x8424 -#define DPIO_PCS_TX2MARGIN_MASK (0x7 << 13) -#define DPIO_PCS_TX2MARGIN_000 (0 << 13) -#define DPIO_PCS_TX2MARGIN_101 (1 << 13) -#define DPIO_PCS_TX1MARGIN_MASK (0x7 << 10) -#define DPIO_PCS_TX1MARGIN_000 (0 << 10) -#define DPIO_PCS_TX1MARGIN_101 (1 << 10) -#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1) - -#define _VLV_PCS01_DW9_CH0 0x224 -#define _VLV_PCS23_DW9_CH0 0x424 -#define _VLV_PCS01_DW9_CH1 0x2624 -#define _VLV_PCS23_DW9_CH1 0x2824 -#define VLV_PCS01_DW9(ch) _PORT(ch, _VLV_PCS01_DW9_CH0, _VLV_PCS01_DW9_CH1) -#define VLV_PCS23_DW9(ch) _PORT(ch, _VLV_PCS23_DW9_CH0, _VLV_PCS23_DW9_CH1) - -#define _CHV_PCS_DW10_CH0 0x8228 -#define _CHV_PCS_DW10_CH1 0x8428 -#define DPIO_PCS_SWING_CALC_TX0_TX2 (1 << 30) -#define DPIO_PCS_SWING_CALC_TX1_TX3 (1 << 31) -#define DPIO_PCS_TX2DEEMP_MASK (0xf << 24) -#define DPIO_PCS_TX2DEEMP_9P5 (0 << 24) -#define DPIO_PCS_TX2DEEMP_6P0 (2 << 24) -#define DPIO_PCS_TX1DEEMP_MASK (0xf << 16) -#define DPIO_PCS_TX1DEEMP_9P5 (0 << 16) -#define DPIO_PCS_TX1DEEMP_6P0 (2 << 16) -#define CHV_PCS_DW10(ch) _PORT(ch, _CHV_PCS_DW10_CH0, _CHV_PCS_DW10_CH1) - -#define _VLV_PCS01_DW10_CH0 0x0228 -#define _VLV_PCS23_DW10_CH0 0x0428 -#define _VLV_PCS01_DW10_CH1 0x2628 -#define _VLV_PCS23_DW10_CH1 0x2828 -#define VLV_PCS01_DW10(port) _PORT(port, _VLV_PCS01_DW10_CH0, _VLV_PCS01_DW10_CH1) -#define VLV_PCS23_DW10(port) _PORT(port, _VLV_PCS23_DW10_CH0, _VLV_PCS23_DW10_CH1) - -#define _VLV_PCS_DW11_CH0 0x822c -#define _VLV_PCS_DW11_CH1 0x842c -#define DPIO_TX2_STAGGER_MASK(x) ((x) << 24) -#define DPIO_LANEDESKEW_STRAP_OVRD (1 << 3) -#define DPIO_LEFT_TXFIFO_RST_MASTER (1 << 1) -#define DPIO_RIGHT_TXFIFO_RST_MASTER (1 << 0) -#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1) - -#define _VLV_PCS01_DW11_CH0 0x022c -#define _VLV_PCS23_DW11_CH0 0x042c -#define _VLV_PCS01_DW11_CH1 0x262c -#define _VLV_PCS23_DW11_CH1 0x282c -#define VLV_PCS01_DW11(ch) _PORT(ch, _VLV_PCS01_DW11_CH0, _VLV_PCS01_DW11_CH1) -#define VLV_PCS23_DW11(ch) _PORT(ch, _VLV_PCS23_DW11_CH0, _VLV_PCS23_DW11_CH1) - -#define _VLV_PCS01_DW12_CH0 0x0230 -#define _VLV_PCS23_DW12_CH0 0x0430 -#define _VLV_PCS01_DW12_CH1 0x2630 -#define _VLV_PCS23_DW12_CH1 0x2830 -#define VLV_PCS01_DW12(ch) _PORT(ch, _VLV_PCS01_DW12_CH0, _VLV_PCS01_DW12_CH1) -#define VLV_PCS23_DW12(ch) _PORT(ch, _VLV_PCS23_DW12_CH0, _VLV_PCS23_DW12_CH1) - -#define _VLV_PCS_DW12_CH0 0x8230 -#define _VLV_PCS_DW12_CH1 0x8430 -#define DPIO_TX2_STAGGER_MULT(x) ((x) << 20) -#define DPIO_TX1_STAGGER_MULT(x) ((x) << 16) -#define DPIO_TX1_STAGGER_MASK(x) ((x) << 8) -#define DPIO_LANESTAGGER_STRAP_OVRD (1 << 6) -#define DPIO_LANESTAGGER_STRAP(x) ((x) << 0) -#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1) - -#define _VLV_PCS_DW14_CH0 0x8238 -#define _VLV_PCS_DW14_CH1 0x8438 -#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1) - -#define _VLV_PCS_DW23_CH0 0x825c -#define _VLV_PCS_DW23_CH1 0x845c -#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1) - -#define _VLV_TX_DW2_CH0 0x8288 -#define _VLV_TX_DW2_CH1 0x8488 -#define DPIO_SWING_MARGIN000_SHIFT 16 -#define DPIO_SWING_MARGIN000_MASK (0xff << DPIO_SWING_MARGIN000_SHIFT) -#define DPIO_UNIQ_TRANS_SCALE_SHIFT 8 -#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1) - -#define _VLV_TX_DW3_CH0 0x828c -#define _VLV_TX_DW3_CH1 0x848c -/* The following bit for CHV phy */ -#define DPIO_TX_UNIQ_TRANS_SCALE_EN (1 << 27) -#define DPIO_SWING_MARGIN101_SHIFT 16 -#define DPIO_SWING_MARGIN101_MASK (0xff << DPIO_SWING_MARGIN101_SHIFT) -#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1) - -#define _VLV_TX_DW4_CH0 0x8290 -#define _VLV_TX_DW4_CH1 0x8490 -#define DPIO_SWING_DEEMPH9P5_SHIFT 24 -#define DPIO_SWING_DEEMPH9P5_MASK (0xff << DPIO_SWING_DEEMPH9P5_SHIFT) -#define DPIO_SWING_DEEMPH6P0_SHIFT 16 -#define DPIO_SWING_DEEMPH6P0_MASK (0xff << DPIO_SWING_DEEMPH6P0_SHIFT) -#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1) - -#define _VLV_TX3_DW4_CH0 0x690 -#define _VLV_TX3_DW4_CH1 0x2a90 -#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1) - -#define _VLV_TX_DW5_CH0 0x8294 -#define _VLV_TX_DW5_CH1 0x8494 -#define DPIO_TX_OCALINIT_EN (1 << 31) -#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1) - -#define _VLV_TX_DW11_CH0 0x82ac -#define _VLV_TX_DW11_CH1 0x84ac -#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1) - -#define _VLV_TX_DW14_CH0 0x82b8 -#define _VLV_TX_DW14_CH1 0x84b8 -#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1) - -/* CHV dpPhy registers */ -#define _CHV_PLL_DW0_CH0 0x8000 -#define _CHV_PLL_DW0_CH1 0x8180 -#define CHV_PLL_DW0(ch) _PIPE(ch, _CHV_PLL_DW0_CH0, _CHV_PLL_DW0_CH1) - -#define _CHV_PLL_DW1_CH0 0x8004 -#define _CHV_PLL_DW1_CH1 0x8184 -#define DPIO_CHV_N_DIV_SHIFT 8 -#define DPIO_CHV_M1_DIV_BY_2 (0 << 0) -#define CHV_PLL_DW1(ch) _PIPE(ch, _CHV_PLL_DW1_CH0, _CHV_PLL_DW1_CH1) - -#define _CHV_PLL_DW2_CH0 0x8008 -#define _CHV_PLL_DW2_CH1 0x8188 -#define CHV_PLL_DW2(ch) _PIPE(ch, _CHV_PLL_DW2_CH0, _CHV_PLL_DW2_CH1) - -#define _CHV_PLL_DW3_CH0 0x800c -#define _CHV_PLL_DW3_CH1 0x818c -#define DPIO_CHV_FRAC_DIV_EN (1 << 16) -#define DPIO_CHV_FIRST_MOD (0 << 8) -#define DPIO_CHV_SECOND_MOD (1 << 8) -#define DPIO_CHV_FEEDFWD_GAIN_SHIFT 0 -#define DPIO_CHV_FEEDFWD_GAIN_MASK (0xF << 0) -#define CHV_PLL_DW3(ch) _PIPE(ch, _CHV_PLL_DW3_CH0, _CHV_PLL_DW3_CH1) - -#define _CHV_PLL_DW6_CH0 0x8018 -#define _CHV_PLL_DW6_CH1 0x8198 -#define DPIO_CHV_GAIN_CTRL_SHIFT 16 -#define DPIO_CHV_INT_COEFF_SHIFT 8 -#define DPIO_CHV_PROP_COEFF_SHIFT 0 -#define CHV_PLL_DW6(ch) _PIPE(ch, _CHV_PLL_DW6_CH0, _CHV_PLL_DW6_CH1) - -#define _CHV_PLL_DW8_CH0 0x8020 -#define _CHV_PLL_DW8_CH1 0x81A0 -#define DPIO_CHV_TDC_TARGET_CNT_SHIFT 0 -#define DPIO_CHV_TDC_TARGET_CNT_MASK (0x3FF << 0) -#define CHV_PLL_DW8(ch) _PIPE(ch, _CHV_PLL_DW8_CH0, _CHV_PLL_DW8_CH1) - -#define _CHV_PLL_DW9_CH0 0x8024 -#define _CHV_PLL_DW9_CH1 0x81A4 -#define DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT 1 /* 3 bits */ -#define DPIO_CHV_INT_LOCK_THRESHOLD_MASK (7 << 1) -#define DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE 1 /* 1: coarse & 0 : fine */ -#define CHV_PLL_DW9(ch) _PIPE(ch, _CHV_PLL_DW9_CH0, _CHV_PLL_DW9_CH1) - -#define _CHV_CMN_DW0_CH0 0x8100 -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH0 19 -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH0 18 -#define DPIO_ALLDL_POWERDOWN (1 << 1) -#define DPIO_ANYDL_POWERDOWN (1 << 0) - -#define _CHV_CMN_DW5_CH0 0x8114 -#define CHV_BUFRIGHTENA1_DISABLE (0 << 20) -#define CHV_BUFRIGHTENA1_NORMAL (1 << 20) -#define CHV_BUFRIGHTENA1_FORCE (3 << 20) -#define CHV_BUFRIGHTENA1_MASK (3 << 20) -#define CHV_BUFLEFTENA1_DISABLE (0 << 22) -#define CHV_BUFLEFTENA1_NORMAL (1 << 22) -#define CHV_BUFLEFTENA1_FORCE (3 << 22) -#define CHV_BUFLEFTENA1_MASK (3 << 22) - -#define _CHV_CMN_DW13_CH0 0x8134 -#define _CHV_CMN_DW0_CH1 0x8080 -#define DPIO_CHV_S1_DIV_SHIFT 21 -#define DPIO_CHV_P1_DIV_SHIFT 13 /* 3 bits */ -#define DPIO_CHV_P2_DIV_SHIFT 8 /* 5 bits */ -#define DPIO_CHV_K_DIV_SHIFT 4 -#define DPIO_PLL_FREQLOCK (1 << 1) -#define DPIO_PLL_LOCK (1 << 0) -#define CHV_CMN_DW13(ch) _PIPE(ch, _CHV_CMN_DW13_CH0, _CHV_CMN_DW0_CH1) - -#define _CHV_CMN_DW14_CH0 0x8138 -#define _CHV_CMN_DW1_CH1 0x8084 -#define DPIO_AFC_RECAL (1 << 14) -#define DPIO_DCLKP_EN (1 << 13) -#define CHV_BUFLEFTENA2_DISABLE (0 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_NORMAL (1 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_FORCE (3 << 17) /* CL2 DW1 only */ -#define CHV_BUFLEFTENA2_MASK (3 << 17) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_DISABLE (0 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_NORMAL (1 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_FORCE (3 << 19) /* CL2 DW1 only */ -#define CHV_BUFRIGHTENA2_MASK (3 << 19) /* CL2 DW1 only */ -#define CHV_CMN_DW14(ch) _PIPE(ch, _CHV_CMN_DW14_CH0, _CHV_CMN_DW1_CH1) - -#define _CHV_CMN_DW19_CH0 0x814c -#define _CHV_CMN_DW6_CH1 0x8098 -#define DPIO_ALLDL_POWERDOWN_SHIFT_CH1 30 /* CL2 DW6 only */ -#define DPIO_ANYDL_POWERDOWN_SHIFT_CH1 29 /* CL2 DW6 only */ -#define DPIO_DYNPWRDOWNEN_CH1 (1 << 28) /* CL2 DW6 only */ -#define CHV_CMN_USEDCLKCHANNEL (1 << 13) - -#define CHV_CMN_DW19(ch) _PIPE(ch, _CHV_CMN_DW19_CH0, _CHV_CMN_DW6_CH1) - -#define CHV_CMN_DW28 0x8170 -#define DPIO_CL1POWERDOWNEN (1 << 23) -#define DPIO_DYNPWRDOWNEN_CH0 (1 << 22) -#define DPIO_SUS_CLK_CONFIG_ON (0 << 0) -#define DPIO_SUS_CLK_CONFIG_CLKREQ (1 << 0) -#define DPIO_SUS_CLK_CONFIG_GATE (2 << 0) -#define DPIO_SUS_CLK_CONFIG_GATE_CLKREQ (3 << 0) - -#define CHV_CMN_DW30 0x8178 -#define DPIO_CL2_LDOFUSE_PWRENB (1 << 6) -#define DPIO_LRC_BYPASS (1 << 3) - -#define _TXLANE(ch, lane, offset) ((ch ? 0x2400 : 0) + \ - (lane) * 0x200 + (offset)) - -#define CHV_TX_DW0(ch, lane) _TXLANE(ch, lane, 0x80) -#define CHV_TX_DW1(ch, lane) _TXLANE(ch, lane, 0x84) -#define CHV_TX_DW2(ch, lane) _TXLANE(ch, lane, 0x88) -#define CHV_TX_DW3(ch, lane) _TXLANE(ch, lane, 0x8c) -#define CHV_TX_DW4(ch, lane) _TXLANE(ch, lane, 0x90) -#define CHV_TX_DW5(ch, lane) _TXLANE(ch, lane, 0x94) -#define CHV_TX_DW6(ch, lane) _TXLANE(ch, lane, 0x98) -#define CHV_TX_DW7(ch, lane) _TXLANE(ch, lane, 0x9c) -#define CHV_TX_DW8(ch, lane) _TXLANE(ch, lane, 0xa0) -#define CHV_TX_DW9(ch, lane) _TXLANE(ch, lane, 0xa4) -#define CHV_TX_DW10(ch, lane) _TXLANE(ch, lane, 0xa8) -#define CHV_TX_DW11(ch, lane) _TXLANE(ch, lane, 0xac) -#define DPIO_FRC_LATENCY_SHFIT 8 -#define CHV_TX_DW14(ch, lane) _TXLANE(ch, lane, 0xb8) -#define DPIO_UPAR_SHIFT 30 - #define BXT_P_CR_GT_DISP_PWRON _MMIO(0x138090) #define MIPIO_RST_CTRL (1 << 2) @@ -966,22 +623,6 @@ #define I915_ASLE_INTERRUPT (1 << 0) #define I915_BSD_USER_INTERRUPT (1 << 25) -#define I915_HDMI_LPE_AUDIO_BASE (VLV_DISPLAY_BASE + 0x65000) -#define I915_HDMI_LPE_AUDIO_SIZE 0x1000 - -/* DisplayPort Audio w/ LPE */ -#define VLV_AUD_CHICKEN_BIT_REG _MMIO(VLV_DISPLAY_BASE + 0x62F38) -#define VLV_CHICKEN_BIT_DBG_ENABLE (1 << 0) - -#define _VLV_AUD_PORT_EN_B_DBG (VLV_DISPLAY_BASE + 0x62F20) -#define _VLV_AUD_PORT_EN_C_DBG (VLV_DISPLAY_BASE + 0x62F30) -#define _VLV_AUD_PORT_EN_D_DBG (VLV_DISPLAY_BASE + 0x62F34) -#define VLV_AUD_PORT_EN_DBG(port) _MMIO_PORT3((port) - PORT_B, \ - _VLV_AUD_PORT_EN_B_DBG, \ - _VLV_AUD_PORT_EN_C_DBG, \ - _VLV_AUD_PORT_EN_D_DBG) -#define VLV_AMP_MUTE (1 << 1) - #define GEN6_BSD_RNCID _MMIO(0x12198) #define GEN7_FF_THREAD_MODE _MMIO(0x20a0) @@ -1002,109 +643,6 @@ #define GEN7_FF_DS_SCHED_LOAD_BALANCE (0x1 << 4) /* Default */ #define GEN7_FF_DS_SCHED_HW (0x0 << 4) -/* - * Framebuffer compression (915+ only) - */ - -#define FBC_CFB_BASE _MMIO(0x3200) /* 4k page aligned */ -#define FBC_LL_BASE _MMIO(0x3204) /* 4k page aligned */ -#define FBC_CONTROL _MMIO(0x3208) -#define FBC_CTL_EN REG_BIT(31) -#define FBC_CTL_PERIODIC REG_BIT(30) -#define FBC_CTL_INTERVAL_MASK REG_GENMASK(29, 16) -#define FBC_CTL_INTERVAL(x) REG_FIELD_PREP(FBC_CTL_INTERVAL_MASK, (x)) -#define FBC_CTL_STOP_ON_MOD REG_BIT(15) -#define FBC_CTL_UNCOMPRESSIBLE REG_BIT(14) /* i915+ */ -#define FBC_CTL_C3_IDLE REG_BIT(13) /* i945gm only */ -#define FBC_CTL_STRIDE_MASK REG_GENMASK(12, 5) -#define FBC_CTL_STRIDE(x) REG_FIELD_PREP(FBC_CTL_STRIDE_MASK, (x)) -#define FBC_CTL_FENCENO_MASK REG_GENMASK(3, 0) -#define FBC_CTL_FENCENO(x) REG_FIELD_PREP(FBC_CTL_FENCENO_MASK, (x)) -#define FBC_COMMAND _MMIO(0x320c) -#define FBC_CMD_COMPRESS REG_BIT(0) -#define FBC_STATUS _MMIO(0x3210) -#define FBC_STAT_COMPRESSING REG_BIT(31) -#define FBC_STAT_COMPRESSED REG_BIT(30) -#define FBC_STAT_MODIFIED REG_BIT(29) -#define FBC_STAT_CURRENT_LINE_MASK REG_GENMASK(10, 0) -#define FBC_CONTROL2 _MMIO(0x3214) /* i965gm only */ -#define FBC_CTL_FENCE_DBL REG_BIT(4) -#define FBC_CTL_IDLE_MASK REG_GENMASK(3, 2) -#define FBC_CTL_IDLE_IMM REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 0) -#define FBC_CTL_IDLE_FULL REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 1) -#define FBC_CTL_IDLE_LINE REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 2) -#define FBC_CTL_IDLE_DEBUG REG_FIELD_PREP(FBC_CTL_IDLE_MASK, 3) -#define FBC_CTL_CPU_FENCE_EN REG_BIT(1) -#define FBC_CTL_PLANE_MASK REG_GENMASK(1, 0) -#define FBC_CTL_PLANE(i9xx_plane) REG_FIELD_PREP(FBC_CTL_PLANE_MASK, (i9xx_plane)) -#define FBC_FENCE_OFF _MMIO(0x3218) /* i965gm only, BSpec typo has 321Bh */ -#define FBC_MOD_NUM _MMIO(0x3220) /* i965gm only */ -#define FBC_MOD_NUM_MASK REG_GENMASK(31, 1) -#define FBC_MOD_NUM_VALID REG_BIT(0) -#define FBC_TAG(i) _MMIO(0x3300 + (i) * 4) /* 49 reisters */ -#define FBC_TAG_MASK REG_GENMASK(1, 0) /* 16 tags per register */ -#define FBC_TAG_MODIFIED REG_FIELD_PREP(FBC_TAG_MASK, 0) -#define FBC_TAG_UNCOMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 1) -#define FBC_TAG_UNCOMPRESSIBLE REG_FIELD_PREP(FBC_TAG_MASK, 2) -#define FBC_TAG_COMPRESSED REG_FIELD_PREP(FBC_TAG_MASK, 3) - -#define FBC_LL_SIZE (1536) - -/* Framebuffer compression for GM45+ */ -#define DPFC_CB_BASE _MMIO(0x3200) -#define ILK_DPFC_CB_BASE(fbc_id) _MMIO_PIPE((fbc_id), 0x43200, 0x43240) -#define DPFC_CONTROL _MMIO(0x3208) -#define ILK_DPFC_CONTROL(fbc_id) _MMIO_PIPE((fbc_id), 0x43208, 0x43248) -#define DPFC_CTL_EN REG_BIT(31) -#define DPFC_CTL_PLANE_MASK_G4X REG_BIT(30) /* g4x-snb */ -#define DPFC_CTL_PLANE_G4X(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_G4X, (i9xx_plane)) -#define DPFC_CTL_FENCE_EN_G4X REG_BIT(29) /* g4x-snb */ -#define DPFC_CTL_PLANE_MASK_IVB REG_GENMASK(30, 29) /* ivb only */ -#define DPFC_CTL_PLANE_IVB(i9xx_plane) REG_FIELD_PREP(DPFC_CTL_PLANE_MASK_IVB, (i9xx_plane)) -#define DPFC_CTL_FENCE_EN_IVB REG_BIT(28) /* ivb+ */ -#define DPFC_CTL_PERSISTENT_MODE REG_BIT(25) /* g4x-snb */ -#define DPFC_CTL_PLANE_BINDING_MASK REG_GENMASK(12, 11) /* lnl+ */ -#define DPFC_CTL_PLANE_BINDING(plane_id) REG_FIELD_PREP(DPFC_CTL_PLANE_BINDING_MASK, (plane_id)) -#define DPFC_CTL_FALSE_COLOR REG_BIT(10) /* ivb+ */ -#define DPFC_CTL_SR_EN REG_BIT(10) /* g4x only */ -#define DPFC_CTL_SR_EXIT_DIS REG_BIT(9) /* g4x only */ -#define DPFC_CTL_LIMIT_MASK REG_GENMASK(7, 6) -#define DPFC_CTL_LIMIT_1X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 0) -#define DPFC_CTL_LIMIT_2X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 1) -#define DPFC_CTL_LIMIT_4X REG_FIELD_PREP(DPFC_CTL_LIMIT_MASK, 2) -#define DPFC_CTL_FENCENO_MASK REG_GENMASK(3, 0) -#define DPFC_CTL_FENCENO(fence) REG_FIELD_PREP(DPFC_CTL_FENCENO_MASK, (fence)) -#define DPFC_RECOMP_CTL _MMIO(0x320c) -#define ILK_DPFC_RECOMP_CTL(fbc_id) _MMIO_PIPE((fbc_id), 0x4320c, 0x4324c) -#define DPFC_RECOMP_STALL_EN REG_BIT(27) -#define DPFC_RECOMP_STALL_WM_MASK REG_GENMASK(26, 16) -#define DPFC_RECOMP_TIMER_COUNT_MASK REG_GENMASK(5, 0) -#define DPFC_STATUS _MMIO(0x3210) -#define ILK_DPFC_STATUS(fbc_id) _MMIO_PIPE((fbc_id), 0x43210, 0x43250) -#define DPFC_INVAL_SEG_MASK REG_GENMASK(26, 16) -#define DPFC_COMP_SEG_MASK REG_GENMASK(10, 0) -#define DPFC_STATUS2 _MMIO(0x3214) -#define ILK_DPFC_STATUS2(fbc_id) _MMIO_PIPE((fbc_id), 0x43214, 0x43254) -#define DPFC_COMP_SEG_MASK_IVB REG_GENMASK(11, 0) -#define DPFC_FENCE_YOFF _MMIO(0x3218) -#define ILK_DPFC_FENCE_YOFF(fbc_id) _MMIO_PIPE((fbc_id), 0x43218, 0x43258) -#define DPFC_CHICKEN _MMIO(0x3224) -#define ILK_DPFC_CHICKEN(fbc_id) _MMIO_PIPE((fbc_id), 0x43224, 0x43264) -#define DPFC_HT_MODIFY REG_BIT(31) /* pre-ivb */ -#define DPFC_NUKE_ON_ANY_MODIFICATION REG_BIT(23) /* bdw+ */ -#define DPFC_CHICKEN_COMP_DUMMY_PIXEL REG_BIT(14) /* glk+ */ -#define DPFC_CHICKEN_FORCE_SLB_INVALIDATION REG_BIT(13) /* icl+ */ -#define DPFC_DISABLE_DUMMY0 REG_BIT(8) /* ivb+ */ - -#define GLK_FBC_STRIDE(fbc_id) _MMIO_PIPE((fbc_id), 0x43228, 0x43268) -#define FBC_STRIDE_OVERRIDE REG_BIT(15) -#define FBC_STRIDE_MASK REG_GENMASK(14, 0) -#define FBC_STRIDE(x) REG_FIELD_PREP(FBC_STRIDE_MASK, (x)) - -#define ILK_FBC_RT_BASE _MMIO(0x2128) -#define ILK_FBC_RT_VALID REG_BIT(0) -#define SNB_FBC_FRONT_BUFFER REG_BIT(1) - #define ILK_DISPLAY_CHICKEN1 _MMIO(0x42000) #define ILK_FBCQ_DIS REG_BIT(22) #define ILK_PABSTRETCH_DIS REG_BIT(21) @@ -1120,37 +658,18 @@ #define IVB_SPR_STRETCH_MAX_X2 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 2) #define IVB_SPR_STRETCH_MAX_X1 REG_FIELD_PREP(IVB_SPR_STRETCH_MAX_MASK, 3) - -/* - * Framebuffer compression for Sandybridge - * - * The following two registers are of type GTTMMADR - */ -#define SNB_DPFC_CTL_SA _MMIO(0x100100) -#define SNB_DPFC_FENCE_EN REG_BIT(29) -#define SNB_DPFC_FENCENO_MASK REG_GENMASK(4, 0) -#define SNB_DPFC_FENCENO(fence) REG_FIELD_PREP(SNB_DPFC_FENCENO_MASK, (fence)) -#define SNB_DPFC_CPU_FENCE_OFFSET _MMIO(0x100104) - -/* Framebuffer compression for Ivybridge */ -#define IVB_FBC_RT_BASE _MMIO(0x7020) -#define IVB_FBC_RT_BASE_UPPER _MMIO(0x7024) - #define IPS_CTL _MMIO(0x43408) #define IPS_ENABLE REG_BIT(31) #define IPS_FALSE_COLOR REG_BIT(4) -#define MSG_FBC_REND_STATE(fbc_id) _MMIO_PIPE((fbc_id), 0x50380, 0x50384) -#define FBC_REND_NUKE REG_BIT(2) -#define FBC_REND_CACHE_CLEAN REG_BIT(1) - /* * Clock control & power management */ -#define _DPLL_A (DISPLAY_MMIO_BASE(dev_priv) + 0x6014) -#define _DPLL_B (DISPLAY_MMIO_BASE(dev_priv) + 0x6018) -#define _CHV_DPLL_C (DISPLAY_MMIO_BASE(dev_priv) + 0x6030) -#define DPLL(pipe) _MMIO_PIPE3((pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) +#define _DPLL_A 0x6014 +#define _DPLL_B 0x6018 +#define _CHV_DPLL_C 0x6030 +#define DPLL(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ + (pipe), _DPLL_A, _DPLL_B, _CHV_DPLL_C) #define VGA0 _MMIO(0x6000) #define VGA1 _MMIO(0x6004) @@ -1246,10 +765,11 @@ #define SDVO_MULTIPLIER_SHIFT_HIRES 4 #define SDVO_MULTIPLIER_SHIFT_VGA 0 -#define _DPLL_A_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x601c) -#define _DPLL_B_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x6020) -#define _CHV_DPLL_C_MD (DISPLAY_MMIO_BASE(dev_priv) + 0x603c) -#define DPLL_MD(pipe) _MMIO_PIPE3((pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) +#define _DPLL_A_MD 0x601c +#define _DPLL_B_MD 0x6020 +#define _CHV_DPLL_C_MD 0x603c +#define DPLL_MD(pipe) _MMIO_BASE_PIPE3(DISPLAY_MMIO_BASE(dev_priv), \ + (pipe), _DPLL_A_MD, _DPLL_B_MD, _CHV_DPLL_C_MD) /* * UDI pixel divider, controlling how many pixels are stuffed into a packet. @@ -1454,36 +974,6 @@ #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510) -/* - * Palette regs - */ -#define _PALETTE_A 0xa000 -#define _PALETTE_B 0xa800 -#define _CHV_PALETTE_C 0xc000 -/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */ -#define PALETTE_RED_MASK REG_GENMASK(23, 16) -#define PALETTE_GREEN_MASK REG_GENMASK(15, 8) -#define PALETTE_BLUE_MASK REG_GENMASK(7, 0) -/* pre-i965 10bit interpolated mode ldw */ -#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16) -#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8) -#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0) -/* pre-i965 10bit interpolated mode udw */ -#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22) -#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18) -#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16) -#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14) -#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10) -#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8) -#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6) -#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2) -#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0) -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \ - _PICK_EVEN_2RANGES(pipe, 2, \ - _PALETTE_A, _PALETTE_B, \ - _CHV_PALETTE_C, _CHV_PALETTE_C) + \ - (i) * 4) - #define PEG_BAND_GAP_DATA _MMIO(0x14d68) #define BXT_RP_STATE_CAP _MMIO(0x138170) @@ -1647,18 +1137,18 @@ #define _PIPE_CRC_RES_4_B_IVB 0x61070 #define _PIPE_CRC_RES_5_B_IVB 0x61074 -#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_CTL_A) -#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_1_A_IVB) -#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_2_A_IVB) -#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_3_A_IVB) -#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_4_A_IVB) -#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_5_A_IVB) +#define PIPE_CRC_CTL(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_CTL_A) +#define PIPE_CRC_RES_1_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_1_A_IVB) +#define PIPE_CRC_RES_2_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_2_A_IVB) +#define PIPE_CRC_RES_3_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_3_A_IVB) +#define PIPE_CRC_RES_4_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_4_A_IVB) +#define PIPE_CRC_RES_5_IVB(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_5_A_IVB) -#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RED_A) -#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_GREEN_A) -#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_BLUE_A) -#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES1_A_I915) -#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(pipe, _PIPE_CRC_RES_RES2_A_G4X) +#define PIPE_CRC_RES_RED(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RED_A) +#define PIPE_CRC_RES_GREEN(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_GREEN_A) +#define PIPE_CRC_RES_BLUE(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_BLUE_A) +#define PIPE_CRC_RES_RES1_I915(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES1_A_I915) +#define PIPE_CRC_RES_RES2_G4X(pipe) _MMIO_TRANS2(dev_priv, pipe, _PIPE_CRC_RES_RES2_A_G4X) /* Pipe/transcoder A timing regs */ #define _TRANS_HTOTAL_A 0x60000 @@ -1727,23 +1217,23 @@ #define _TRANS_VSYNC_DSI1 0x6b814 #define _TRANS_VSYNCSHIFT_DSI1 0x6b828 -#define TRANS_HTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_HTOTAL_A) -#define TRANS_HBLANK(trans) _MMIO_TRANS2((trans), _TRANS_HBLANK_A) -#define TRANS_HSYNC(trans) _MMIO_TRANS2((trans), _TRANS_HSYNC_A) -#define TRANS_VTOTAL(trans) _MMIO_TRANS2((trans), _TRANS_VTOTAL_A) -#define TRANS_VBLANK(trans) _MMIO_TRANS2((trans), _TRANS_VBLANK_A) -#define TRANS_VSYNC(trans) _MMIO_TRANS2((trans), _TRANS_VSYNC_A) -#define BCLRPAT(trans) _MMIO_TRANS2((trans), _BCLRPAT_A) -#define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2((trans), _TRANS_VSYNCSHIFT_A) -#define PIPESRC(pipe) _MMIO_TRANS2((pipe), _PIPEASRC) -#define TRANS_MULT(trans) _MMIO_TRANS2((trans), _TRANS_MULT_A) +#define TRANS_HTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HTOTAL_A) +#define TRANS_HBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HBLANK_A) +#define TRANS_HSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_HSYNC_A) +#define TRANS_VTOTAL(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VTOTAL_A) +#define TRANS_VBLANK(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VBLANK_A) +#define TRANS_VSYNC(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNC_A) +#define BCLRPAT(trans) _MMIO_TRANS2(dev_priv, (trans), _BCLRPAT_A) +#define TRANS_VSYNCSHIFT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_VSYNCSHIFT_A) +#define PIPESRC(pipe) _MMIO_TRANS2(dev_priv, (pipe), _PIPEASRC) +#define TRANS_MULT(trans) _MMIO_TRANS2(dev_priv, (trans), _TRANS_MULT_A) /* VRR registers */ #define _TRANS_VRR_CTL_A 0x60420 #define _TRANS_VRR_CTL_B 0x61420 #define _TRANS_VRR_CTL_C 0x62420 #define _TRANS_VRR_CTL_D 0x63420 -#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(trans, _TRANS_VRR_CTL_A) +#define TRANS_VRR_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_CTL_A) #define VRR_CTL_VRR_ENABLE REG_BIT(31) #define VRR_CTL_IGN_MAX_SHIFT REG_BIT(30) #define VRR_CTL_FLIP_LINE_EN REG_BIT(29) @@ -1757,21 +1247,21 @@ #define _TRANS_VRR_VMAX_B 0x61424 #define _TRANS_VRR_VMAX_C 0x62424 #define _TRANS_VRR_VMAX_D 0x63424 -#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMAX_A) +#define TRANS_VRR_VMAX(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMAX_A) #define VRR_VMAX_MASK REG_GENMASK(19, 0) #define _TRANS_VRR_VMIN_A 0x60434 #define _TRANS_VRR_VMIN_B 0x61434 #define _TRANS_VRR_VMIN_C 0x62434 #define _TRANS_VRR_VMIN_D 0x63434 -#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VMIN_A) +#define TRANS_VRR_VMIN(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VMIN_A) #define VRR_VMIN_MASK REG_GENMASK(15, 0) #define _TRANS_VRR_VMAXSHIFT_A 0x60428 #define _TRANS_VRR_VMAXSHIFT_B 0x61428 #define _TRANS_VRR_VMAXSHIFT_C 0x62428 #define _TRANS_VRR_VMAXSHIFT_D 0x63428 -#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(trans, \ +#define TRANS_VRR_VMAXSHIFT(trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_VMAXSHIFT_A) #define VRR_VMAXSHIFT_DEC_MASK REG_GENMASK(29, 16) #define VRR_VMAXSHIFT_DEC REG_BIT(16) @@ -1781,7 +1271,7 @@ #define _TRANS_VRR_STATUS_B 0x6142C #define _TRANS_VRR_STATUS_C 0x6242C #define _TRANS_VRR_STATUS_D 0x6342C -#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS_A) +#define TRANS_VRR_STATUS(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS_A) #define VRR_STATUS_VMAX_REACHED REG_BIT(31) #define VRR_STATUS_NOFLIP_TILL_BNDR REG_BIT(30) #define VRR_STATUS_FLIP_BEF_BNDR REG_BIT(29) @@ -1801,7 +1291,7 @@ #define _TRANS_VRR_VTOTAL_PREV_B 0x61480 #define _TRANS_VRR_VTOTAL_PREV_C 0x62480 #define _TRANS_VRR_VTOTAL_PREV_D 0x63480 -#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(trans, \ +#define TRANS_VRR_VTOTAL_PREV(trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_VTOTAL_PREV_A) #define VRR_VTOTAL_FLIP_BEFR_BNDR REG_BIT(31) #define VRR_VTOTAL_FLIP_AFTER_BNDR REG_BIT(30) @@ -1812,7 +1302,7 @@ #define _TRANS_VRR_FLIPLINE_B 0x61438 #define _TRANS_VRR_FLIPLINE_C 0x62438 #define _TRANS_VRR_FLIPLINE_D 0x63438 -#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(trans, \ +#define TRANS_VRR_FLIPLINE(trans) _MMIO_TRANS2(dev_priv, trans, \ _TRANS_VRR_FLIPLINE_A) #define VRR_FLIPLINE_MASK REG_GENMASK(19, 0) @@ -1820,19 +1310,19 @@ #define _TRANS_VRR_STATUS2_B 0x6143C #define _TRANS_VRR_STATUS2_C 0x6243C #define _TRANS_VRR_STATUS2_D 0x6343C -#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(trans, _TRANS_VRR_STATUS2_A) +#define TRANS_VRR_STATUS2(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_STATUS2_A) #define VRR_STATUS2_VERT_LN_CNT_MASK REG_GENMASK(19, 0) #define _TRANS_PUSH_A 0x60A70 #define _TRANS_PUSH_B 0x61A70 #define _TRANS_PUSH_C 0x62A70 #define _TRANS_PUSH_D 0x63A70 -#define TRANS_PUSH(trans) _MMIO_TRANS2(trans, _TRANS_PUSH_A) +#define TRANS_PUSH(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_PUSH_A) #define TRANS_PUSH_EN REG_BIT(31) #define TRANS_PUSH_SEND REG_BIT(30) #define _TRANS_VRR_VSYNC_A 0x60078 -#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(trans, _TRANS_VRR_VSYNC_A) +#define TRANS_VRR_VSYNC(trans) _MMIO_TRANS2(dev_priv, trans, _TRANS_VRR_VSYNC_A) #define VRR_VSYNC_END_MASK REG_GENMASK(28, 16) #define VRR_VSYNC_END(vsync_end) REG_FIELD_PREP(VRR_VSYNC_END_MASK, (vsync_end)) #define VRR_VSYNC_START_MASK REG_GENMASK(12, 0) @@ -2388,18 +1878,18 @@ #define PIPESTAT_INT_ENABLE_MASK 0x7fff0000 #define PIPESTAT_INT_STATUS_MASK 0x0000ffff -#define TRANSCONF(trans) _MMIO_PIPE2((trans), _TRANSACONF) -#define PIPEDSL(pipe) _MMIO_PIPE2(pipe, _PIPEADSL) -#define PIPEFRAME(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEHIGH) -#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(pipe, _PIPEAFRAMEPIXEL) -#define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) +#define TRANSCONF(trans) _MMIO_PIPE2(dev_priv, (trans), _TRANSACONF) +#define PIPEDSL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEADSL) +#define PIPEFRAME(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEHIGH) +#define PIPEFRAMEPIXEL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEAFRAMEPIXEL) +#define PIPESTAT(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEASTAT) #define _PIPEAGCMAX 0x70010 #define _PIPEBGCMAX 0x71010 -#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ +#define PIPEGCMAX(pipe, i) _MMIO_PIPE2(dev_priv, pipe, _PIPEAGCMAX + (i) * 4) /* u1.16 */ #define _PIPE_ARB_CTL_A 0x70028 /* icl+ */ -#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(pipe, _PIPE_ARB_CTL_A) +#define PIPE_ARB_CTL(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPE_ARB_CTL_A) #define PIPE_ARB_USE_PROG_SLOTS REG_BIT(13) #define _PIPE_MISC_A 0x70030 @@ -2443,7 +1933,7 @@ #define PIPE_MISC2(pipe) _MMIO_PIPE(pipe, _PIPE_MISC2_A, _PIPE_MISC2_B) #define _ICL_PIPE_A_STATUS 0x70058 -#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(pipe, _ICL_PIPE_A_STATUS) +#define ICL_PIPESTATUS(pipe) _MMIO_PIPE2(dev_priv, pipe, _ICL_PIPE_A_STATUS) #define PIPE_STATUS_UNDERRUN REG_BIT(31) #define PIPE_STATUS_SOFT_UNDERRUN_XELPD REG_BIT(28) #define PIPE_STATUS_HARD_UNDERRUN_XELPD REG_BIT(27) @@ -2718,8 +2208,8 @@ #define _WM0_PIPEA_ILK 0x45100 #define _WM0_PIPEB_ILK 0x45104 #define _WM0_PIPEC_IVB 0x45200 -#define WM0_PIPE_ILK(pipe) _MMIO_PIPE3((pipe), _WM0_PIPEA_ILK, \ - _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) +#define WM0_PIPE_ILK(pipe) _MMIO_BASE_PIPE3(0, (pipe), _WM0_PIPEA_ILK, \ + _WM0_PIPEB_ILK, _WM0_PIPEC_IVB) #define WM0_PIPE_PRIMARY_MASK REG_GENMASK(31, 16) #define WM0_PIPE_SPRITE_MASK REG_GENMASK(15, 8) #define WM0_PIPE_CURSOR_MASK REG_GENMASK(7, 0) @@ -2773,8 +2263,8 @@ /* GM45+ just has to be different */ #define _PIPEA_FRMCOUNT_G4X 0x70040 #define _PIPEA_FLIPCOUNT_G4X 0x70044 -#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FRMCOUNT_G4X) -#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(pipe, _PIPEA_FLIPCOUNT_G4X) +#define PIPE_FRMCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FRMCOUNT_G4X) +#define PIPE_FLIPCOUNT_G4X(pipe) _MMIO_PIPE2(dev_priv, pipe, _PIPEA_FLIPCOUNT_G4X) /* Cursor A & B regs */ #define _CURACNTR 0x70080 @@ -2835,14 +2325,14 @@ #define _CURBBASE_IVB 0x71084 #define _CURBPOS_IVB 0x71088 -#define CURCNTR(pipe) _MMIO_CURSOR2(pipe, _CURACNTR) -#define CURBASE(pipe) _MMIO_CURSOR2(pipe, _CURABASE) -#define CURPOS(pipe) _MMIO_CURSOR2(pipe, _CURAPOS) -#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(pipe, _CURAPOS_ERLY_TPT) -#define CURSIZE(pipe) _MMIO_CURSOR2(pipe, _CURASIZE) -#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(pipe, _CUR_FBC_CTL_A) -#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(pipe, _CUR_CHICKEN_A) -#define CURSURFLIVE(pipe) _MMIO_CURSOR2(pipe, _CURASURFLIVE) +#define CURCNTR(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURACNTR) +#define CURBASE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURABASE) +#define CURPOS(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS) +#define CURPOS_ERLY_TPT(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURAPOS_ERLY_TPT) +#define CURSIZE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASIZE) +#define CUR_FBC_CTL(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_FBC_CTL_A) +#define CUR_CHICKEN(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CUR_CHICKEN_A) +#define CURSURFLIVE(pipe) _MMIO_CURSOR2(dev_priv, pipe, _CURASURFLIVE) /* Display A control */ #define _DSPAADDR_VLV 0x7017C /* vlv/chv */ @@ -2899,18 +2389,18 @@ #define _DSPASURFLIVE 0x701AC #define _DSPAGAMC 0x701E0 -#define DSPADDR_VLV(plane) _MMIO_PIPE2(plane, _DSPAADDR_VLV) -#define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) -#define DSPADDR(plane) _MMIO_PIPE2(plane, _DSPAADDR) -#define DSPSTRIDE(plane) _MMIO_PIPE2(plane, _DSPASTRIDE) -#define DSPPOS(plane) _MMIO_PIPE2(plane, _DSPAPOS) -#define DSPSIZE(plane) _MMIO_PIPE2(plane, _DSPASIZE) -#define DSPSURF(plane) _MMIO_PIPE2(plane, _DSPASURF) -#define DSPTILEOFF(plane) _MMIO_PIPE2(plane, _DSPATILEOFF) +#define DSPADDR_VLV(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR_VLV) +#define DSPCNTR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPACNTR) +#define DSPADDR(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAADDR) +#define DSPSTRIDE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASTRIDE) +#define DSPPOS(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAPOS) +#define DSPSIZE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASIZE) +#define DSPSURF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURF) +#define DSPTILEOFF(plane) _MMIO_PIPE2(dev_priv, plane, _DSPATILEOFF) #define DSPLINOFF(plane) DSPADDR(plane) -#define DSPOFFSET(plane) _MMIO_PIPE2(plane, _DSPAOFFSET) -#define DSPSURFLIVE(plane) _MMIO_PIPE2(plane, _DSPASURFLIVE) -#define DSPGAMC(plane, i) _MMIO_PIPE2(plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ +#define DSPOFFSET(plane) _MMIO_PIPE2(dev_priv, plane, _DSPAOFFSET) +#define DSPSURFLIVE(plane) _MMIO_PIPE2(dev_priv, plane, _DSPASURFLIVE) +#define DSPGAMC(plane, i) _MMIO_PIPE2(dev_priv, plane, _DSPAGAMC + (5 - (i)) * 4) /* plane C only, 6 x u0.8 */ /* CHV pipe B blender and primary plane */ #define _CHV_BLEND_A 0x60a00 @@ -2937,11 +2427,11 @@ #define PRIM_CONST_ALPHA_MASK REG_GENMASK(7, 0) #define PRIM_CONST_ALPHA(alpha) REG_FIELD_PREP(PRIM_CONST_ALPHA_MASK, (alpha)) -#define CHV_BLEND(pipe) _MMIO_TRANS2(pipe, _CHV_BLEND_A) -#define CHV_CANVAS(pipe) _MMIO_TRANS2(pipe, _CHV_CANVAS_A) -#define PRIMPOS(plane) _MMIO_TRANS2(plane, _PRIMPOS_A) -#define PRIMSIZE(plane) _MMIO_TRANS2(plane, _PRIMSIZE_A) -#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(plane, _PRIMCNSTALPHA_A) +#define CHV_BLEND(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_BLEND_A) +#define CHV_CANVAS(pipe) _MMIO_TRANS2(dev_priv, pipe, _CHV_CANVAS_A) +#define PRIMPOS(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMPOS_A) +#define PRIMSIZE(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMSIZE_A) +#define PRIMCNSTALPHA(plane) _MMIO_TRANS2(dev_priv, plane, _PRIMCNSTALPHA_A) /* Display/Sprite base address macros */ #define DISP_BASEADDR_MASK (0xfffff000) @@ -2991,346 +2481,6 @@ #define _PIPEDSI0CONF 0x7b008 #define _PIPEDSI1CONF 0x7b808 -/* Sprite A control */ -#define _DVSACNTR 0x72180 -#define DVS_ENABLE REG_BIT(31) -#define DVS_PIPE_GAMMA_ENABLE REG_BIT(30) -#define DVS_YUV_RANGE_CORRECTION_DISABLE REG_BIT(27) -#define DVS_FORMAT_MASK REG_GENMASK(26, 25) -#define DVS_FORMAT_YUV422 REG_FIELD_PREP(DVS_FORMAT_MASK, 0) -#define DVS_FORMAT_RGBX101010 REG_FIELD_PREP(DVS_FORMAT_MASK, 1) -#define DVS_FORMAT_RGBX888 REG_FIELD_PREP(DVS_FORMAT_MASK, 2) -#define DVS_FORMAT_RGBX161616 REG_FIELD_PREP(DVS_FORMAT_MASK, 3) -#define DVS_PIPE_CSC_ENABLE REG_BIT(24) -#define DVS_SOURCE_KEY REG_BIT(22) -#define DVS_RGB_ORDER_XBGR REG_BIT(20) -#define DVS_YUV_FORMAT_BT709 REG_BIT(18) -#define DVS_YUV_ORDER_MASK REG_GENMASK(17, 16) -#define DVS_YUV_ORDER_YUYV REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 0) -#define DVS_YUV_ORDER_UYVY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 1) -#define DVS_YUV_ORDER_YVYU REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 2) -#define DVS_YUV_ORDER_VYUY REG_FIELD_PREP(DVS_YUV_ORDER_MASK, 3) -#define DVS_ROTATE_180 REG_BIT(15) -#define DVS_TRICKLE_FEED_DISABLE REG_BIT(14) -#define DVS_TILED REG_BIT(10) -#define DVS_DEST_KEY REG_BIT(2) -#define _DVSALINOFF 0x72184 -#define _DVSASTRIDE 0x72188 -#define _DVSAPOS 0x7218c -#define DVS_POS_Y_MASK REG_GENMASK(31, 16) -#define DVS_POS_Y(y) REG_FIELD_PREP(DVS_POS_Y_MASK, (y)) -#define DVS_POS_X_MASK REG_GENMASK(15, 0) -#define DVS_POS_X(x) REG_FIELD_PREP(DVS_POS_X_MASK, (x)) -#define _DVSASIZE 0x72190 -#define DVS_HEIGHT_MASK REG_GENMASK(31, 16) -#define DVS_HEIGHT(h) REG_FIELD_PREP(DVS_HEIGHT_MASK, (h)) -#define DVS_WIDTH_MASK REG_GENMASK(15, 0) -#define DVS_WIDTH(w) REG_FIELD_PREP(DVS_WIDTH_MASK, (w)) -#define _DVSAKEYVAL 0x72194 -#define _DVSAKEYMSK 0x72198 -#define _DVSASURF 0x7219c -#define DVS_ADDR_MASK REG_GENMASK(31, 12) -#define _DVSAKEYMAXVAL 0x721a0 -#define _DVSATILEOFF 0x721a4 -#define DVS_OFFSET_Y_MASK REG_GENMASK(31, 16) -#define DVS_OFFSET_Y(y) REG_FIELD_PREP(DVS_OFFSET_Y_MASK, (y)) -#define DVS_OFFSET_X_MASK REG_GENMASK(15, 0) -#define DVS_OFFSET_X(x) REG_FIELD_PREP(DVS_OFFSET_X_MASK, (x)) -#define _DVSASURFLIVE 0x721ac -#define _DVSAGAMC_G4X 0x721e0 /* g4x */ -#define _DVSASCALE 0x72204 -#define DVS_SCALE_ENABLE REG_BIT(31) -#define DVS_FILTER_MASK REG_GENMASK(30, 29) -#define DVS_FILTER_MEDIUM REG_FIELD_PREP(DVS_FILTER_MASK, 0) -#define DVS_FILTER_ENHANCING REG_FIELD_PREP(DVS_FILTER_MASK, 1) -#define DVS_FILTER_SOFTENING REG_FIELD_PREP(DVS_FILTER_MASK, 2) -#define DVS_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ -#define DVS_VERTICAL_OFFSET_ENABLE REG_BIT(27) -#define DVS_SRC_WIDTH_MASK REG_GENMASK(26, 16) -#define DVS_SRC_WIDTH(w) REG_FIELD_PREP(DVS_SRC_WIDTH_MASK, (w)) -#define DVS_SRC_HEIGHT_MASK REG_GENMASK(10, 0) -#define DVS_SRC_HEIGHT(h) REG_FIELD_PREP(DVS_SRC_HEIGHT_MASK, (h)) -#define _DVSAGAMC_ILK 0x72300 /* ilk/snb */ -#define _DVSAGAMCMAX_ILK 0x72340 /* ilk/snb */ - -#define _DVSBCNTR 0x73180 -#define _DVSBLINOFF 0x73184 -#define _DVSBSTRIDE 0x73188 -#define _DVSBPOS 0x7318c -#define _DVSBSIZE 0x73190 -#define _DVSBKEYVAL 0x73194 -#define _DVSBKEYMSK 0x73198 -#define _DVSBSURF 0x7319c -#define _DVSBKEYMAXVAL 0x731a0 -#define _DVSBTILEOFF 0x731a4 -#define _DVSBSURFLIVE 0x731ac -#define _DVSBGAMC_G4X 0x731e0 /* g4x */ -#define _DVSBSCALE 0x73204 -#define _DVSBGAMC_ILK 0x73300 /* ilk/snb */ -#define _DVSBGAMCMAX_ILK 0x73340 /* ilk/snb */ - -#define DVSCNTR(pipe) _MMIO_PIPE(pipe, _DVSACNTR, _DVSBCNTR) -#define DVSLINOFF(pipe) _MMIO_PIPE(pipe, _DVSALINOFF, _DVSBLINOFF) -#define DVSSTRIDE(pipe) _MMIO_PIPE(pipe, _DVSASTRIDE, _DVSBSTRIDE) -#define DVSPOS(pipe) _MMIO_PIPE(pipe, _DVSAPOS, _DVSBPOS) -#define DVSSURF(pipe) _MMIO_PIPE(pipe, _DVSASURF, _DVSBSURF) -#define DVSKEYMAX(pipe) _MMIO_PIPE(pipe, _DVSAKEYMAXVAL, _DVSBKEYMAXVAL) -#define DVSSIZE(pipe) _MMIO_PIPE(pipe, _DVSASIZE, _DVSBSIZE) -#define DVSSCALE(pipe) _MMIO_PIPE(pipe, _DVSASCALE, _DVSBSCALE) -#define DVSTILEOFF(pipe) _MMIO_PIPE(pipe, _DVSATILEOFF, _DVSBTILEOFF) -#define DVSKEYVAL(pipe) _MMIO_PIPE(pipe, _DVSAKEYVAL, _DVSBKEYVAL) -#define DVSKEYMSK(pipe) _MMIO_PIPE(pipe, _DVSAKEYMSK, _DVSBKEYMSK) -#define DVSSURFLIVE(pipe) _MMIO_PIPE(pipe, _DVSASURFLIVE, _DVSBSURFLIVE) -#define DVSGAMC_G4X(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_G4X, _DVSBGAMC_G4X) + (5 - (i)) * 4) /* 6 x u0.8 */ -#define DVSGAMC_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMC_ILK, _DVSBGAMC_ILK) + (i) * 4) /* 16 x u0.10 */ -#define DVSGAMCMAX_ILK(pipe, i) _MMIO(_PIPE(pipe, _DVSAGAMCMAX_ILK, _DVSBGAMCMAX_ILK) + (i) * 4) /* 3 x u1.10 */ - -#define _SPRA_CTL 0x70280 -#define SPRITE_ENABLE REG_BIT(31) -#define SPRITE_PIPE_GAMMA_ENABLE REG_BIT(30) -#define SPRITE_YUV_RANGE_CORRECTION_DISABLE REG_BIT(28) -#define SPRITE_FORMAT_MASK REG_GENMASK(27, 25) -#define SPRITE_FORMAT_YUV422 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 0) -#define SPRITE_FORMAT_RGBX101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 1) -#define SPRITE_FORMAT_RGBX888 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 2) -#define SPRITE_FORMAT_RGBX161616 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 3) -#define SPRITE_FORMAT_YUV444 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 4) -#define SPRITE_FORMAT_XR_BGR101010 REG_FIELD_PREP(SPRITE_FORMAT_MASK, 5) /* Extended range */ -#define SPRITE_PIPE_CSC_ENABLE REG_BIT(24) -#define SPRITE_SOURCE_KEY REG_BIT(22) -#define SPRITE_RGB_ORDER_RGBX REG_BIT(20) /* only for 888 and 161616 */ -#define SPRITE_YUV_TO_RGB_CSC_DISABLE REG_BIT(19) -#define SPRITE_YUV_TO_RGB_CSC_FORMAT_BT709 REG_BIT(18) /* 0 is BT601 */ -#define SPRITE_YUV_ORDER_MASK REG_GENMASK(17, 16) -#define SPRITE_YUV_ORDER_YUYV REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 0) -#define SPRITE_YUV_ORDER_UYVY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 1) -#define SPRITE_YUV_ORDER_YVYU REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 2) -#define SPRITE_YUV_ORDER_VYUY REG_FIELD_PREP(SPRITE_YUV_ORDER_MASK, 3) -#define SPRITE_ROTATE_180 REG_BIT(15) -#define SPRITE_TRICKLE_FEED_DISABLE REG_BIT(14) -#define SPRITE_PLANE_GAMMA_DISABLE REG_BIT(13) -#define SPRITE_TILED REG_BIT(10) -#define SPRITE_DEST_KEY REG_BIT(2) -#define _SPRA_LINOFF 0x70284 -#define _SPRA_STRIDE 0x70288 -#define _SPRA_POS 0x7028c -#define SPRITE_POS_Y_MASK REG_GENMASK(31, 16) -#define SPRITE_POS_Y(y) REG_FIELD_PREP(SPRITE_POS_Y_MASK, (y)) -#define SPRITE_POS_X_MASK REG_GENMASK(15, 0) -#define SPRITE_POS_X(x) REG_FIELD_PREP(SPRITE_POS_X_MASK, (x)) -#define _SPRA_SIZE 0x70290 -#define SPRITE_HEIGHT_MASK REG_GENMASK(31, 16) -#define SPRITE_HEIGHT(h) REG_FIELD_PREP(SPRITE_HEIGHT_MASK, (h)) -#define SPRITE_WIDTH_MASK REG_GENMASK(15, 0) -#define SPRITE_WIDTH(w) REG_FIELD_PREP(SPRITE_WIDTH_MASK, (w)) -#define _SPRA_KEYVAL 0x70294 -#define _SPRA_KEYMSK 0x70298 -#define _SPRA_SURF 0x7029c -#define SPRITE_ADDR_MASK REG_GENMASK(31, 12) -#define _SPRA_KEYMAX 0x702a0 -#define _SPRA_TILEOFF 0x702a4 -#define SPRITE_OFFSET_Y_MASK REG_GENMASK(31, 16) -#define SPRITE_OFFSET_Y(y) REG_FIELD_PREP(SPRITE_OFFSET_Y_MASK, (y)) -#define SPRITE_OFFSET_X_MASK REG_GENMASK(15, 0) -#define SPRITE_OFFSET_X(x) REG_FIELD_PREP(SPRITE_OFFSET_X_MASK, (x)) -#define _SPRA_OFFSET 0x702a4 -#define _SPRA_SURFLIVE 0x702ac -#define _SPRA_SCALE 0x70304 -#define SPRITE_SCALE_ENABLE REG_BIT(31) -#define SPRITE_FILTER_MASK REG_GENMASK(30, 29) -#define SPRITE_FILTER_MEDIUM REG_FIELD_PREP(SPRITE_FILTER_MASK, 0) -#define SPRITE_FILTER_ENHANCING REG_FIELD_PREP(SPRITE_FILTER_MASK, 1) -#define SPRITE_FILTER_SOFTENING REG_FIELD_PREP(SPRITE_FILTER_MASK, 2) -#define SPRITE_VERTICAL_OFFSET_HALF REG_BIT(28) /* must be enabled below */ -#define SPRITE_VERTICAL_OFFSET_ENABLE REG_BIT(27) -#define SPRITE_SRC_WIDTH_MASK REG_GENMASK(26, 16) -#define SPRITE_SRC_WIDTH(w) REG_FIELD_PREP(SPRITE_SRC_WIDTH_MASK, (w)) -#define SPRITE_SRC_HEIGHT_MASK REG_GENMASK(10, 0) -#define SPRITE_SRC_HEIGHT(h) REG_FIELD_PREP(SPRITE_SRC_HEIGHT_MASK, (h)) -#define _SPRA_GAMC 0x70400 -#define _SPRA_GAMC16 0x70440 -#define _SPRA_GAMC17 0x7044c - -#define _SPRB_CTL 0x71280 -#define _SPRB_LINOFF 0x71284 -#define _SPRB_STRIDE 0x71288 -#define _SPRB_POS 0x7128c -#define _SPRB_SIZE 0x71290 -#define _SPRB_KEYVAL 0x71294 -#define _SPRB_KEYMSK 0x71298 -#define _SPRB_SURF 0x7129c -#define _SPRB_KEYMAX 0x712a0 -#define _SPRB_TILEOFF 0x712a4 -#define _SPRB_OFFSET 0x712a4 -#define _SPRB_SURFLIVE 0x712ac -#define _SPRB_SCALE 0x71304 -#define _SPRB_GAMC 0x71400 -#define _SPRB_GAMC16 0x71440 -#define _SPRB_GAMC17 0x7144c - -#define SPRCTL(pipe) _MMIO_PIPE(pipe, _SPRA_CTL, _SPRB_CTL) -#define SPRLINOFF(pipe) _MMIO_PIPE(pipe, _SPRA_LINOFF, _SPRB_LINOFF) -#define SPRSTRIDE(pipe) _MMIO_PIPE(pipe, _SPRA_STRIDE, _SPRB_STRIDE) -#define SPRPOS(pipe) _MMIO_PIPE(pipe, _SPRA_POS, _SPRB_POS) -#define SPRSIZE(pipe) _MMIO_PIPE(pipe, _SPRA_SIZE, _SPRB_SIZE) -#define SPRKEYVAL(pipe) _MMIO_PIPE(pipe, _SPRA_KEYVAL, _SPRB_KEYVAL) -#define SPRKEYMSK(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMSK, _SPRB_KEYMSK) -#define SPRSURF(pipe) _MMIO_PIPE(pipe, _SPRA_SURF, _SPRB_SURF) -#define SPRKEYMAX(pipe) _MMIO_PIPE(pipe, _SPRA_KEYMAX, _SPRB_KEYMAX) -#define SPRTILEOFF(pipe) _MMIO_PIPE(pipe, _SPRA_TILEOFF, _SPRB_TILEOFF) -#define SPROFFSET(pipe) _MMIO_PIPE(pipe, _SPRA_OFFSET, _SPRB_OFFSET) -#define SPRSCALE(pipe) _MMIO_PIPE(pipe, _SPRA_SCALE, _SPRB_SCALE) -#define SPRGAMC(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC, _SPRB_GAMC) + (i) * 4) /* 16 x u0.10 */ -#define SPRGAMC16(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC16, _SPRB_GAMC16) + (i) * 4) /* 3 x u1.10 */ -#define SPRGAMC17(pipe, i) _MMIO(_PIPE(pipe, _SPRA_GAMC17, _SPRB_GAMC17) + (i) * 4) /* 3 x u2.10 */ -#define SPRSURFLIVE(pipe) _MMIO_PIPE(pipe, _SPRA_SURFLIVE, _SPRB_SURFLIVE) - -#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) -#define SP_ENABLE REG_BIT(31) -#define SP_PIPE_GAMMA_ENABLE REG_BIT(30) -#define SP_FORMAT_MASK REG_GENMASK(29, 26) -#define SP_FORMAT_YUV422 REG_FIELD_PREP(SP_FORMAT_MASK, 0) -#define SP_FORMAT_8BPP REG_FIELD_PREP(SP_FORMAT_MASK, 2) -#define SP_FORMAT_BGR565 REG_FIELD_PREP(SP_FORMAT_MASK, 5) -#define SP_FORMAT_BGRX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 6) -#define SP_FORMAT_BGRA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 7) -#define SP_FORMAT_RGBX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 8) -#define SP_FORMAT_RGBA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 9) -#define SP_FORMAT_BGRX1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 10) /* CHV pipe B */ -#define SP_FORMAT_BGRA1010102 REG_FIELD_PREP(SP_FORMAT_MASK, 11) /* CHV pipe B */ -#define SP_FORMAT_RGBX8888 REG_FIELD_PREP(SP_FORMAT_MASK, 14) -#define SP_FORMAT_RGBA8888 REG_FIELD_PREP(SP_FORMAT_MASK, 15) -#define SP_ALPHA_PREMULTIPLY REG_BIT(23) /* CHV pipe B */ -#define SP_SOURCE_KEY REG_BIT(22) -#define SP_YUV_FORMAT_BT709 REG_BIT(18) -#define SP_YUV_ORDER_MASK REG_GENMASK(17, 16) -#define SP_YUV_ORDER_YUYV REG_FIELD_PREP(SP_YUV_ORDER_MASK, 0) -#define SP_YUV_ORDER_UYVY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 1) -#define SP_YUV_ORDER_YVYU REG_FIELD_PREP(SP_YUV_ORDER_MASK, 2) -#define SP_YUV_ORDER_VYUY REG_FIELD_PREP(SP_YUV_ORDER_MASK, 3) -#define SP_ROTATE_180 REG_BIT(15) -#define SP_TILED REG_BIT(10) -#define SP_MIRROR REG_BIT(8) /* CHV pipe B */ -#define _SPALINOFF (VLV_DISPLAY_BASE + 0x72184) -#define _SPASTRIDE (VLV_DISPLAY_BASE + 0x72188) -#define _SPAPOS (VLV_DISPLAY_BASE + 0x7218c) -#define SP_POS_Y_MASK REG_GENMASK(31, 16) -#define SP_POS_Y(y) REG_FIELD_PREP(SP_POS_Y_MASK, (y)) -#define SP_POS_X_MASK REG_GENMASK(15, 0) -#define SP_POS_X(x) REG_FIELD_PREP(SP_POS_X_MASK, (x)) -#define _SPASIZE (VLV_DISPLAY_BASE + 0x72190) -#define SP_HEIGHT_MASK REG_GENMASK(31, 16) -#define SP_HEIGHT(h) REG_FIELD_PREP(SP_HEIGHT_MASK, (h)) -#define SP_WIDTH_MASK REG_GENMASK(15, 0) -#define SP_WIDTH(w) REG_FIELD_PREP(SP_WIDTH_MASK, (w)) -#define _SPAKEYMINVAL (VLV_DISPLAY_BASE + 0x72194) -#define _SPAKEYMSK (VLV_DISPLAY_BASE + 0x72198) -#define _SPASURF (VLV_DISPLAY_BASE + 0x7219c) -#define SP_ADDR_MASK REG_GENMASK(31, 12) -#define _SPAKEYMAXVAL (VLV_DISPLAY_BASE + 0x721a0) -#define _SPATILEOFF (VLV_DISPLAY_BASE + 0x721a4) -#define SP_OFFSET_Y_MASK REG_GENMASK(31, 16) -#define SP_OFFSET_Y(y) REG_FIELD_PREP(SP_OFFSET_Y_MASK, (y)) -#define SP_OFFSET_X_MASK REG_GENMASK(15, 0) -#define SP_OFFSET_X(x) REG_FIELD_PREP(SP_OFFSET_X_MASK, (x)) -#define _SPACONSTALPHA (VLV_DISPLAY_BASE + 0x721a8) -#define SP_CONST_ALPHA_ENABLE REG_BIT(31) -#define SP_CONST_ALPHA_MASK REG_GENMASK(7, 0) -#define SP_CONST_ALPHA(alpha) REG_FIELD_PREP(SP_CONST_ALPHA_MASK, (alpha)) -#define _SPASURFLIVE (VLV_DISPLAY_BASE + 0x721ac) -#define _SPACLRC0 (VLV_DISPLAY_BASE + 0x721d0) -#define SP_CONTRAST_MASK REG_GENMASK(26, 18) -#define SP_CONTRAST(x) REG_FIELD_PREP(SP_CONTRAST_MASK, (x)) /* u3.6 */ -#define SP_BRIGHTNESS_MASK REG_GENMASK(7, 0) -#define SP_BRIGHTNESS(x) REG_FIELD_PREP(SP_BRIGHTNESS_MASK, (x)) /* s8 */ -#define _SPACLRC1 (VLV_DISPLAY_BASE + 0x721d4) -#define SP_SH_SIN_MASK REG_GENMASK(26, 16) -#define SP_SH_SIN(x) REG_FIELD_PREP(SP_SH_SIN_MASK, (x)) /* s4.7 */ -#define SP_SH_COS_MASK REG_GENMASK(9, 0) -#define SP_SH_COS(x) REG_FIELD_PREP(SP_SH_COS_MASK, (x)) /* u3.7 */ -#define _SPAGAMC (VLV_DISPLAY_BASE + 0x721e0) - -#define _SPBCNTR (VLV_DISPLAY_BASE + 0x72280) -#define _SPBLINOFF (VLV_DISPLAY_BASE + 0x72284) -#define _SPBSTRIDE (VLV_DISPLAY_BASE + 0x72288) -#define _SPBPOS (VLV_DISPLAY_BASE + 0x7228c) -#define _SPBSIZE (VLV_DISPLAY_BASE + 0x72290) -#define _SPBKEYMINVAL (VLV_DISPLAY_BASE + 0x72294) -#define _SPBKEYMSK (VLV_DISPLAY_BASE + 0x72298) -#define _SPBSURF (VLV_DISPLAY_BASE + 0x7229c) -#define _SPBKEYMAXVAL (VLV_DISPLAY_BASE + 0x722a0) -#define _SPBTILEOFF (VLV_DISPLAY_BASE + 0x722a4) -#define _SPBCONSTALPHA (VLV_DISPLAY_BASE + 0x722a8) -#define _SPBSURFLIVE (VLV_DISPLAY_BASE + 0x722ac) -#define _SPBCLRC0 (VLV_DISPLAY_BASE + 0x722d0) -#define _SPBCLRC1 (VLV_DISPLAY_BASE + 0x722d4) -#define _SPBGAMC (VLV_DISPLAY_BASE + 0x722e0) - -#define _VLV_SPR(pipe, plane_id, reg_a, reg_b) \ - _PIPE((pipe) * 2 + (plane_id) - PLANE_SPRITE0, (reg_a), (reg_b)) -#define _MMIO_VLV_SPR(pipe, plane_id, reg_a, reg_b) \ - _MMIO(_VLV_SPR((pipe), (plane_id), (reg_a), (reg_b))) - -#define SPCNTR(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACNTR, _SPBCNTR) -#define SPLINOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPALINOFF, _SPBLINOFF) -#define SPSTRIDE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASTRIDE, _SPBSTRIDE) -#define SPPOS(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAPOS, _SPBPOS) -#define SPSIZE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASIZE, _SPBSIZE) -#define SPKEYMINVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMINVAL, _SPBKEYMINVAL) -#define SPKEYMSK(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMSK, _SPBKEYMSK) -#define SPSURF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURF, _SPBSURF) -#define SPKEYMAXVAL(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPAKEYMAXVAL, _SPBKEYMAXVAL) -#define SPTILEOFF(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPATILEOFF, _SPBTILEOFF) -#define SPCONSTALPHA(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACONSTALPHA, _SPBCONSTALPHA) -#define SPSURFLIVE(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPASURFLIVE, _SPBSURFLIVE) -#define SPCLRC0(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC0, _SPBCLRC0) -#define SPCLRC1(pipe, plane_id) _MMIO_VLV_SPR((pipe), (plane_id), _SPACLRC1, _SPBCLRC1) -#define SPGAMC(pipe, plane_id, i) _MMIO(_VLV_SPR((pipe), (plane_id), _SPAGAMC, _SPBGAMC) + (5 - (i)) * 4) /* 6 x u0.10 */ - -/* - * CHV pipe B sprite CSC - * - * |cr| |c0 c1 c2| |cr + cr_ioff| |cr_ooff| - * |yg| = |c3 c4 c5| x |yg + yg_ioff| + |yg_ooff| - * |cb| |c6 c7 c8| |cb + cr_ioff| |cb_ooff| - */ -#define _MMIO_CHV_SPCSC(plane_id, reg) \ - _MMIO(VLV_DISPLAY_BASE + ((plane_id) - PLANE_SPRITE0) * 0x1000 + (reg)) - -#define SPCSCYGOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d900) -#define SPCSCCBOFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d904) -#define SPCSCCROFF(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d908) -#define SPCSC_OOFF_MASK REG_GENMASK(26, 16) -#define SPCSC_OOFF(x) REG_FIELD_PREP(SPCSC_OOFF_MASK, (x) & 0x7ff) /* s11 */ -#define SPCSC_IOFF_MASK REG_GENMASK(10, 0) -#define SPCSC_IOFF(x) REG_FIELD_PREP(SPCSC_IOFF_MASK, (x) & 0x7ff) /* s11 */ - -#define SPCSCC01(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d90c) -#define SPCSCC23(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d910) -#define SPCSCC45(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d914) -#define SPCSCC67(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d918) -#define SPCSCC8(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d91c) -#define SPCSC_C1_MASK REG_GENMASK(30, 16) -#define SPCSC_C1(x) REG_FIELD_PREP(SPCSC_C1_MASK, (x) & 0x7fff) /* s3.12 */ -#define SPCSC_C0_MASK REG_GENMASK(14, 0) -#define SPCSC_C0(x) REG_FIELD_PREP(SPCSC_C0_MASK, (x) & 0x7fff) /* s3.12 */ - -#define SPCSCYGICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d920) -#define SPCSCCBICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d924) -#define SPCSCCRICLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d928) -#define SPCSC_IMAX_MASK REG_GENMASK(26, 16) -#define SPCSC_IMAX(x) REG_FIELD_PREP(SPCSC_IMAX_MASK, (x) & 0x7ff) /* s11 */ -#define SPCSC_IMIN_MASK REG_GENMASK(10, 0) -#define SPCSC_IMIN(x) REG_FIELD_PREP(SPCSC_IMIN_MASK, (x) & 0x7ff) /* s11 */ - -#define SPCSCYGOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d92c) -#define SPCSCCBOCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d930) -#define SPCSCCROCLAMP(plane_id) _MMIO_CHV_SPCSC(plane_id, 0x6d934) -#define SPCSC_OMAX_MASK REG_GENMASK(25, 16) -#define SPCSC_OMAX(x) REG_FIELD_PREP(SPCSC_OMAX_MASK, (x)) /* u10 */ -#define SPCSC_OMIN_MASK REG_GENMASK(9, 0) -#define SPCSC_OMIN(x) REG_FIELD_PREP(SPCSC_OMIN_MASK, (x)) /* u10 */ - /* Skylake plane registers */ #define _PLANE_CTL_1_A 0x70180 @@ -3740,14 +2890,14 @@ #define _PIPEB_LINK_M2 0x61048 #define _PIPEB_LINK_N2 0x6104c -#define PIPE_DATA_M1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M1) -#define PIPE_DATA_N1(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N1) -#define PIPE_DATA_M2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_M2) -#define PIPE_DATA_N2(tran) _MMIO_TRANS2(tran, _PIPEA_DATA_N2) -#define PIPE_LINK_M1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M1) -#define PIPE_LINK_N1(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N1) -#define PIPE_LINK_M2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_M2) -#define PIPE_LINK_N2(tran) _MMIO_TRANS2(tran, _PIPEA_LINK_N2) +#define PIPE_DATA_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M1) +#define PIPE_DATA_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N1) +#define PIPE_DATA_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_M2) +#define PIPE_DATA_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_DATA_N2) +#define PIPE_LINK_M1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M1) +#define PIPE_LINK_N1(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N1) +#define PIPE_LINK_M2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_M2) +#define PIPE_LINK_N2(tran) _MMIO_TRANS2(dev_priv, tran, _PIPEA_LINK_N2) /* CPU panel fitter */ /* IVB+ has 3 fitters, 0 is 7x5 capable, the other two only 3x3 */ @@ -4767,27 +3917,29 @@ #define TVIDEO_DIP_GCP(pipe) _MMIO_PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B) /* Per-transcoder DIP controls (VLV) */ -#define _VLV_VIDEO_DIP_CTL_A (VLV_DISPLAY_BASE + 0x60200) -#define _VLV_VIDEO_DIP_DATA_A (VLV_DISPLAY_BASE + 0x60208) -#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A (VLV_DISPLAY_BASE + 0x60210) - -#define _VLV_VIDEO_DIP_CTL_B (VLV_DISPLAY_BASE + 0x61170) -#define _VLV_VIDEO_DIP_DATA_B (VLV_DISPLAY_BASE + 0x61174) -#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B (VLV_DISPLAY_BASE + 0x61178) - -#define _CHV_VIDEO_DIP_CTL_C (VLV_DISPLAY_BASE + 0x611f0) -#define _CHV_VIDEO_DIP_DATA_C (VLV_DISPLAY_BASE + 0x611f4) -#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C (VLV_DISPLAY_BASE + 0x611f8) - -#define VLV_TVIDEO_DIP_CTL(pipe) \ - _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_CTL_A, \ - _VLV_VIDEO_DIP_CTL_B, _CHV_VIDEO_DIP_CTL_C) -#define VLV_TVIDEO_DIP_DATA(pipe) \ - _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_DATA_A, \ - _VLV_VIDEO_DIP_DATA_B, _CHV_VIDEO_DIP_DATA_C) -#define VLV_TVIDEO_DIP_GCP(pipe) \ - _MMIO_PIPE3((pipe), _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ - _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) +#define _VLV_VIDEO_DIP_CTL_A 0x60200 +#define _VLV_VIDEO_DIP_CTL_B 0x61170 +#define _CHV_VIDEO_DIP_CTL_C 0x611f0 +#define VLV_TVIDEO_DIP_CTL(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_CTL_A, \ + _VLV_VIDEO_DIP_CTL_B, \ + _CHV_VIDEO_DIP_CTL_C) + +#define _VLV_VIDEO_DIP_DATA_A 0x60208 +#define _VLV_VIDEO_DIP_DATA_B 0x61174 +#define _CHV_VIDEO_DIP_DATA_C 0x611f4 +#define VLV_TVIDEO_DIP_DATA(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_DATA_A, \ + _VLV_VIDEO_DIP_DATA_B, \ + _CHV_VIDEO_DIP_DATA_C) + +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_A 0x60210 +#define _VLV_VIDEO_DIP_GDCP_PAYLOAD_B 0x61178 +#define _CHV_VIDEO_DIP_GDCP_PAYLOAD_C 0x611f8 +#define VLV_TVIDEO_DIP_GCP(pipe) _MMIO_BASE_PIPE3(VLV_DISPLAY_BASE, (pipe), \ + _VLV_VIDEO_DIP_GDCP_PAYLOAD_A, \ + _VLV_VIDEO_DIP_GDCP_PAYLOAD_B, \ + _CHV_VIDEO_DIP_GDCP_PAYLOAD_C) /* Haswell DIP controls */ @@ -4832,25 +3984,25 @@ #define _ICL_VIDEO_DIP_PPS_ECC_A 0x603D4 #define _ICL_VIDEO_DIP_PPS_ECC_B 0x613D4 -#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_CTL_A) -#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GCP_A) -#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) -#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) -#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) -#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) +#define HSW_TVIDEO_DIP_CTL(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_CTL_A) +#define HSW_TVIDEO_DIP_GCP(trans) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GCP_A) +#define HSW_TVIDEO_DIP_AVI_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_AVI_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_VS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VS_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_SPD_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_SPD_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_GMP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_GMP_DATA_A + (i) * 4) +#define HSW_TVIDEO_DIP_VSC_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _HSW_VIDEO_DIP_VSC_DATA_A + (i) * 4) +#define GLK_TVIDEO_DIP_DRM_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _GLK_VIDEO_DIP_DRM_DATA_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4) +#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(dev_priv, trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4) /*ADLP and later: */ -#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(trans,\ +#define ADL_TVIDEO_DIP_AS_SDP_DATA(trans, i) _MMIO_TRANS2(dev_priv, trans,\ _ADL_VIDEO_DIP_AS_DATA_A + (i) * 4) #define _HSW_STEREO_3D_CTL_A 0x70020 #define S3D_ENABLE (1 << 31) #define _HSW_STEREO_3D_CTL_B 0x71020 -#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(trans, _HSW_STEREO_3D_CTL_A) +#define HSW_STEREO_3D_CTL(trans) _MMIO_PIPE2(dev_priv, trans, _HSW_STEREO_3D_CTL_A) #define _PCH_TRANS_HTOTAL_B 0xe1000 #define _PCH_TRANS_HBLANK_B 0xe1004 @@ -5336,7 +4488,7 @@ enum skl_power_gate { #define _TRANS_DDI_FUNC_CTL_EDP 0x6F400 #define _TRANS_DDI_FUNC_CTL_DSI0 0x6b400 #define _TRANS_DDI_FUNC_CTL_DSI1 0x6bc00 -#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL_A) +#define TRANS_DDI_FUNC_CTL(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL_A) #define TRANS_DDI_FUNC_ENABLE (1 << 31) /* Those bits are ignored by pipe EDP since it can only connect to DDI A */ @@ -5391,7 +4543,7 @@ enum skl_power_gate { #define _TRANS_DDI_FUNC_CTL2_EDP 0x6f404 #define _TRANS_DDI_FUNC_CTL2_DSI0 0x6b404 #define _TRANS_DDI_FUNC_CTL2_DSI1 0x6bc04 -#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(tran, _TRANS_DDI_FUNC_CTL2_A) +#define TRANS_DDI_FUNC_CTL2(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_DDI_FUNC_CTL2_A) #define PORT_SYNC_MODE_ENABLE REG_BIT(4) #define PORT_SYNC_MODE_MASTER_SELECT_MASK REG_GENMASK(2, 0) #define PORT_SYNC_MODE_MASTER_SELECT(x) REG_FIELD_PREP(PORT_SYNC_MODE_MASTER_SELECT_MASK, (x)) @@ -5404,7 +4556,7 @@ enum skl_power_gate { #define _DP_TP_CTL_B 0x64140 #define _TGL_DP_TP_CTL_A 0x60540 #define DP_TP_CTL(port) _MMIO_PORT(port, _DP_TP_CTL_A, _DP_TP_CTL_B) -#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_CTL_A) +#define TGL_DP_TP_CTL(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_CTL_A) #define DP_TP_CTL_ENABLE (1 << 31) #define DP_TP_CTL_FEC_ENABLE (1 << 30) #define DP_TP_CTL_MODE_SST (0 << 27) @@ -5430,7 +4582,7 @@ enum skl_power_gate { #define _DP_TP_STATUS_B 0x64144 #define _TGL_DP_TP_STATUS_A 0x60544 #define DP_TP_STATUS(port) _MMIO_PORT(port, _DP_TP_STATUS_A, _DP_TP_STATUS_B) -#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2((tran), _TGL_DP_TP_STATUS_A) +#define TGL_DP_TP_STATUS(tran) _MMIO_TRANS2(dev_priv, (tran), _TGL_DP_TP_STATUS_A) #define DP_TP_STATUS_FEC_ENABLE_LIVE (1 << 28) #define DP_TP_STATUS_IDLE_DONE (1 << 25) #define DP_TP_STATUS_ACT_SENT (1 << 24) @@ -5611,14 +4763,14 @@ enum skl_power_gate { #define _TRANSB_MSA_MISC 0x61410 #define _TRANSC_MSA_MISC 0x62410 #define _TRANS_EDP_MSA_MISC 0x6f410 -#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(tran, _TRANSA_MSA_MISC) +#define TRANS_MSA_MISC(tran) _MMIO_TRANS2(dev_priv, tran, _TRANSA_MSA_MISC) /* See DP_MSA_MISC_* for the bit definitions */ #define _TRANS_A_SET_CONTEXT_LATENCY 0x6007C #define _TRANS_B_SET_CONTEXT_LATENCY 0x6107C #define _TRANS_C_SET_CONTEXT_LATENCY 0x6207C #define _TRANS_D_SET_CONTEXT_LATENCY 0x6307C -#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(tran, _TRANS_A_SET_CONTEXT_LATENCY) +#define TRANS_SET_CONTEXT_LATENCY(tran) _MMIO_TRANS2(dev_priv, tran, _TRANS_A_SET_CONTEXT_LATENCY) #define TRANS_SET_CONTEXT_LATENCY_MASK REG_GENMASK(15, 0) #define TRANS_SET_CONTEXT_LATENCY_VALUE(x) REG_FIELD_PREP(TRANS_SET_CONTEXT_LATENCY_MASK, (x)) @@ -6072,7 +5224,7 @@ enum skl_power_gate { #define _VLV_PIPE_MSA_MISC_A 0x70048 #define VLV_PIPE_MSA_MISC(pipe) \ - _MMIO_PIPE2(pipe, _VLV_PIPE_MSA_MISC_A) + _MMIO_PIPE2(dev_priv, pipe, _VLV_PIPE_MSA_MISC_A) #define VLV_MSA_MISC1_HW_ENABLE REG_BIT(31) #define VLV_MSA_MISC1_SW_S3D_MASK REG_GENMASK(2, 0) /* MSA MISC1 3:1 */ @@ -6145,7 +5297,7 @@ enum skl_power_gate { #define _MTL_CLKGATE_DIS_TRANS_A 0x604E8 #define _MTL_CLKGATE_DIS_TRANS_B 0x614E8 -#define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(trans, _MTL_CLKGATE_DIS_TRANS_A) +#define MTL_CLKGATE_DIS_TRANS(trans) _MMIO_TRANS2(dev_priv, trans, _MTL_CLKGATE_DIS_TRANS_A) #define MTL_CLKGATE_DIS_TRANS_DMASC_GATING_DIS REG_BIT(7) #define MTL_MEM_SS_INFO_GLOBAL _MMIO(0x45700) diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c index 7e70ee4fbd84d..1dc5281b2adec 100644 --- a/drivers/gpu/drm/i915/intel_clock_gating.c +++ b/drivers/gpu/drm/i915/intel_clock_gating.c @@ -28,6 +28,7 @@ #include "display/intel_de.h" #include "display/intel_display.h" #include "display/intel_display_trace.h" +#include "display/intel_fbc_regs.h" #include "display/skl_watermark.h" #include "gt/intel_engine_regs.h" diff --git a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c index d0f111ff0adad..e1a35f70b5442 100644 --- a/drivers/gpu/drm/i915/intel_gvt_mmio_table.c +++ b/drivers/gpu/drm/i915/intel_gvt_mmio_table.c @@ -11,9 +11,11 @@ #include "display/intel_dmc_regs.h" #include "display/intel_dp_aux_regs.h" #include "display/intel_dpio_phy.h" +#include "display/intel_fbc_regs.h" #include "display/intel_fdi_regs.h" #include "display/intel_lvds_regs.h" #include "display/intel_psr_regs.h" +#include "display/intel_sprite_regs.h" #include "display/skl_watermark_regs.h" #include "display/vlv_dsi_pll_regs.h" #include "gt/intel_engine_regs.h" diff --git a/drivers/gpu/drm/i915/vlv_sideband.c b/drivers/gpu/drm/i915/vlv_sideband.c index ffa195560d0dd..68291412f4cb3 100644 --- a/drivers/gpu/drm/i915/vlv_sideband.c +++ b/drivers/gpu/drm/i915/vlv_sideband.c @@ -9,7 +9,6 @@ #include "vlv_sideband.h" #include "display/intel_dpio_phy.h" -#include "display/intel_display_types.h" /* * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c index 63b27fbcdaca3..0de0566e5b394 100644 --- a/drivers/gpu/drm/xe/display/xe_display.c +++ b/drivers/gpu/drm/xe/display/xe_display.c @@ -51,14 +51,6 @@ bool xe_display_driver_probe_defer(struct pci_dev *pdev) return intel_display_driver_probe_defer(pdev); } -static void xe_display_last_close(struct drm_device *dev) -{ - struct xe_device *xe = to_xe_device(dev); - - if (xe->info.enable_display) - intel_fbdev_restore_mode(to_xe_device(dev)); -} - /** * xe_display_driver_set_hooks - Add driver flags and hooks for display * @driver: DRM device driver @@ -73,7 +65,6 @@ void xe_display_driver_set_hooks(struct drm_driver *driver) return; driver->driver_features |= DRIVER_MODESET | DRIVER_ATOMIC; - driver->lastclose = xe_display_last_close; } static void unset_display_features(struct xe_device *xe) @@ -212,9 +203,7 @@ void xe_display_fini(struct xe_device *xe) if (!xe->info.enable_display) return; - /* poll work can call into fbdev, hence clean that up afterwards */ intel_hpd_poll_fini(xe); - intel_fbdev_fini(xe); intel_hdcp_component_fini(xe); intel_audio_deinit(xe); diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 55bbc8b8df159..5ef9b50a20d01 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -9,6 +9,7 @@ #include <drm/drm_aperture.h> #include <drm/drm_atomic_helper.h> +#include <drm/drm_client.h> #include <drm/drm_gem_ttm_helper.h> #include <drm/drm_ioctl.h> #include <drm/drm_managed.h> |