diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2014-07-29 17:18:51 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2014-11-06 17:34:25 +0000 |
| commit | 26a17ad59544f026878efdb0524ce66b7a314784 (patch) | |
| tree | ec6287712137c6c155859d91eaa8a0d4a847a325 | |
| parent | 119f54ca240684f47d8c1897ca4594fccc59846b (diff) | |
| download | boot-wrapper-aarch64-26a17ad59544f026878efdb0524ce66b7a314784.tar.gz | |
bootwrapper: improve UART initialisation
The PL011 spec requires that baud rate settings should be done by
writing both xBRD registers followed by a write to LCR_H (which we
skipped so far completely).[1]
So include the FBRD register write as well and set up the LCR_H
register to initialise the UART to 8N1.
Also skip the automatic RTS/CTS enablement, as this may not be
used by the peer (and the generic UART does not have it at all).
[1] ARM PL011 TRM, 3.3.7 (top of page 3-14)
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| -rw-r--r-- | ns.S | 12 |
1 files changed, 9 insertions, 3 deletions
@@ -8,6 +8,8 @@ */ #define PL011_UARTIBRD 0x24 +#define PL011_UARTFBRD 0x28 +#define PL011_UART_LCR_H 0x2c #define PL011_UARTCR 0x30 #define V2M_SYS_CFGDATA 0xa0 @@ -23,8 +25,12 @@ ns_init_system: ldr x4, =UART_BASE mov w5, #0x10 str w5, [x4, #PL011_UARTIBRD] - mov w5, #0xc300 - orr w5, w5, #0x0001 + str wzr, [x4, #PL011_UARTFBRD] + /* set parameters to 8N1 and enable the FIFOs */ + mov w5, #0x70 + str w5, [x4, #PL011_UART_LCR_H] + /* enable the UART, TXen and RXen */ + mov w5, #0x301 str w5, [x4, #PL011_UARTCR] /* @@ -38,4 +44,4 @@ ns_init_system: ret .ltorg - .org 0x40 + .org 0x80 |