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| author | Vladimir Murzin <vladimir.murzin@arm.com> | 2014-03-20 11:01:32 +0000 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2014-03-20 15:38:20 +0000 |
| commit | ebc511d7b1215b02c7ff1804f14307ec9619dedb (patch) | |
| tree | 6f54cc1527fbd0fe358a52abbfa19d876e9a7fe8 | |
| parent | 4266507a84f8c06452109d38e0350d4759740694 (diff) | |
| download | boot-wrapper-aarch64-ebc511d7b1215b02c7ff1804f14307ec9619dedb.tar.gz | |
fix SetWay bits alignment for DC op
Althought comment is aligned with ARMv8 ARM implentation is different. In
fact, "set" is shifted by "shift" and "way" is shifted by "line size".
Correct this missalignment.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | cache.S | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -47,9 +47,9 @@ flush_caches: /* loop over sets */ /* build the set/way command */ 3: lsl x9, x2, #1 /* cache level (-1) */ - lsl x10, x8, x5 /* way << shift */ + lsl x10, x6, x5 /* way << shift */ orr x9, x9, x10 - lsl x10, x6, x4 /* set << line size */ + lsl x10, x8, x4 /* set << line size */ orr x9, x9, x10 dc cisw, x9 |