diff options
| author | Mark Rutland <mark.rutland@arm.com> | 2013-05-16 11:07:41 +0100 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2013-06-05 13:57:42 +0100 |
| commit | 76eca64800b99aaf0c3d7e46b2111875f266e05e (patch) | |
| tree | cd6a8420c77568fb8460ed452ec273e5491d9311 | |
| parent | cc281ad661f59102b52ee1274555e69b1a3bd887 (diff) | |
| download | boot-wrapper-aarch64-76eca64800b99aaf0c3d7e46b2111875f266e05e.tar.gz | |
Test all MPIDR affinity bits
Currently we only test the Aff0 bits of the MPIDR to determine the
'primary' CPU. In multi-cluster systems, MPIDR.Aff{3,2,1} may not be
zero, and there may by multiple CPUs where MPIDR.Aff0 is zero. In these
systems we might determine that two cpus are the primary CPU.
This patch adds a MPIDR_ID_BITS mask, and uses it in all cases we test
the MPIDR, making this safe for multi-cluster systems. This doesn't
bring full support for multi-cluster systems, however, as they may
require additional hardware to be set up (e.g. CCI).
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
| -rw-r--r-- | boot.S | 6 | ||||
| -rw-r--r-- | common.S | 2 |
2 files changed, 6 insertions, 2 deletions
@@ -36,7 +36,8 @@ _start: * registers. */ mrs x0, mpidr_el1 - tst x0, #15 + ldr x1, =MPIDR_ID_BITS + tst x0, x1 b.ne 1f // secondary CPU ldr x1, =GIC_DIST_BASE // GICD_CTLR @@ -76,7 +77,8 @@ start_ns: mov x3, xzr mrs x4, mpidr_el1 - tst x4, #15 + ldr x5, =MPIDR_ID_BITS + tst x4, x5 b.eq 2f /* @@ -7,6 +7,8 @@ * found in the LICENSE.txt file. */ +#define MPIDR_ID_BITS (0xff00ffffff) + #define CURRENTEL_EL3 (3 << 2) #define SPSR_A (1 << 8) /* System Error masked */ |