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| author | Mark Rutland <mark.rutland@arm.com> | 2022-01-19 15:05:15 +0000 |
|---|---|---|
| committer | Mark Rutland <mark.rutland@arm.com> | 2022-01-27 15:49:20 +0000 |
| commit | 2dd9f3117d00b4d78e7a2e5309140b11f5f5ac07 (patch) | |
| tree | d1f42b5c9ae4371249661534b448fa4e8488d522 | |
| parent | 0607f1669cd66442cc956ff174db679971e14613 (diff) | |
| download | boot-wrapper-aarch64-2dd9f3117d00b4d78e7a2e5309140b11f5f5ac07.tar.gz | |
aarch64: correct ZCR_EL3.LEN initialization
The ZCR_ELx.LEN field covers bits[3:0] of ZCR_ELx, and bits[8:4] are
RAZ/WI, likely so that in future these can be used to extend LEN without
complicating the probing of the maximum available vector length.
Currently ZCR_EL3_LEN_MASK is defined as 0x1ff, covering both the LEN
field and the RAZ/WI bits.
To match the architecture as documented, reduce this down to 0xf, only
covering the bits currently allocated to the LEN field. We can extend
this in future if the LEN field is widened.
As the same time, rename ZCR_EL3_LEN_MASK to ZCR_EL3_LEN_MAX, as it is
used as a value rather than as a bit mask.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cc: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | arch/aarch64/boot.S | 2 | ||||
| -rw-r--r-- | arch/aarch64/include/asm/cpu.h | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/arch/aarch64/boot.S b/arch/aarch64/boot.S index 72c6b79..ee9ddaa 100644 --- a/arch/aarch64/boot.S +++ b/arch/aarch64/boot.S @@ -123,7 +123,7 @@ ASM_FUNC(_start) msr cptr_el3, x0 isb - mov x0, #ZCR_EL3_LEN_MASK // SVE: Enable full vector len + mov x0, #ZCR_EL3_LEN_MAX // SVE: Enable full vector len msr ZCR_EL3, x0 // for EL2. 1: diff --git a/arch/aarch64/include/asm/cpu.h b/arch/aarch64/include/asm/cpu.h index 63eb1c3..e3269b8 100644 --- a/arch/aarch64/include/asm/cpu.h +++ b/arch/aarch64/include/asm/cpu.h @@ -30,7 +30,7 @@ #define CPTR_EL3_EZ (1 << 8) #define ZCR_EL3 s3_6_c1_c2_0 -#define ZCR_EL3_LEN_MASK 0x1ff +#define ZCR_EL3_LEN_MAX 0xf #define SCTLR_EL1_CP15BEN (1 << 5) #define SCTLR_EL1_RES1 (3 << 28 | 3 << 22 | 1 << 11) |