Import Panasonic FZ-A1B changesHEADmaster

Unpacked from source.tgz [1] from Panasonic OSS web site [2].

[1] http://scw3sr02elb001-529496401.ap-northeast-1.elb.amazonaws.com/oss/tabletcomputer/FZA1B001/source.tgz
[2] https://panasonic.net/cns/oss/tabletcomputer/FZA1B001.html

150 files changed, 23756 insertions, 192 deletions

diff --git a/Makefile b/Makefile
index 77140eb7a2..c1323379e6 100644
--- a/Makefile
+++ b/Makefile
@@ -454,7 +454,7 @@ $(obj)spl/u-boot-spl.bin:		depend
 		$(MAKE) -C spl all
 
 $(TIMESTAMP_FILE):
-		@LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@
+		@LC_ALL=C date +'#define U_BOOT_DATE "%Y%m%d"' > $@
 		@LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@
 
 updater:
diff --git a/arch/arm/cpu/arm926ejs/armada100/cpu.c b/arch/arm/cpu/arm926ejs/armada100/cpu.c
index c21938e31f..14121a08f8 100644
--- a/arch/arm/cpu/arm926ejs/armada100/cpu.c
+++ b/arch/arm/cpu/arm926ejs/armada100/cpu.c
@@ -24,8 +24,8 @@
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/armada100.h>
-#include <asm/io.h>
 
 #define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
 #define SET_MRVL_ID	(1<<8)
diff --git a/arch/arm/cpu/arm926ejs/armada100/dram.c b/arch/arm/cpu/arm926ejs/armada100/dram.c
index eacec2386d..8609004565 100644
--- a/arch/arm/cpu/arm926ejs/armada100/dram.c
+++ b/arch/arm/cpu/arm926ejs/armada100/dram.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/armada100.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/arm926ejs/armada100/timer.c b/arch/arm/cpu/arm926ejs/armada100/timer.c
index 82a6d7b72d..fbade4b459 100644
--- a/arch/arm/cpu/arm926ejs/armada100/timer.c
+++ b/arch/arm/cpu/arm926ejs/armada100/timer.c
@@ -24,6 +24,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/armada100.h>
 
 /*
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
index b4a4c0428f..8f04ddbb86 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/cpu.c
@@ -26,6 +26,8 @@
 #include <netdev.h>
 #include <asm/cache.h>
 #include <u-boot/md5.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <hush.h>
 
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/dram.c b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
index 2441554ae3..181b3e7bd3 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/dram.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/dram.c
@@ -24,6 +24,8 @@
 
 #include <config.h>
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
index b2f0ad55e3..3da6c98d11 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/mpp.c
@@ -10,6 +10,8 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 
diff --git a/arch/arm/cpu/arm926ejs/kirkwood/timer.c b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
index b4f6cf87e0..a98f54c05b 100644
--- a/arch/arm/cpu/arm926ejs/kirkwood/timer.c
+++ b/arch/arm/cpu/arm926ejs/kirkwood/timer.c
@@ -22,6 +22,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/kirkwood.h>
 
 #define UBOOT_CNTR	0	/* counter to use for uboot timer */
diff --git a/arch/arm/cpu/arm926ejs/pantheon/cpu.c b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
index 8b2eafa40b..8f94ea90ae 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/cpu.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/cpu.c
@@ -23,8 +23,8 @@
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pantheon.h>
-#include <asm/io.h>
 
 #define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
 #define SET_MRVL_ID	(1<<8)
@@ -42,6 +42,9 @@ int arch_cpu_init(void)
 	struct panthmpmu_registers *mpmu =
 		(struct panthmpmu_registers*) PANTHEON_MPMU_BASE;
 
+	struct panthapmu_registers *apmu =
+		(struct panthapmu_registers *) PANTHEON_APMU_BASE;
+
 	/* set SEL_MRVL_ID bit in PANTHEON_CPU_CONF register */
 	val = readl(&cpuregs->cpu_conf);
 	val = val | SET_MRVL_ID;
@@ -65,6 +68,20 @@ int arch_cpu_init(void)
 	writel(APBC_FNCLK | APBC_APBCLK, &apbclkres->twsi);
 #endif
 
+#ifdef CONFIG_MV_SDHCI
+	/* Enable mmc clock */
+	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+			&apmu->sd1);
+	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+			&apmu->sd3);
+#endif
+
+#ifdef CONFIG_MV_UDC
+	/* Enable usb clock */
+	writel(APMU_PERI_CLK | APMU_AXI_CLK | APMU_PERI_RST | APMU_AXI_RST,
+			&apmu->usb);
+#endif
+
 	icache_enable();
 
 	return 0;
@@ -88,3 +105,17 @@ void i2c_clk_enable(void)
 {
 }
 #endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+
+void  flush_cache(unsigned long start, unsigned long size)
+{
+	/* clean & invalidate all D cache */
+	asm("mcr p15, 0, %0, c7, c14, 0" : : "r" (0));
+}
+#endif
diff --git a/arch/arm/cpu/arm926ejs/pantheon/dram.c b/arch/arm/cpu/arm926ejs/pantheon/dram.c
index bbca7eef16..a3d719e5cf 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/dram.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/dram.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/io.h>
 #include <asm/arch/pantheon.h>
 
 DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/cpu/arm926ejs/pantheon/timer.c b/arch/arm/cpu/arm926ejs/pantheon/timer.c
index c71162a8be..17045b1c2f 100644
--- a/arch/arm/cpu/arm926ejs/pantheon/timer.c
+++ b/arch/arm/cpu/arm926ejs/pantheon/timer.c
@@ -23,6 +23,7 @@
  */
 
 #include <common.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/pantheon.h>
 
 /*
diff --git a/arch/arm/cpu/armv7/armada610/Makefile b/arch/arm/cpu/armv7/armada610/Makefile
new file mode 100644
index 0000000000..e622e66b87
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada610/Makefile
@@ -0,0 +1,47 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= timer.o cpu.o dram.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/armada610/cpu.c b/arch/arm/cpu/armv7/armada610/cpu.c
new file mode 100644
index 0000000000..8fae10538c
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada610/cpu.c
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada610.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+#define CPUID_ID	        0
+extern unsigned int mv_stepping;
+
+int cpu_is_armada610_z0(void)
+{
+    unsigned int chip_id;
+    unsigned int id;
+    if (mv_stepping)
+        return 0;
+    chip_id = __raw_readl(0xd4282c00);
+	id = read_cpuid(CPUID_ID);
+	if (__cpu_is_armada610(id) && ((chip_id & 0x00ff0000) == 0x00f00000))
+        return 1;
+	else
+        return 0;
+}
+
+int cpu_is_armada610_z1(void)
+{
+    unsigned int chip_id;
+    unsigned int id;
+    if (mv_stepping)
+        return 0;
+	chip_id = __raw_readl(0xd4282c00);
+	id = read_cpuid(CPUID_ID);
+	if (__cpu_is_armada610(id) && ((chip_id & 0x00ff0000) == 0x00e00000))
+		return 1;
+	else
+		return 0;
+}
+
+int cpu_is_armada610(void)
+{
+	unsigned int id = read_cpuid(CPUID_ID);
+	return __cpu_is_armada610(id);
+}
+
+int cpu_is_armada610_a0(void)
+{
+	if (mv_stepping == 0xa0)
+		return 1;
+	else
+		return 0;
+}
+
+int cpu_is_armada610_a1(void)
+{
+	if (mv_stepping == 0xa1)
+		return 1;
+	else
+		return 0;
+}
+
+int cpu_is_armada610_a2(void)
+{
+	if (mv_stepping == 0xa2)
+		return 1;
+	else
+		return 0;
+}
+
+int arch_cpu_init(void)
+{
+	struct armd6mpmu_registers *mpmu =
+		(struct armd6mpmu_registers *) AMAD6_MPMU_BASE;
+
+	struct armd6apbc_registers *apbc =
+		(struct armd6apbc_registers *) AMAD6_APBC_BASE;
+
+	struct armd6apmu_registers *apmu =
+		(struct armd6apmu_registers *) AMAD6_APMU_BASE;
+
+	/* Turn on clock gating (PMUM_CGR_PJ) */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on APB, PLL1, PLL2 clock */
+	writel(0x1FFFF, &apmu->gbl_clkctrl);
+
+	/* Turn on AIB clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->aib);
+
+	/* Turn on uart3 clock */
+	writel(UARTCLK14745KHZ, &apbc->uart3);
+
+	/* Turn on timer clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(0x3), &apbc->timers);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->gpio);
+
+	/* Enable twsi1,5,6 clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi1);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi5);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi6);
+
+	icache_enable();
+
+#ifdef CONFIG_MV_SDHCI
+	/* Enable SD1 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+		APMU_AXI_RESET | (1 << 10), &apmu->sd1);
+
+	/* Enable SD3 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+		APMU_AXI_RESET, &apmu->sd3);
+#endif
+
+	/* Enable USB clock */
+	writel(APMU_AXI_CLK_EN | APMU_AXI_RESET, &apmu->usb);
+	writel(0xffff, &apmu->usb_dyn_gate);
+
+#ifdef CONFIG_PXA168_FB
+	/* Enable display clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+		APMU_AXI_RESET | CLK_DIV_SEL(2) | CLK_SEL(2) | DSI_ESCCLK_EN |\
+		DIS_CLK_PLL_SEL | DSI_PHY_SLOW_CLK_EN, &apmu->display1);
+	writel(PLL1_1P5M_EN, &mpmu->pll1);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->pwm3);
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+int print_cpuinfo(void)
+{
+	u32 id;
+	struct armd6cpu_registers *cpuregs =
+		(struct armd6cpu_registers *) AMAD6_CPU_BASE;
+
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   ARMADA610 88AP%X-%X\n", (id & 0xFFF), (id >> 0x10));
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/armada610/dram.c b/arch/arm/cpu/armv7/armada610/dram.c
new file mode 100644
index 0000000000..05fc871436
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada610/dram.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada610.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * armd6_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd6_sdram_base(int chip_sel)
+{
+	struct armd6ddr_registers *ddr_regs =
+		(struct armd6ddr_registers *)AMAD6_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd6_sdram_size - reads SDRAM size
+ */
+u32 armd6_sdram_size(int chip_sel)
+{
+	struct armd6ddr_registers *ddr_regs =
+		(struct armd6ddr_registers *)AMAD6_DRAM_BASE;
+	u32 result = 0;
+	u32 CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return (0x8 << (result - 0x7)) * 1024 * 1024;
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	int i;
+
+	gd->ram_size = 0;
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = armd6_sdram_base(i);
+		gd->bd->bi_dram[i].size = armd6_sdram_size(i);
+		/*
+		 * It is assumed that all memory banks are consecutive
+		 * and without gaps.
+		 * If the gap is found, ram_size will be reported for
+		 * consecutive memory only
+		 */
+		if (gd->bd->bi_dram[i].start != gd->ram_size)
+			break;
+
+		gd->ram_size += gd->bd->bi_dram[i].size;
+
+	}
+
+	for (; i < CONFIG_NR_DRAM_BANKS; i++) {
+		/*
+		 * If above loop terminated prematurely, we need to set
+		 * remaining banks' start address & size as 0. Otherwise other
+		 * u-boot functions and Linux kernel gets wrong values which
+		 * could result in crash
+		 */
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	dram_init();
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/armada610/timer.c b/arch/arm/cpu/armv7/armada610/timer.c
new file mode 100644
index 0000000000..336ce41f61
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada610/timer.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada610.h>
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd6timer_registers *armd6timers =
+		(struct armd6timer_registers *) AMAD6_TIMER_BASE;
+	int loop = 100;
+	ulong val;
+
+	writel(COUNT_RD_REQ, &armd6timers->cvwr);
+	while (loop--)
+		val = readl(&armd6timers->cvwr);
+
+	/*
+	 * This stop gcc complain and prevent loop mistake init to 0
+	 */
+	val = readl(&armd6timers->cvwr);
+
+	return val;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime)
+		;
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd6apbc_registers *apb1clkres =
+		(struct armd6apbc_registers *) AMAD6_APBC_BASE;
+	struct armd6timer_registers *armd6timers =
+		(struct armd6timer_registers *) AMAD6_TIMER_BASE;
+
+	/* Enable Timer clock at 6.5 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1),
+			&apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd6timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd6timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd6timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x0, &armd6timers->preload_ctrl[TIMER]);
+
+	/* Enable count 0 */
+	writel(0x1, &armd6timers->cer);
+	/* Set free run mode */
+	writel(0x1, &armd6timers->cmr);
+
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/armada620/Makefile b/arch/arm/cpu/armv7/armada620/Makefile
new file mode 100644
index 0000000000..0388b3a346
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada620/Makefile
@@ -0,0 +1,48 @@
+#
+# (C) Copyright 2011
+# Marvell Semiconductor <www.marvell.com>
+# Written-by: Lei Wen <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(SOC).o
+
+COBJS	= timer.o cpu.o dram.o
+SOBJS	= smp_init.o
+
+SRCS	:= $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
+START	:= $(addprefix $(obj),$(START))
+
+all:	$(obj).depend $(LIB)
+
+$(LIB):	$(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS)
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/arch/arm/cpu/armv7/armada620/cpu.c b/arch/arm/cpu/armv7/armada620/cpu.c
new file mode 100644
index 0000000000..d98f2ba9f2
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada620/cpu.c
@@ -0,0 +1,204 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada620.h>
+
+#define UARTCLK14745KHZ	(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1))
+int arch_cpu_init(void)
+{
+	struct armd6mpmu_registers *mpmu =
+		(struct armd6mpmu_registers *) AMAD6_MPMU_BASE;
+
+	struct armd6apbc_registers *apbc =
+		(struct armd6apbc_registers *) AMAD6_APBC_BASE;
+
+	struct armd6apmu_registers *apmu =
+		(struct armd6apmu_registers *) AMAD6_APMU_BASE;
+
+	struct armd6cpu_registers *cpuregs =
+		(struct armd6cpu_registers *) AMAD6_CPU_BASE;
+
+	/* Start of day */
+	writel(readl(&apmu->genctrl) | 0x70, &apmu->genctrl);
+	writel(readl(&mpmu->sccr) | 0x1, &mpmu->sccr);
+	writel(0x0, &apmu->sram_pd);
+
+	writel(readl(&cpuregs->mp1_pd) & ~(0xfc00) | 0x5400, &cpuregs->mp1_pd);
+	writel(readl(&cpuregs->mp2_pd) & ~(0xfc00) | 0x5400, &cpuregs->mp2_pd);
+	writel(readl(&cpuregs->mm_pd) & ~(0xfc00) | 0x5400, &cpuregs->mm_pd);
+
+	/* Turn off NF clock */
+	writel(readl(&apmu->nf) & ~(0x3f), &apmu->nf);
+
+	/* Turn off SMC clock */
+	writel(readl(&apmu->smc) & ~(0x1f), &apmu->smc);
+
+	/* Turn on clock gating (PMUM_CGR_PJ) */
+	writel(0xFFFFFFFF, &mpmu->acgr);
+
+	/* Turn on APB, PLL1, PLL2 clock */
+	writel(0x1FFFF, &apmu->gbl_clkctrl);
+
+	/* Turn on AIB clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->aib);
+
+	/* Turn on uart3 clock */
+	writel(UARTCLK14745KHZ, &apbc->uart3);
+
+	/* Turn on timer clock */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(0x3), &apbc->timers);
+
+	/* Enable GPIO clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->gpio);
+
+	/* Enable twsi1,3,5,6 clock */
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi1);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi3);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi5);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->twsi6);
+
+	icache_enable();
+
+#ifdef CONFIG_MV_SDHCI
+	/* Enable SD1 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+	       APMU_AXI_RESET | (1 << 10), &apmu->sd1);
+
+	/* Enable SD3 clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+	       APMU_AXI_RESET, &apmu->sd3);
+#endif
+
+	/* Enable USB clock */
+	writel(USB_26M_SEL | APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | \
+	       APMU_PERIPH_RESET | APMU_AXI_RESET, &apmu->fsic3);
+	writel(APMU_AXI_CLK_EN | APMU_AXI_RESET, &apmu->usb);
+	writel(0xffff, &apmu->usb_dyn_gate);
+
+#ifdef CONFIG_PXA168_FB
+	/* Enable display clock */
+	writel(APMU_PERIPH_CLK_EN | APMU_AXI_CLK_EN | APMU_PERIPH_RESET | \
+		APMU_AXI_RESET | CLK_DIV_SEL(1) | CLK_SEL(2) | DSI_ESCCLK_EN |\
+		DSI_PHY_SLOW_CLK_EN, &apmu->display1);
+	writel(APBC_APBCLK | APBC_FNCLK, &apbc->pwm3);
+	/*Enable PLL3 for DSI PLL as 1GHz*/
+	writel(readl(&mpmu->pll3_ctl2) | SEL_VCO_CLK_SE, &mpmu->pll3_ctl2);
+	writel(VCODIV_SEL_SE(0x2) | ICP(0x4) | KVCO(0x5) | CTUNE(0x2)
+	      | VCO_VRNG(0x4) | VREG_IVREF(0x2) | VDDM(0x1) | VDDL(0x9),
+	      &mpmu->pll3_ctl1);
+	/*MPMU_PLL3CR: Program PLL3 VCO for 2.0Ghz -REFD = 3;*/
+	if ((readl(&apmu->fsic3) & USB_PHY_REF_MASK) == USB_PHY_26M)
+		writel(PLL3_REFDIV(0x3) | FBDIV(0xe6) | PLL3_ACTV_CNTRL,
+		       &mpmu->pll3_cr);
+	else
+		writel(PLL3_REFDIV(0x3) | FBDIV(0xf6) | PLL3_ACTV_CNTRL,
+		       &mpmu->pll3_cr);
+
+	/* PLL3 Control register -Enable SW PLL3*/
+	writel(readl(&mpmu->pll3_cr) | PLL3_SW_EN, &mpmu->pll3_cr);
+
+	/* wait for PLLs to lock*/
+	udelay(500);
+
+	/* PMUM_PLL3_CTRL1: take PLL3 out of reset*/
+	writel(readl(&mpmu->pll3_ctl1) | PLL_RST, &mpmu->pll3_ctl1);
+	udelay(500);
+#endif
+
+#ifdef CONFIG_ARMADA100_FEC
+	/* Enable Fast Ethernet clock */
+	writel(FE_CLK_SRC_SEL | FE_CLKEN | FE_ACLKEN, &apmu->fastenet);
+	udelay(500);
+	writel(FE_CLK_SRC_SEL | FE_CLKEN | FE_ACLKEN | FE_SW_RSTN | FE_AXI_SW_RSTN,
+		&apmu->fastenet);
+#endif
+	return 0;
+}
+
+int cpu_is_ax(void)
+{
+	struct armd6cpu_registers *cpuregs =
+		(struct armd6cpu_registers *) AMAD6_CPU_BASE;
+	u32 id;
+
+	id = readl(&cpuregs->chip_id);
+	return ((id >> 20) & 0xf) == 0xa;
+}
+
+int cpu_is_bx(void)
+{
+	struct armd6cpu_registers *cpuregs =
+		(struct armd6cpu_registers *) AMAD6_CPU_BASE;
+	u32 id;
+
+	id = readl(&cpuregs->chip_id);
+	return ((id >> 20) & 0xf) == 0xb;
+}
+
+#if defined(CONFIG_DISPLAY_CPUINFO)
+extern void wtm_read_stepping(void);
+extern unsigned int mv_soc_stepping;
+int print_cpuinfo(void)
+{
+	u32 id;
+	char *stepping;
+	struct armd6cpu_registers *cpuregs =
+		(struct armd6cpu_registers *) AMAD6_CPU_BASE;
+
+	wtm_read_stepping();
+	switch (mv_soc_stepping) {
+	case 0x4130:
+		stepping = "A0"; break;
+	case 0x4131:
+		stepping = "A1"; break;
+	case 0x4132:
+		stepping = "A2"; break;
+	case 0x4230:
+		stepping = "B0"; break;
+	case 0x423050:
+		stepping = "B0P"; break;
+	default:
+		stepping = "unknown"; break;
+	}
+	id = readl(&cpuregs->chip_id);
+	printf("SoC:   ARMADA620 88AP%X-%s\n", (id & 0xFFFF), stepping);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_I2C_MV
+void i2c_clk_enable(void)
+{
+}
+#endif
+
+#ifndef CONFIG_SYS_DCACHE_OFF
+void enable_caches(void)
+{
+	/* Enable D-cache. I-cache is already enabled in start.S */
+	dcache_enable();
+}
+#endif
diff --git a/arch/arm/cpu/armv7/armada620/dram.c b/arch/arm/cpu/armv7/armada620/dram.c
new file mode 100644
index 0000000000..0cac790a00
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada620/dram.c
@@ -0,0 +1,216 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>,
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada620.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * armd6_sdram_base - reads SDRAM Base Address Register
+ */
+u32 armd6_sdram_base(int chip_sel, u32 base)
+{
+	struct armd6ddr_registers *ddr_regs;
+	u32 result = 0;
+	u32 CS_valid;
+
+	ddr_regs = (struct armd6ddr_registers *)base;
+	CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs) & 0xFF800000;
+	return result;
+}
+
+/*
+ * armd6_sdram_size - reads SDRAM size
+ */
+u32 armd6_sdram_size(int chip_sel, u32 base)
+{
+	struct armd6ddr_registers *ddr_regs;
+	u32 result = 0;
+	u32 CS_valid;
+
+	ddr_regs = (struct armd6ddr_registers *)base;
+	CS_valid = 0x01 & readl(&ddr_regs->mmap[chip_sel].cs);
+	if (!CS_valid)
+		return 0;
+
+	result = readl(&ddr_regs->mmap[chip_sel].cs);
+	result = (result >> 16) & 0xF;
+	if (result < 0x7) {
+		printf("Unknown DRAM Size\n");
+		return -1;
+	} else {
+		return (0x8 << (result - 0x7)) * 1024 * 1024;
+	}
+}
+
+#ifndef CONFIG_SYS_BOARD_DRAM_INIT
+int dram_init(void)
+{
+	/* This confine uboot relocation final range */
+	gd->ram_size = CONFIG_FIX_RAMSIZE;
+
+	return 0;
+}
+
+u32 dram_interleave_size(void)
+{
+	if (cpu_is_ax()) {
+		switch ((readl(0xd4282984) & 0x3f0000) >> 16) {
+		case 0x1:	return 0x00001000;
+		case 0x2:	return 0x00004000;
+		case 0x4:	return 0x00010000;
+		case 0x8:	return 0x00040000;
+		case 0x10:	return 0x00100000;
+		case 0x20:	return 0x40000000;
+		}
+	} else {
+		switch (readl(0xd4282ca0) & 0x7f) {
+		case 0x1:	return 0x00001000;
+		case 0x2:	return 0x00004000;
+		case 0x4:	return 0x00010000;
+		case 0x8:	return 0x00040000;
+		case 0x10:	return 0x00100000;
+		case 0x20:	return 0x20000000;
+		case 0x40:	return 0x40000000;
+		}
+	}
+	return 0;
+}
+
+/*
+ * If this function is not defined here,
+ * board.c alters dram bank zero configuration defined above.
+ */
+void dram_init_banksize(void)
+{
+	int i;
+	u32 itlvsize, base, high_edge;
+
+	/**
+	 *
+	 *  some assumptions on the working MC configuration to simplify things
+	 *  1. lower CS on lower address
+	 *  2. no space overlap
+	 *  3. multiple CS address mapping in to one contiguous space
+	 *  4. always using lower CS
+	 *  5. in dual MC configuration, both MC use the same space setup
+	 *  6. DDR reserved space is 0x00000000-0x80000000
+	 *  7. no CS size smaller than 8MB
+	 *  8. CS starting address aligned to 8MB
+	 *  9. first CS address starts at 0x0, required by CPU reset vector
+	 *
+	 *  With above assumption we can only read the first address and
+	 *  add up all size.
+	 */
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		gd->bd->bi_dram[i].start = 0;
+		gd->bd->bi_dram[i].size = 0;
+	}
+
+
+	/* read the first MC configuration */
+	base = AMAD6_DRAM_BASE;
+	gd->bd->bi_dram[0].start = armd6_sdram_base(0, base);
+	gd->bd->bi_dram[0].size = 0;
+	for (i = 0; i < CONFIG_DRAM_CSNUM_MAX; i++) {
+		/* since we assume all CS will be configured to be one range */
+		gd->bd->bi_dram[0].size += armd6_sdram_size(i, base);
+	}
+
+	/* now process interleave */
+	itlvsize = dram_interleave_size();
+	if (itlvsize != 0) {
+		if (gd->bd->bi_dram[0].size > itlvsize) {
+			/**
+			 *  there is no holes in the space, just double it
+			 *  Ax has a bug that lead to loss of half memory
+			 */
+			if (!cpu_is_ax())
+				gd->bd->bi_dram[0].size *= 2;
+		} else {
+			/* hole */
+			if (CONFIG_NR_DRAM_BANKS > 1) {
+				gd->bd->bi_dram[1].start =
+					gd->bd->bi_dram[0].start + itlvsize;
+				gd->bd->bi_dram[1].size =
+					gd->bd->bi_dram[0].size;
+			}
+		}
+	}
+
+
+	/*
+
+	high_edge = 0x80000000;
+
+	 * workaround for Ax and B0
+	 * According to JIRA MMP3-1713, the 0x7FF00000~0x7FFFFFFF memory space
+	 * is mapped to ROM space, no for DDR. Remove the range
+	 */
+	high_edge = 0x7FF00000;
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (gd->bd->bi_dram[i].start < high_edge) {
+			/* start not in range */
+			if ((gd->bd->bi_dram[i].start
+				+ gd->bd->bi_dram[i].size) >= high_edge) {
+				gd->bd->bi_dram[i].size =
+					high_edge - gd->bd->bi_dram[i].start;
+				/* space beyong 0x80000000 not in DDR space */
+			}
+		} else {
+			gd->bd->bi_dram[i].start = 0;
+			gd->bd->bi_dram[i].size = 0;
+		}
+	}
+
+
+	/* space always starts @ 0x0 */
+	if (gd->bd->bi_dram[0].size < CONFIG_TZ_HYPERVISOR_SIZE) {
+		/* should not happen, TZ MAX to 128MB */
+		printf("Cannot meet requirement for trustzone hypervisor\n");
+	} else {
+		gd->bd->bi_dram[0].start += CONFIG_TZ_HYPERVISOR_SIZE;
+		gd->bd->bi_dram[0].size  -= CONFIG_TZ_HYPERVISOR_SIZE;
+	}
+
+	for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+		if (gd->bd->bi_dram[i].size > 0) {
+			printf("DRAM_BANKS[%d]: 0x%08x, 0x%08x\n"
+				, i
+				, (unsigned int)gd->bd->bi_dram[i].start
+				, (unsigned int)gd->bd->bi_dram[i].size
+				);
+		}
+	}
+
+	return;
+}
+#endif /* CONFIG_SYS_BOARD_DRAM_INIT */
diff --git a/arch/arm/cpu/armv7/armada620/smp_init.S b/arch/arm/cpu/armv7/armada620/smp_init.S
new file mode 100644
index 0000000000..ad3606d889
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada620/smp_init.S
@@ -0,0 +1,265 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ * Jason Chagas <jason.chagas@marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * NOTE: Stack isn't setup yet when these subroutines are called.
+ * So we donot push the registers onto Stack during entry.
+ */
+
+pj4_common_int:
+
+	ldr	r1, =0xE0000100		@ CPU Int interfaces
+	mov	r0, #0x1		@ Enable SGI #0
+	str	r0, [r1, #0x0]		@ ... on ISER0
+	mov	r0, #0xF0		@ Enable SPIs
+	str	r0, [r1, #0x4]		@ ... on ISER1
+
+	mov	pc, lr			@ return
+
+cpu_die:
+	@ r0 = cpuid
+	@ r2 = idle_cfg register address
+	@ r3 = pj_cc4 register address
+	@ default C2 internal clock gate
+	@ disable FIQ and IRQ
+	mrs	r1, cpsr
+	orr	r1, r1, #0xc0
+	msr	cpsr_c, r1
+
+	@ disable GIC CPU interface
+	ldr	r4, =0xE0000100
+	mov	r1, #0
+	str	r1, [r4]
+
+	@ set idle_cfg register
+	ldr	r1, [r2]
+	orr	r1, r1, #(1<<1)		@ external idle
+	orr	r1, r1, #(1<<5)		@ core power down
+	orr	r1, r1, #(1<<6)		@ sram/L1 power down
+	@ no need to set these two bits for b0
+	@ orr	r1, r1, #(1<<7)		@ sram/L2 power down
+	@ orr	r1, r1, #(1<<25)
+	str	r1, [r2]
+
+	@clear pj_cc4 L1_LOW_LEAK_DIS
+	ldr	r1, [r3]
+	bic	r1, r1, #(1<<13)	@ L1_LOW_LEAK_DIS
+	str	r1, [r3]
+
+	@set pj_cc4 to mask gic global interrupt
+1:	ldr	r1, [r3]
+	orr	r1, r1, #(1<<0)
+	str	r1, [r3]
+
+	.word	0xf57ff04f		@ DSB
+	.word	0xe320f003		@ WFI
+
+	@clear pj_cc4 to mask gic global interrupt
+	ldr	r1, [r3]
+	bic	r1, r1, #(1<<0)
+	str	r1, [r3]
+
+	@wake from c2, check whether has GIC pending
+	ldr	r4, =0xE0000100
+	ldr	r1, [r4, #0xc]
+	str	r1, [r4, #0x10]
+
+	b	1b
+
+/*
+ MMP3 BOOTSTRAP - Begin
+#define USE_MM_AS_MAIN_CORE
+#define USE_MM
+*/
+#define USE_MP1
+#define USE_MP2
+
+bootstrap:
+	@ Turn core interrupts off
+	mrs	r0, cpsr
+	orr	r0, r0, #0xc0	@ disable FIQ & IRQ
+	msr	cpsr_c, r0
+
+	@ Check core id
+	mov	r2, #0
+	mrc	p15, 0, r0, c0, c0, 5	@ read  MPIDR
+	and	r0, r0, #0xf		@ Fetch CPUID
+	cmp	r0, #1			@MP2
+#ifndef USE_MP2
+	ldreq	r2, =0xd4282a00
+	ldr 	r3, =0xd4282a4c
+#endif
+	beq	core_stub
+
+	cmp	r0, #0			@MP1
+#ifndef USE_MP1
+	ldreq	r2, =0xd4282818
+	ldr	r3, =0xd4282a48
+#endif
+	beq	core_stub
+
+	cmp	r0, #2			@MM
+#ifndef USE_MM
+	ldreq	r2, =0xd4282a04
+	ldr	r3, =0xd4282a50
+#endif
+	beq	core_stub
+
+	b	bootstrap_endless_loop
+
+core_stub:
+	bl	pj4_common_int
+
+	ands	r2, r2, r2
+	@ core die ?
+	bne	cpu_die			@ never returns
+
+	@ Use scratch register
+	ldr	r1, =0xD4282C24		@ __sw_branch
+	mov	r0, #0x0		@ clear SW branch reg
+	str	r0, [r1, #0x0]		@ ...
+
+	@ FIXME! - For now, use delay loop before checking the address
+1:	mov	r3, #0x4000
+2:	subs	r3, r3, #1
+	bne	2b
+
+	ldr	r0, [r1, #0x0]		@ load sw branch address
+	cmp	r0, #0x0		@ contains an address?
+	movne	pc, r0			@ yes, then branch
+	b	1b			@ otherwise, loop again
+
+bootstrap_endless_loop:
+1:	b	1b
+
+.ltorg
+
+.globl smp_hw_cpuid
+       .type   smp_hw_cpuid, %function
+smp_hw_cpuid:
+	mrc	p15, 0, r0, c0, c0, 5	@ Read CPUID register
+	and	r0, r0, #0xf		@ Fetch CPUID
+	mov	pc, lr
+
+.ltorg
+
+.globl smp_config
+       .type   smp_config, %function
+smp_config:
+	stmfd	sp!, {r1-r3}
+	mov	r0, #0
+
+	ldr	r1, =0xd4050020
+	ldr	r3, [r1]
+	ands	r2, r3, #1 << 1
+#ifdef USE_MP1
+	orreq	r0, #1
+#endif
+	ldr	r1, =0xd4282950
+	ldr	r3, [r1]
+	ands	r2, r3, #1 << 25
+#ifdef USE_MP2
+	orrne	r0, #2
+#endif
+	ands	r2, r3, #1 << 26
+#ifdef USE_MM
+	orrne	r0, #4
+#endif
+
+	ldmfd	sp!, {r1-r3}
+	mov	pc, lr
+
+.ltorg
+
+/* MMP3 - Begin */
+.globl lowlevel_init
+	.type   lowlevel_init, %function
+lowlevel_init:
+	@ Save link register in r3
+	mov	r3, lr
+
+	@ PMUM_CGR_SP enable all clocks
+	ldr	r0, =0xd4050024
+	mov	r1, #0xffffffff
+	str	r1, [r0]
+
+	@ PMUM_CGR_PJ enable all clocks
+	ldr	r0, =0xd4051024
+	mov	r1, #0xffffffff
+	str	r1, [r0]
+
+	@ PMUA_GLB_CLK_CTRL enable all clocks
+	ldr	r0, =0xd42828DC
+	ldr	r1, =0x0003ffff
+	str	r1, [r0]
+
+	@ Ensure ICU_GBL_IRQ1_MSK is cleared
+	ldr	r0, =0xd4282110
+	mov	r1, #0x0
+	str	r1, [r0]
+
+	@ Set PMR to 0xE000_0000
+	ldr	r0, =0xd4282c94		@ CIU_MOLT_PERI_CFG_CTL1
+	ldr	r1, =0xe0000000
+	str	r1, [r0]
+
+	@ PMR Init
+	@ Enable PMR
+	ldr	r0, =0xd4282c9c
+	ldr	r1, =0xffffe001
+	str	r1, [r0]
+
+	@ PMUA_CC3_PJ
+	ldr	r0, =0xD4282988
+	ldr	r1, [r0]
+	orr	r1, r1, #(1<<3) @ PJ4_MP_TIMER_RST
+	orr	r1, r1, #(1<<4) @ PJ4_MP_TIMER_CLK_EN
+	str	r1, [r0]
+
+	@ PMUM_PRR_PJ - release mpcore 1 out of reset
+	ldr	r0, =0xd4050020
+	ldr	r1, [r0]
+	bic	r1, r1, #(1<<1)
+	str	r1, [r0]
+
+	@ PMUA_CC2_PJ - release mp2/mm out of reset
+	ldr	r0, =0xd4282950
+	ldr	r1, [r0]
+	orr	r1, r1, #(3<<25)
+	str	r1, [r0]
+
+	@ Check core where it run from
+	mrc	p15, 0, r0, c0, c0, 5	@ Read CPUID register
+	and	r0, r0, #0xf		@ Fetch CPUID
+#ifdef USE_MM_AS_MAIN_CORE
+	cmp	r0, #0x2		@ mm?
+#else
+	cmp	r0, #0x0		@ mpcore 1?
+#endif
+	bne	bootstrap		@ No, then jump to bootstrap code
+					@ Else, proceed with u-boot
+
+	@ Common init for PJ4
+	bl	pj4_common_int
+
+	mov	pc, r3			@ return
+/* MMP3 - End */
diff --git a/arch/arm/cpu/armv7/armada620/timer.c b/arch/arm/cpu/armv7/armada620/timer.c
new file mode 100644
index 0000000000..1d3f4dd069
--- /dev/null
+++ b/arch/arm/cpu/armv7/armada620/timer.c
@@ -0,0 +1,144 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/armada620.h>
+
+#define TIMER			0	/* Use TIMER 0 */
+/* Each timer has 3 match registers */
+#define MATCH_CMP(x)		((3 * TIMER) + x)
+#define TIMER_LOAD_VAL		0xffffffff
+#define	COUNT_RD_REQ		0x1
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * For preventing risk of instability in reading counter value,
+ * first set read request to register cvwr and then read same
+ * register after it captures counter value.
+ */
+ulong read_timer(void)
+{
+	struct armd6timer_registers *armd6timers =
+		(struct armd6timer_registers *) AMAD6_TIMER_BASE;
+	int loop = 100;
+	ulong val;
+
+	writel(COUNT_RD_REQ, &armd6timers->cvwr);
+	while (loop--)
+		val = readl(&armd6timers->cvwr);
+
+	/*
+	 * This stop gcc complain and prevent loop mistake init to 0
+	 */
+	val = readl(&armd6timers->cvwr);
+
+	return val;
+}
+
+void reset_timer_masked(void)
+{
+	/* reset time */
+	gd->tbl = read_timer();
+	gd->tbu = 0;
+}
+
+ulong get_timer_masked(void)
+{
+	ulong now = read_timer();
+
+	if (now >= gd->tbl) {
+		/* normal mode */
+		gd->tbu += now - gd->tbl;
+	} else {
+		/* we have an overflow ... */
+		gd->tbu += now + TIMER_LOAD_VAL - gd->tbl;
+	}
+	gd->tbl = now;
+
+	return gd->tbu;
+}
+
+void reset_timer(void)
+{
+	reset_timer_masked();
+}
+
+ulong get_timer(ulong base)
+{
+	return (get_timer_masked() / (CONFIG_SYS_HZ_CLOCK / 1000)) - base;
+}
+
+void set_timer(ulong t)
+{
+	gd->tbu = t;
+}
+
+void __udelay(unsigned long usec)
+{
+	ulong delayticks;
+	ulong endtime;
+
+	delayticks = (usec * (CONFIG_SYS_HZ_CLOCK / 1000000));
+	endtime = get_timer_masked() + delayticks;
+
+	while (get_timer_masked() < endtime)
+		;
+}
+
+/*
+ * init the Timer
+ */
+int timer_init(void)
+{
+	struct armd6apbc_registers *apb1clkres =
+		(struct armd6apbc_registers *) AMAD6_APBC_BASE;
+	struct armd6timer_registers *armd6timers =
+		(struct armd6timer_registers *) AMAD6_TIMER_BASE;
+
+	/* Enable Timer clock at 6.5 MHZ */
+	writel(APBC_APBCLK | APBC_FNCLK | APBC_FNCLKSEL(1),
+			&apb1clkres->timers);
+
+	/* load value into timer */
+	writel(0x0, &armd6timers->clk_ctrl);
+	/* Use Timer 0 Match Resiger 0 */
+	writel(TIMER_LOAD_VAL, &armd6timers->match[MATCH_CMP(0)]);
+	/* Preload value is 0 */
+	writel(0x0, &armd6timers->preload[TIMER]);
+	/* Enable match comparator 0 for Timer 0 */
+	writel(0x0, &armd6timers->preload_ctrl[TIMER]);
+
+	/* Enable count 0 */
+	writel(0x1, &armd6timers->cer);
+	/* Set free run mode */
+	writel(0x1, &armd6timers->cmr);
+
+	/* init the gd->tbu and gd->tbl value */
+	reset_timer_masked();
+
+	return 0;
+}
diff --git a/arch/arm/cpu/armv7/cpu.c b/arch/arm/cpu/armv7/cpu.c
index 091e3e0842..105ea6140c 100644
--- a/arch/arm/cpu/armv7/cpu.c
+++ b/arch/arm/cpu/armv7/cpu.c
@@ -80,3 +80,143 @@ int cleanup_before_linux(void)
 
 	return 0;
 }
+
+
+#ifdef CONFIG_CMD_MIPS
+
+static unsigned long loops_per_sec;
+#define PMNC_MASK	0x3f		/* Mask for writable bits */
+#define PMNC_E		(1 << 0)	/* Enable all counters */
+#define PMNC_P		(1 << 1)	/* Reset all counters */
+#define PMNC_C		(1 << 2)	/* Cycle counter reset */
+#define PMNC_D		(1 << 3)	/* CCNT counts every 64th cpu cycle */
+#define PMNC_X		(1 << 4)	/* Export to ETM */
+#define PMNC_DP		(1 << 5)	/* Disable CCNT if non-invasive debug*/
+
+#define FLAG_C		(1 << 31)
+#define FLAG_MASK	0x8000000f	/* Mask for writable bits */
+
+#define CNTENC_C	(1 << 31)
+#define CNTENC_MASK	0x8000000f	/* Mask for writable bits */
+
+#define CNTENS_C	(1 << 31)
+#define CNTENS_MASK	0x8000000f	/* Mask for writable bits */
+
+static inline u32 armv7_pmnc_read(void)
+{
+	u32 val;
+
+	asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
+	return val;
+}
+
+static inline void armv7_pmnc_write(u32 val)
+{
+	val &= PMNC_MASK;
+	asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r" (val));
+}
+
+static inline void armv7_pmnc_disable_counter(void)
+{
+	u32 val;
+
+	val = CNTENC_C;
+
+	val &= CNTENC_MASK;
+	asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
+}
+
+static void armv7_pmnc_reset_counter(void)
+{
+	u32 val = 0;
+
+	asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (val));
+}
+
+
+static inline void armv7_pmnc_enable_counter(void)
+{
+	u32 val;
+
+	val = CNTENS_C;
+	val &= CNTENS_MASK;
+	asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
+}
+
+static inline void armv7_start_pmnc(void)
+{
+	armv7_pmnc_write(armv7_pmnc_read() | PMNC_E);
+}
+
+static inline void armv7_stop_pmnc(void)
+{
+	armv7_pmnc_write(armv7_pmnc_read() & ~PMNC_E);
+}
+
+static inline u32 armv7_counter_read(void)
+{
+	u32 val;
+
+	asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
+	return val;
+}
+
+static inline u32 armv7_pmnc_getreset_flags(void)
+{
+	u32 val;
+
+	/* Read */
+	asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
+
+	/* Write to clear flags */
+	val &= FLAG_MASK;
+	asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
+
+	return val;
+}
+
+int do_calibrate_delay(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong oldtimer, timer;
+	unsigned int val, val_new;
+	unsigned int flags;
+
+	loops_per_sec = 0;
+	printf("Calibrating delay loop.. ");
+
+	armv7_pmnc_write(PMNC_P | PMNC_C);
+	armv7_pmnc_disable_counter();
+	armv7_pmnc_reset_counter();
+	armv7_pmnc_enable_counter();
+	val = armv7_counter_read();
+	armv7_start_pmnc();
+
+	oldtimer = get_timer_masked();
+	while (1) {
+		timer = get_timer_masked();
+		timer = timer - oldtimer;
+		if (timer >= CONFIG_SYS_HZ_CLOCK)
+			break;
+	}
+
+	armv7_stop_pmnc();
+	val_new = armv7_counter_read();
+	flags = armv7_pmnc_getreset_flags();
+	if (flags & FLAG_C)
+		printf("counter overflow\n");
+	loops_per_sec = val_new - val;
+
+	printf("ok - %lu.%02lu BogoMips\n",
+			loops_per_sec/1000000,
+			(loops_per_sec/10000) % 100);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+		mips,	6,	1,	do_calibrate_delay,
+		"mips	- calculating BogoMips\n",
+		" - calculating BogoMips\n"
+	  );
+
+#endif
diff --git a/arch/arm/include/asm/arch-armada100/armada100.h b/arch/arm/include/asm/arch-armada100/armada100.h
index d5d125a963..f23291c0a4 100644
--- a/arch/arm/include/asm/arch-armada100/armada100.h
+++ b/arch/arm/include/asm/arch-armada100/armada100.h
@@ -26,13 +26,7 @@
 #ifndef _ASM_ARCH_ARMADA100_H
 #define _ASM_ARCH_ARMADA100_H
 
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif	/* __ASSEMBLY__ */
-
 #if defined (CONFIG_ARMADA100)
-#include <asm/arch/cpu.h>
 
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
@@ -43,6 +37,7 @@
 
 /* Register Base Addresses */
 #define ARMD1_DRAM_BASE		0xB0000000
+#define ARMD1_FEC_BASE		0xC0800000
 #define ARMD1_TIMER_BASE	0xD4014000
 #define ARMD1_APBC1_BASE	0xD4015000
 #define ARMD1_APBC2_BASE	0xD4015800
@@ -60,62 +55,5 @@
 #define ARMD1_APMU_BASE		0xD4282800
 #define ARMD1_CPU_BASE		0xD4282C00
 
-/*
- * Main Power Management (MPMU) Registers
- * Refer Datasheet Appendix A.8
- */
-struct armd1mpmu_registers {
-	u8 pad0[0x08 - 0x00];
-	u32 fccr;	/*0x0008*/
-	u32 pocr;	/*0x000c*/
-	u32 posr;	/*0x0010*/
-	u32 succr;	/*0x0014*/
-	u8 pad1[0x030 - 0x014 - 4];
-	u32 gpcr;	/*0x0030*/
-	u8 pad2[0x200 - 0x030 - 4];
-	u32 wdtpcr;	/*0x0200*/
-	u8 pad3[0x1000 - 0x200 - 4];
-	u32 apcr;	/*0x1000*/
-	u32 apsr;	/*0x1004*/
-	u8 pad4[0x1020 - 0x1004 - 4];
-	u32 aprr;	/*0x1020*/
-	u32 acgr;	/*0x1024*/
-	u32 arsr;	/*0x1028*/
-};
-
-/*
- * APB1 Clock Reset/Control Registers
- * Refer Datasheet Appendix A.10
- */
-struct armd1apb1_registers {
-	u32 uart1;	/*0x000*/
-	u32 uart2;	/*0x004*/
-	u32 gpio;	/*0x008*/
-	u32 pwm1;	/*0x00c*/
-	u32 pwm2;	/*0x010*/
-	u32 pwm3;	/*0x014*/
-	u32 pwm4;	/*0x018*/
-	u8 pad0[0x028 - 0x018 - 4];
-	u32 rtc;	/*0x028*/
-	u32 twsi0;	/*0x02c*/
-	u32 kpc;	/*0x030*/
-	u32 timers;	/*0x034*/
-	u8 pad1[0x03c - 0x034 - 4];
-	u32 aib;	/*0x03c*/
-	u32 sw_jtag;	/*0x040*/
-	u32 timer1;	/*0x044*/
-	u32 onewire;	/*0x048*/
-	u8 pad2[0x050 - 0x048 - 4];
-	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
-	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
-	u8 pad3[0x06c - 0x054 - 4];
-	u32 twsi1;	/*0x06c*/
-	u32 uart3;	/*0x070*/
-	u8 pad4[0x07c - 0x070 - 4];
-	u32 timer2;	/*0x07C*/
-	u8 pad5[0x084 - 0x07c - 4];
-	u32 ac97;	/*0x084*/
-};
-
 #endif /* CONFIG_ARMADA100 */
 #endif /* _ASM_ARCH_ARMADA100_H */
diff --git a/arch/arm/include/asm/arch-armada100/config.h b/arch/arm/include/asm/arch-armada100/config.h
index 1126b38a27..d2094e5303 100644
--- a/arch/arm/include/asm/arch-armada100/config.h
+++ b/arch/arm/include/asm/arch-armada100/config.h
@@ -31,6 +31,7 @@
 #ifndef _ARMD1_CONFIG_H
 #define _ARMD1_CONFIG_H
 
+#include <asm/arch/armada100.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
diff --git a/arch/arm/include/asm/arch-armada100/cpu.h b/arch/arm/include/asm/arch-armada100/cpu.h
index 0518a6a4b0..f7ec938868 100644
--- a/arch/arm/include/asm/arch-armada100/cpu.h
+++ b/arch/arm/include/asm/arch-armada100/cpu.h
@@ -29,6 +29,63 @@
 #include <asm/system.h>
 
 /*
+ * Main Power Management (MPMU) Registers
+ * Refer Datasheet Appendix A.8
+ */
+struct armd1mpmu_registers {
+	u8 pad0[0x08 - 0x00];
+	u32 fccr;	/*0x0008*/
+	u32 pocr;	/*0x000c*/
+	u32 posr;	/*0x0010*/
+	u32 succr;	/*0x0014*/
+	u8 pad1[0x030 - 0x014 - 4];
+	u32 gpcr;	/*0x0030*/
+	u8 pad2[0x200 - 0x030 - 4];
+	u32 wdtpcr;	/*0x0200*/
+	u8 pad3[0x1000 - 0x200 - 4];
+	u32 apcr;	/*0x1000*/
+	u32 apsr;	/*0x1004*/
+	u8 pad4[0x1020 - 0x1004 - 4];
+	u32 aprr;	/*0x1020*/
+	u32 acgr;	/*0x1024*/
+	u32 arsr;	/*0x1028*/
+};
+
+/*
+ * APB1 Clock Reset/Control Registers
+ * Refer Datasheet Appendix A.10
+ */
+struct armd1apb1_registers {
+	u32 uart1;	/*0x000*/
+	u32 uart2;	/*0x004*/
+	u32 gpio;	/*0x008*/
+	u32 pwm1;	/*0x00c*/
+	u32 pwm2;	/*0x010*/
+	u32 pwm3;	/*0x014*/
+	u32 pwm4;	/*0x018*/
+	u8 pad0[0x028 - 0x018 - 4];
+	u32 rtc;	/*0x028*/
+	u32 twsi0;	/*0x02c*/
+	u32 kpc;	/*0x030*/
+	u32 timers;	/*0x034*/
+	u8 pad1[0x03c - 0x034 - 4];
+	u32 aib;	/*0x03c*/
+	u32 sw_jtag;	/*0x040*/
+	u32 timer1;	/*0x044*/
+	u32 onewire;	/*0x048*/
+	u8 pad2[0x050 - 0x048 - 4];
+	u32 asfar;	/*0x050 AIB Secure First Access Reg*/
+	u32 assar;	/*0x054 AIB Secure Second Access Reg*/
+	u8 pad3[0x06c - 0x054 - 4];
+	u32 twsi1;	/*0x06c*/
+	u32 uart3;	/*0x070*/
+	u8 pad4[0x07c - 0x070 - 4];
+	u32 timer2;	/*0x07C*/
+	u8 pad5[0x084 - 0x07c - 4];
+	u32 ac97;	/*0x084*/
+};
+
+/*
  * CPU Interface Registers
  * Refer Datasheet Appendix A.2
  */
diff --git a/arch/arm/include/asm/arch-armada100/gpio.h b/arch/arm/include/asm/arch-armada100/gpio.h
new file mode 100644
index 0000000000..07c44e3035
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada100/gpio.h
@@ -0,0 +1,46 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada100.h>
+#include <mvgpio.h>
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	const unsigned int offset[4] = {0, 4, 8, 0x100};
+	/* gpio register bank offset - refer Appendix A.36 */
+	return (struct gpio_reg *)(ARMD1_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
diff --git a/arch/arm/include/asm/arch-armada610/armada610.h b/arch/arm/include/asm/arch-armada610/armada610.h
new file mode 100644
index 0000000000..e89cf82d4c
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/armada610.h
@@ -0,0 +1,65 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_H
+#define _AMAD6_H
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK		(1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK		(1<<1)  /* Functional Clock Enable */
+#define APBC_RST		(1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Common APMU clock register bit definitions */
+#define APMU_PERIPH_CLK_EN	(1<<4)	/* Peripheral clock enable */
+#define APMU_AXI_CLK_EN		(1<<3)	/* AXI clock enable */
+#define APMU_PERIPH_RESET	(1<<1)	/* Peripheral reset */
+#define APMU_AXI_RESET		(1<<0)	/* AXI BUS reset */
+
+/* Display Control 1 Clock/Rest Control Register */
+#define CLK_DIV_SEL(x)		((x)<<8)
+#define CLK_SEL(x)		((x)<<6)
+#define DIS_CLK_PLL_SEL		(1<<20)
+#define DSI_ESCCLK_EN		(1<<12)
+#define DSI_PHY_SLOW_CLK_EN	(1<<5)
+
+/* PMUM PLL1 Control Register */
+#define PLL1_1P5M_EN		(1<<0)
+
+/* Register Base Addresses */
+#define AMAD6_DRAM_BASE		0xD0000000
+#define AMAD6_TIMER_BASE	0xD4014000
+#define AMAD6_APBC_BASE		0xD4015000
+#define AMAD6_UART3_BASE	0xD4018000
+#define AMAD6_GPIO_BASE		0xD4019000
+#define AMAD6_MFPR_BASE		0xD401E000
+#define AMAD6_MPMU_BASE		0xD4050000
+#define AMAD6_APMU_BASE		0xD4282800
+#define AMAD6_CPU_BASE		0xD4282C00
+#define ARAD6_GPIO_BASE		0xD4019000
+
+/* armada610 has upto 256 gpio control bit */
+#define MV_MAX_GPIO		256
+#endif /* _AMAD6_H */
diff --git a/arch/arm/include/asm/arch-armada610/config.h b/arch/arm/include/asm/arch-armada610/config.h
new file mode 100644
index 0000000000..fc9a3d9ec8
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/config.h
@@ -0,0 +1,127 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_CONFIG_H
+#define _AMAD6_CONFIG_H
+
+#include <asm/arch/armada610.h>
+#undef CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_TCLK		(26000000)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(6500000)	/* Timer Freq. 6.5MHZ */
+#define CONFIG_LOADADDR                0x7fc0        /* Default load place */
+#define CONFIG_SYS_LOAD_ADDR   CONFIG_LOADADDR
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define MV_MFPR_BASE		AMAD6_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	AMAD6_UART3_BASE
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+#define CONFIG_ARMADA610
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV          1
+#define CONFIG_MV_I2C_NUM      6
+#define CONFIG_I2C_MULTI_BUS   1
+#define CONFIG_MV_I2C_REG	{0xd4011000, 0xd4031000, 0xd4032000,\
+	0xd4033000, 0xd4033800, 0xd4034000}
+#define CONFIG_HARD_I2C                1
+#define CONFIG_SYS_I2C_SPEED   0
+#define CONFIG_SYS_I2C_SLAVE   0xfe
+#endif
+
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT         1
+#define CONFIG_MMC              1
+#define CONFIG_GENERIC_MMC      1
+#define CONFIG_SDHCI           1
+#define CONFIG_MMC_SDMA                1
+#define CONFIG_MV_SDHCI                1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_EFI_PARTITION   1
+#define CONFIG_SYS_MMC_NUM     2
+#define CONFIG_SYS_MMC_BASE     {0xD4281000, 0xd4280000}
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT 100
+#endif
+
+#ifdef CONFIG_USB_ETHER
+#define CONFIG_USB_GADGET_MV   1
+#define CONFIG_USB_GADGET_DUALSPEED    1
+#define CONFIG_CMD_NET         1
+#define CONFIG_IPADDR          192.168.1.101
+#define CONFIG_SERVERIP                192.168.1.100
+#define CONFIG_ETHADDR         08:00:3e:26:0a:5b
+#define CONFIG_NET_MULTI       1
+#define CONFIG_USBNET_DEV_ADDR         "00:0a:fa:63:8b:e8"
+#define CONFIG_USBNET_HOST_ADDR        "0a:fa:63:8b:e8:0a"
+#define CONFIG_MV_UDC          1
+#define CONFIG_URB_BUF_SIZE    256
+#define CONFIG_USB_REG_BASE    0xd4208000
+#define CONFIG_USB_PHY_BASE    0xd4207000
+#endif
+
+#ifdef CONFIG_CMD_GPIO
+#define CONFIG_MARVELL_GPIO	1
+#endif
+
+#ifdef CONFIG_CMD_FASTBOOT
+#define CONFIG_USBD_VENDORID		0x18d1
+#define CONFIG_USBD_PRODUCTID		0x4e11
+#define CONFIG_USBD_MANUFACTURER	"Marvell Inc."
+#define CONFIG_USBD_PRODUCT_NAME	"Android 2.1"
+#define CONFIG_SERIAL_NUM		"MRUUUVLs001"
+#define CONFIG_USBD_CONFIGURATION_STR	"fastboot"
+#define CONFIG_SYS_FASTBOOT_ONFLY_SZ	0x40000
+#define USB_LOADADDR			0x100000
+#define CONFIG_FB_RESV			256
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS                      \
+	"autostart=yes\0"                               \
+	"verify=no\0"                                   \
+	"cdc_connect_timeout=60\0"
+
+/*
+ * LCD definition
+ */
+#ifdef CONFIG_PXA168_FB
+#define FB_XRES			1280
+#define FB_YRES			720
+#define CONFIG_CMD_BMP		1
+#define CONFIG_VIDEO		1
+#define CONFIG_CFB_CONSOLE	1
+#define VIDEO_KBD_INIT_FCT	-1
+#define VIDEO_TSTC_FCT		serial_tstc
+#define VIDEO_GETC_FCT		serial_getc
+#define LCD_RST_GPIO		83
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(262144)
+#endif
+
+#endif /* _AMAD6_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada610/cpu.h b/arch/arm/include/asm/arch-armada610/cpu.h
new file mode 100644
index 0000000000..79be75ca39
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/cpu.h
@@ -0,0 +1,184 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_CPU_H
+#define _AMAD6_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct armd6mpmu_registers {
+	u8 pad0[0x0418];
+	u32 pll1;	/*0x0418*/
+	u8 pad1[0x1024 - 0x0418 - 4];
+	u32 acgr;	/*0x1024*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct armd6apbc_registers {
+	u8 pad0[0x004];
+	u32 twsi1;	/*0x004*/
+	u8 pad1[0x024 - 0x04 - 4];
+	u32 timers;	/*0x024*/
+	u8 pad2[0x034 - 0x24 - 4];
+	u32 uart3;	/*0x034*/
+	u32 gpio;	/*0x038*/
+	u8 pad3[0x044 - 0x38 - 4];
+	u32 pwm3;	/*0x044*/
+	u8 pad4[0x064 - 0x44 - 4];
+	u32 aib;	/*0x064*/
+	u8 pad5[0x07c - 0x64 - 4];
+	u32 twsi5;	/*0x07c*/
+	u32 twsi6;	/*0x080*/
+};
+
+/*
+ * Application Subsystem PMU(APMU) Registers
+ * Refer Register Datasheet Appendix A.24
+ */
+struct armd6apmu_registers {
+	u8 pad0[0x034];
+	u32 usb_dyn_gate;	/*0x034*/
+	u8 pad1[0x04c - 0x34 - 4];
+	u32 display1;		/*0x04c*/
+	u8 pad2[0x054 - 0x4c - 4];
+	u32 sd1;		/*0x054*/
+	u8 pad3[0x05c - 0x54 - 4];
+	u32 usb;		/*0x05c*/
+	u8 pad4[0x0dc - 0x5c - 4];
+	u32 gbl_clkctrl;	/*0x0dc*/
+	u8 pad5[0x0e8 - 0xdc - 4];
+	u32 sd2;		/*0x0e8*/
+	u32 sd3;		/*0x0ec*/
+};
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct armd6timer_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+};
+
+struct armd6cpu_registers {
+	u32 chip_id;            /* Chip Id Reg */
+};
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct armd6ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+	u32	pad[3];
+};
+
+struct armd6ddr_registers {
+	u8	pad[0x100];
+	struct armd6ddr_map_registers mmap[2];
+};
+
+/*
+ * Functions
+ */
+u32 armd6_sdram_base(int);
+u32 armd6_sdram_size(int);
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+#define __stringify_1(x)        #x
+#define __stringify(x)          __stringify_1(x)
+
+#define read_cpuid(reg)							\
+	({								\
+		unsigned int __val;					\
+		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
+		    : "=r" (__val)					\
+		    :							\
+		    : "cc");						\
+		__val;							\
+	})
+
+#ifdef CONFIG_ARMADA610
+static unsigned int __cpu_is_armada610(unsigned int id)
+{
+		unsigned int _id = ((id) >> 8) & 0xff;
+		return (_id == 0xb7 || _id == 0xc0  || _id == 0x58);
+}
+#else
+static unsigned int __cpu_is_armada610(unsigned int id)
+{
+		return 0;
+}
+#endif
+int cpu_is_armada610(void);
+int cpu_is_armada610_a0(void);
+int cpu_is_armada610_a1(void);
+int cpu_is_armada610_a2(void);
+int cpu_is_armada610_z0(void);
+int cpu_is_armada610_z1(void);
+/* armada620 special mmc tuning register */
+#define SD_FIFO_PARAM                  0x104
+#define  DIS_PAD_SD_CLK_GATE   (1 << 10)
+#define  CLK_GATE_ON           (1 << 9)
+#define  CLK_GATE_CTL          (1 << 8)
+#define  WTC_DEF               0x1
+#define  WTC(x)                        ((x & 0x3) << 2)
+#define  RTC_DEF               0x1
+#define  RTC(x)                        (x & 0x3)
+
+#define SD_CLOCK_AND_BURST_SIZE_SETUP  0x10a
+#define  SDCLK_DELAY(x)                ((x & 0x1f) << 9)
+#define  SDCLK_SEL             (1 << 8)
+#define  WR_ENDIAN             (1 << 7)
+#define  RD_ENDIAN             (1 << 6)
+#define  DMA_FIFO_128          1
+#define  DMA_SIZE(x)           ((x & 0x3) << 2)
+#define  BURST_64              1
+#define  BURST_SIZE(x)         (x & 0x3)
+#endif /* _AMAD6_CPU_H */
diff --git a/arch/arm/include/asm/arch-armada610/gpio.h b/arch/arm/include/asm/arch-armada610/gpio.h
new file mode 100644
index 0000000000..97a34ce555
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/gpio.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada610.h>
+#include <mvgpio.h>
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	const unsigned int offset[6] = {0, 4, 8, 0x100, 0x104, 0x108};
+	/* gpio register bank offset - refer Appendix A.36 */
+	return (struct gpio_reg *)(AMAD6_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
+
diff --git a/arch/arm/include/asm/arch-armada610/mfp.h b/arch/arm/include/asm/arch-armada610/mfp.h
new file mode 100644
index 0000000000..8898ccdb84
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/mfp.h
@@ -0,0 +1,83 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __AMAD6_MFP_H
+#define __AMAD6_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART3 */
+#define UART3_RXD		(MFP_REG(0x120) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define UART3_TXD		(MFP_REG(0x124) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+/* TWSI5 */
+#define TWSI5_SCL              (MFP_REG(0x1D4) | MFP_AF4 | MFP_DRIVE_SLOW)
+#define TWSI5_SDA              (MFP_REG(0x1D8) | MFP_AF4 | MFP_DRIVE_SLOW)
+
+/* TWSI6 */
+#define TWSI6_SCL              (MFP_REG(0x1CC) | MFP_AF2 | MFP_DRIVE_SLOW)
+#define TWSI6_SDA              (MFP_REG(0x1D0) | MFP_AF2 | MFP_DRIVE_SLOW)
+
+/* MMC1 */
+#define MMC1_DATA3             (MFP_REG(0x28) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA2             (MFP_REG(0x2c) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA1             (MFP_REG(0x30) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA0             (MFP_REG(0x34) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CLK               (MFP_REG(0x48) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CMD               (MFP_REG(0x3c) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CD                (MFP_REG(0x4c) | MFP_AF1 | MFP_PULL_HIGH)
+#define MMC1_WP                (MFP_REG(0x50) | MFP_AF1 | MFP_PULL_HIGH)
+
+/* MMC3 */
+#define MMC3_DATA7             (MFP_REG(0x1ec) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA6             (MFP_REG(0x20c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA5             (MFP_REG(0x1e8) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA4             (MFP_REG(0x208) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA3             (MFP_REG(0x1e4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA2             (MFP_REG(0x204) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA1             (MFP_REG(0x1e0) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA0             (MFP_REG(0x200) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CLK               (MFP_REG(0x240) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CMD               (MFP_REG(0x244) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* LCD */
+#define BACK_LIGHT_PWM3		(MFP_REG(0x128) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+
+#define VOLUME_UP		(MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+#define VOLUME_DOWN		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_MEDIUM | MFP_PULL_HIGH)
+
+/* VERS */
+#define PLAT_VERS_PIN0		(MFP_REG(0x010) | MFP_AF0 | MFP_PULL_HIGH)
+#define PLAT_VERS_PIN1		(MFP_REG(0x014) | MFP_AF0 | MFP_PULL_HIGH)
+#define PLAT_VERS_PIN2		(MFP_REG(0x018) | MFP_AF0 | MFP_PULL_HIGH)
+#define PLAT_VERS_PIN3		(MFP_REG(0x01c) | MFP_AF0 | MFP_PULL_HIGH)
+
+/* More macros can be defined here... */
+
+#define MFP_PIN_MAX	117
+#endif /* __AMAD6_MFP_H */
diff --git a/arch/arm/include/asm/arch-armada610/usb.h b/arch/arm/include/asm/arch-armada610/usb.h
new file mode 100644
index 0000000000..773248435e
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada610/usb.h
@@ -0,0 +1,126 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_USB_H
+#define _AMAD6_USB_H
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+#ifdef CONFIG_MACH_BROWNSTONE
+struct usb_file {
+	u32 pad0;		/* 0x00 */
+	u32 ctrl_reg;		/* 0x04 */
+#define POWER_UP	(1)
+#define PLL_POWER_UP	(1 << 1)
+#define PU_REF		(1 << 20)
+#define USB_CTL_29_28(x)	((x) << 28)
+#define USB_CTL_29_28_MASK	0x30000000
+	u32 pll_reg;		/* 0x08 */
+#define REFDIV_MASK	0xf
+#define REFDIV(x)	((x) - 2)
+#define FBDIV_MASK	0xff0
+#define FBDIV(x)	(((x) - 2) << 4)
+#define ICP(x)		(((x)/5 - 1) << 12)
+#define ICP_MASK	0x7000
+#define PLL_READY	(1 << 23)
+#define PLLVDD12_MASK	0x6000000
+#define PLLVDD12(x)	((x) << 25)
+#define PLLVDD18_MASK	0x18000000
+#define PLLVDD18(x)	((x) << 27)
+#define PLLCALLI12_MASK	0x60000000
+#define PLLCALLI12(x)	((x) << 29)
+#define VCOCAL_START	(1 << 21)
+	u32 tx_reg;		/* 0x0c */
+#define IMPCAL_VTH_MASK	0x1c000
+#define IMPCAL_VTH(x)	((x) << 14)
+#define	CK60_PHSEL_Mask	0x1e0000
+#define	CK60_PHSEL(x)	((x) << 17)
+#define TXVDD12_MASK	0xc00000
+#define TXVDD12(x)	((x) << 22)
+#define TXDATA_BLOCK_EN (1 << 21)
+#define REG_RCAL_START	(1 << 12)
+	u32 rx_reg;		/* 0x10 */
+	u32 ivref_reg;		/* 0x14 */
+	u32 test_group_0;	/* 0x18 */
+	u32 test_group_1;	/* 0x1c */
+	u32 test_group_2;	/* 0x20 */
+	u32 id_grp;		/* 0x24 */
+	u32 usb_int;		/* 0x28 */
+	u32 dbg_ctl;		/* 0x2c */
+	u32 ctl1;		/* 0x30 */
+	u32 test_group_3;	/* 0x34 */
+	u32 test_group_4;	/* 0x38 */
+	u32 test_group_5;	/* 0x3c */
+};
+#else
+struct usb_file {
+	u32 usb_id;		/* 0x00 */
+#define REFDIV_MASK	0x0f00
+#define FB_DIV_MASK	0x00ff
+#define VDD18(x)	((x & 0x3) << 14)
+#define VDD12(x)	((x & 0x3) << 12)
+#define REFDIV(x)	((x << 8) & REFDIV_MASK)
+#define FB_DIV(x)	(x & FB_DIV_MASK)
+	u32 pll_reg0;		/* 0x04 */
+#define PLL_READY	0x8000
+#define PLL_ICP_MASK	0x0700
+#define PLL_KVCO_MASK	0x0070
+#define PLL_CALI12_MASK	0x0003
+#define UTMI_PLL_PU	0x2000
+#define PLL_ICP(x)	((x << 8) & PLL_ICP_MASK)
+#define PLL_KVCO(x)	((x << 4) & PLL_KVCO_MASK)
+#define VCOCAL_START	0x0004
+#define PLL_CALI12(x)	(x & PLL_CALI12_MASK)
+	u32 pll_reg1;		/* 0x08 */
+	u32 pad0;
+#define RCAL_START	0x2000
+#define IMPCAL_VTH_MASK	0x0700
+#define IMPCAL_VTH(x)	((x << 8) & IMPCAL_VTH_MASK)
+	u32 tx_reg0;		/* 0x10 */
+#define CK60_PHSEL_MASK	0x000f
+#define AMP_MASK	0x0070
+#define TX_VDD12_MASK	0x0300
+#define CK60_PHSEL(x)	(x & CK60_PHSEL_MASK)
+#define AMP(x)		((x << 4) & AMP_MASK)
+#define TX_VDD12(x)	((x << 8) & TX_VDD12_MASK)
+	u32 tx_reg1;		/* 0x14 */
+#define DRV_SLEWRATE(x)	((x & 0x3) << 10)
+	u32 tx_reg2;		/* 0x18 */
+	u32 pad1;
+#define SQ_LENGTH_MASK	0x0c00
+#define SQ_THRESH_MASK	0x00f0
+#define SQ_LENGTH(x)	((x << 10) & SQ_LENGTH_MASK)
+#define SQ_THRESH(x)	((x << 4) & SQ_THRESH_MASK)
+	u32 rx_reg0;		/* 0x20 */
+	u32 pad2[4];
+#define ANA_PU		0x4000
+	u32 ana_reg1;		/* 0x34 */
+	u32 pad3[9];
+#define PU_OTG		0x0008
+	u32 otg_reg0;		/* 0x5c */
+};
+#endif
+#endif /* _AMAD6_CPU_H */
diff --git a/arch/arm/include/asm/arch-armada620/armada620.h b/arch/arm/include/asm/arch-armada620/armada620.h
new file mode 100644
index 0000000000..f6f8c16e13
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/armada620.h
@@ -0,0 +1,71 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_H
+#define _AMAD6_H
+
+/* Common APB clock register bit definitions */
+#define APBC_APBCLK		(1<<0)  /* APB Bus Clock Enable */
+#define APBC_FNCLK		(1<<1)  /* Functional Clock Enable */
+#define APBC_RST		(1<<2)  /* Reset Generation */
+/* Functional Clock Selection Mask */
+#define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
+
+/* Common APMU clock register bit definitions */
+#define APMU_PERIPH_CLK_EN	(1<<4)	/* Peripheral clock enable */
+#define APMU_AXI_CLK_EN		(1<<3)	/* AXI clock enable */
+#define APMU_PERIPH_RESET	(1<<1)	/* Peripheral reset */
+#define APMU_AXI_RESET		(1<<0)	/* AXI BUS reset */
+#define USB_26M_SEL		(0xd << 8)	/* select as 26m ref clock*/
+
+/* Fast Ethernet Clock register bit definitions*/
+#define FE_CLK_SRC_SEL		(1<<6) /* Fast Ethernet clock option */
+#define FE_CLKEN		(1<<4) /* Fast Ethernet clock enable */
+#define FE_ACLKEN		(1<<3) /* Fast Ethernet AXI clock enable */
+#define FE_SW_RSTN		(1<<1) /* Fast Ethernet software reset */
+#define FE_AXI_SW_RSTN		(1<<0) /* Fast Ethernet AXI interface software reset */
+
+/* Display Control 1 Clock/Rest Control Register */
+#define CLK_DIV_SEL(x)		((x)<<8)
+#define CLK_SEL(x)		((x)<<6)
+#define DIS_CLK_PLL_SEL		(1<<20)
+#define DSI_ESCCLK_EN		(1<<12)
+#define DSI_PHY_SLOW_CLK_EN	(1<<5)
+
+/* Register Base Addresses */
+#define AMAD6_DRAM_BASE		0xD0000000
+#define AMAD6_FEC_BASE		0xD427F000
+#define AMAD6_TIMER_BASE	0xD4014000
+#define AMAD6_APBC_BASE		0xD4015000
+#define AMAD6_UART3_BASE	0xD4018000
+#define AMAD6_GPIO_BASE		0xD4019000
+#define AMAD6_MFPR_BASE		0xD401E000
+#define AMAD6_MPMU_BASE		0xD4050000
+#define AMAD6_APMU_BASE		0xD4282800
+#define AMAD6_CPU_BASE		0xD4282C00
+#define ARAD6_GPIO_BASE		0xD4019000
+
+/* pxa2128 has upto 169 gpio control bit */
+#define MV_MAX_GPIO            169
+#endif /* _AMAD6_H */
diff --git a/arch/arm/include/asm/arch-armada620/config.h b/arch/arm/include/asm/arch-armada620/config.h
new file mode 100644
index 0000000000..dfb071b5a7
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/config.h
@@ -0,0 +1,161 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_CONFIG_H
+#define _AMAD6_CONFIG_H
+
+#include <asm/arch/armada620.h>
+#undef CONFIG_SYS_LOAD_ADDR
+
+#define CONFIG_SYS_TCLK		(26000000)	/* NS16550 clk config */
+#define CONFIG_SYS_HZ_CLOCK	(6500000)	/* Timer Freq. 6.5MHZ */
+#ifdef CONFIG_TZ_HYPERVISOR
+#define CONFIG_LOADADDR		0x207fc0	/* Default load place */
+#else
+#define CONFIG_LOADADDR		0x7fc0		/* Default load place */
+#endif
+#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
+#define CONFIG_MARVELL_MFP			/* Enable mvmfp driver */
+#define CONFIG_SYS_TIMERBASE	AMAD6_TIMER_BASE
+#define MV_MFPR_BASE		AMAD6_MFPR_BASE
+#define MV_UART_CONSOLE_BASE	AMAD6_UART3_BASE
+/* The max cs num in one controller*/
+#define CONFIG_DRAM_CSNUM_MAX	2
+#define CONFIG_SYS_NS16550_IER	(1 << 6)	/* Bit 6 in UART_IER register
+						represents UART Unit Enable */
+
+#ifndef CONFIG_FIX_RAMSIZE
+#define CONFIG_FIX_RAMSIZE	(384 * 1024 * 1024)
+#endif
+/*
+ * I2C definition
+ */
+#ifdef CONFIG_CMD_I2C
+#define CONFIG_I2C_MV		1
+//#define CONFIG_MV_I2C_NUM	4
+#define CONFIG_MV_I2C_NUM	6
+#define CONFIG_I2C_MULTI_BUS	1
+//#define CONFIG_MV_I2C_REG	{0xd4011000, 0xd4032000, 0xd4033800, 0xd4034000}
+#define CONFIG_MV_I2C_REG	{0xd4011000, 0xd4031000, 0xd4032000,\
+	0xd4033000, 0xd4033800, 0xd4034000}
+//i2c 1->2
+//    2->4
+//    3->5
+
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED	0
+#define CONFIG_SYS_I2C_SLAVE	0xfe
+#endif
+
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT		1
+#define CONFIG_MMC              1
+#define CONFIG_GENERIC_MMC      1
+#define CONFIG_SDHCI		1
+#define CONFIG_MMC_SDMA		1
+#define CONFIG_MV_SDHCI		1
+#define CONFIG_DOS_PARTITION    1
+#define CONFIG_EFI_PARTITION	1
+#define CONFIG_SYS_MMC_NUM	2
+#define CONFIG_SYS_MMC_BASE     {0xd4281000, 0xD4280000}
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT   100
+#endif
+
+#ifdef CONFIG_USB_ETHER
+#define CONFIG_USB_GADGET_MV	1
+#define CONFIG_USB_GADGET_DUALSPEED	1
+#define CONFIG_CMD_NET		1
+#define CONFIG_IPADDR		192.168.1.101
+#define CONFIG_SERVERIP		192.168.1.100
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NET_MULTI	1
+#define CONFIG_USBNET_DEV_ADDR 	"00:0a:fa:63:8b:e8"
+#define CONFIG_USBNET_HOST_ADDR	"0a:fa:63:8b:e8:0a"
+#define CONFIG_MV_UDC		1
+#define CONFIG_URB_BUF_SIZE	256
+#define CONFIG_USB_REG_BASE	0xd4208000
+#define CONFIG_USB_PHY_BASE	0xd4207000
+#endif
+
+#ifdef CONFIG_ARMADA100_FEC
+#ifdef CONFIG_USB_ETHER
+#define CONFIG_CMD_PING
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#else
+#define CONFIG_CMD_NET		1
+#define CONFIG_IPADDR           192.168.1.101
+#define CONFIG_SERVERIP         192.168.1.100
+#define CONFIG_ETHADDR          08:00:3e:26:0a:5b
+#define CONFIG_NET_MULTI        1
+#define CONFIG_CMD_PING
+#define CONFIG_MII
+#define CONFIG_CMD_MII
+#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
+#endif
+#endif
+
+#ifdef CONFIG_CMD_GPIO
+#define CONFIG_MARVELL_GPIO    1
+#endif
+
+#ifdef CONFIG_CMD_FASTBOOT
+#define CONFIG_USBD_VENDORID		0x18d1
+#define CONFIG_USBD_PRODUCTID		0x4e11
+#define CONFIG_USBD_MANUFACTURER	"Marvell Inc."
+#define CONFIG_USBD_PRODUCT_NAME	"Android 2.1"
+#define CONFIG_SERIAL_NUM		"MRUUUVLs001"
+#define CONFIG_USBD_CONFIGURATION_STR	"fastboot"
+#define CONFIG_SYS_FASTBOOT_ONFLY_SZ	0x40000
+#define USB_LOADADDR			0x100000
+#define CONFIG_FB_RESV			256
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"autostart=yes\0"				\
+	"verify=yes\0"					\
+	"cdc_connect_timeout=60\0"
+
+/*
+ * LCD definition
+ */
+#ifdef CONFIG_PXA168_FB
+#define FB_XRES			1024
+#define FB_YRES			768
+#define CONFIG_CMD_BMP		1
+#define CONFIG_VIDEO		1
+#define CONFIG_CFB_CONSOLE	1
+#define VIDEO_KBD_INIT_FCT	-1
+#define VIDEO_TSTC_FCT		serial_tstc
+#define VIDEO_GETC_FCT		serial_getc
+#define LCD_RST_GPIO		128
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE	(262144)
+#endif
+
+#endif /* _AMAD6_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-armada620/cpu.h b/arch/arm/include/asm/arch-armada620/cpu.h
new file mode 100644
index 0000000000..3273291a6d
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/cpu.h
@@ -0,0 +1,207 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_CPU_H
+#define _AMAD6_CPU_H
+
+#include <asm/io.h>
+#include <asm/system.h>
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct armd6mpmu_registers {
+	u8 pad0[0x38];
+	u32 sccr;	/*0x0038*/
+	u8 pad1[0x50 - 0x38 - 4];
+#define PLL3_REFDIV(x)		(((x) & 0x1f) << 19)
+#define FBDIV(x)		(((x) & 0x1ff) << 10)
+#define PLL3_ACTV_CNTRL		(0x1 << 9)
+#define PLL3_SW_EN		(0x1 << 8)
+	u32 pll3_cr;	/*0x0050*/
+	u8 pad2[0x58 - 0x50 - 4];
+#define PLL_RST			(0x1 << 29)
+#define VCODIV_SEL_SE(x)	(((x) & 0x7) << 25)
+#define ICP(x)			(((x) & 0x7) << 22)
+#define KVCO(x)			(((x) & 0x7) << 19)
+#define CTUNE(x)		(((x) & 0x3) << 15)
+#define VCO_VRNG(x)		(((x) & 0x7) << 8)
+#define VREG_IVREF(x)		(((x) & 0x3) << 6)
+#define VDDM(x)			(((x) & 0x3) << 4)
+#define VDDL(x)			(x & 0xf)
+	u32 pll3_ctl1;	/*0x0058*/
+	u8 pad3[0x60 - 0x58 - 4];
+#define SEL_VCO_CLK_SE		0x1
+	u32 pll3_ctl2;	/*0x0060*/
+	u8 pad4[0x1024 - 0x60 - 4];
+	u32 acgr;	/*0x1024*/
+};
+
+/*
+ * APB Clock Reset/Control Registers
+ * Refer Register Datasheet 6.14
+ */
+struct armd6apbc_registers {
+ 	u8 pad0[0x004];
+ 	u32 twsi1;	/*0x004*/
+	u8 pad1[4];
+	u32 twsi3;	/*0x00c*/
+	u8 pad2[0x024 - 0x0c - 4];
+ 	u32 timers;	/*0x024*/
+	u8 pad3[0x034 - 0x24 - 4];
+ 	u32 uart3;	/*0x034*/
+ 	u32 gpio;	/*0x038*/
+	u8 pad4[0x044 - 0x38 - 4];
+ 	u32 pwm3;	/*0x044*/
+	u8 pad5[0x064 - 0x44 - 4];
+ 	u32 aib;	/*0x064*/
+	u8 pad6[0x07c - 0x64 - 4];
+ 	u32 twsi5;	/*0x07c*/
+ 	u32 twsi6;	/*0x080*/
+};
+
+/*
+ * Application Subsystem PMU(APMU) Registers
+ * Refer Register Datasheet Appendix A.24
+ */
+struct armd6apmu_registers {
+	u8 pad0[0x034];
+	u32 usb_dyn_gate;	/*0x034*/
+	u8 pad1[0x04c - 0x34 - 4];
+	u32 display1;		/*0x04c*/
+	u8 pad2[0x054 - 0x4c - 4];
+	u32 sd1;		/*0x054*/
+	u8 pad3[0x05c - 0x54 - 4];
+	u32 usb;		/*0x05c*/
+	u8 pad4[0x060 - 0x5c - 4];
+	u32 nf;			/*0x060*/
+	u8 pad5[0x08c - 0x60 - 4];
+	u32 sram_pd;		/*0x08c*/
+	u8 pad6[0x0d4 - 0x8c - 4];
+	u32 smc;		/*0x0d4*/
+	u32 mspro;
+	u32 gbl_clkctrl;	/*0x0dc*/
+	u8 pad7[0x0e8 - 0xdc - 4];
+	u32 sd3;		/*0x0e8*/
+	u8 pad8[0x100 - 0xe8 - 4];
+#define USB_PHY_REFCLK_SEL(x)	((x & 0xf) << 8)  /* select as 26m ref clock*/
+#define USB_PHY_REF_MASK	(0xf << 8)
+#define USB_PHY_26M		USB_PHY_REFCLK_SEL(0xd)
+	u32 fsic3;		/*0x100*/
+	u8 pad9[0x210 - 0x100 - 4];
+	u32 fastenet;		/*0x210*/
+	u8 pad10[0x244 - 0x210 - 4];
+	u32 genctrl;		/*0x244*/
+};
+
+/*
+ * Timer registers
+ * Refer 6.2.9 in Datasheet
+ */
+struct armd6timer_registers {
+	u32 clk_ctrl;	/* Timer clk control reg */
+	u32 match[9];	/* Timer match registers */
+	u32 count[3];	/* Timer count registers */
+	u32 status[3];
+	u32 ie[3];
+	u32 preload[3];	/* Timer preload value */
+	u32 preload_ctrl[3];
+	u32 wdt_match_en;
+	u32 wdt_match_r;
+	u32 wdt_val;
+	u32 wdt_sts;
+	u32 icr[3];
+	u32 wdt_icr;
+	u32 cer;	/* Timer count enable reg */
+	u32 cmr;
+	u32 ilr[3];
+	u32 wcr;
+	u32 wfar;
+	u32 wsar;
+	u32 cvwr[3];
+};
+
+struct armd6cpu_registers {
+	u32 chip_id;            /* Chip Id Reg */
+	u8 pad0[0x7c - 4];
+	u32 mp1_pd;		/*0x7c*/
+	u32 mp2_pd;		/*0x80*/
+	u32 mm_pd;		/*0x84*/
+};
+
+/*
+ * DDR Memory Control Registers
+ * Refer Datasheet 4.4
+ */
+struct armd6ddr_map_registers {
+	u32	cs;	/* Memory Address Map Register -CS */
+};
+
+struct armd6ddr_registers {
+	u8	pad[0x10];
+	struct armd6ddr_map_registers mmap[4];
+};
+
+/*
+ * Functions
+ */
+u32 armd6_sdram_base(int, u32);
+u32 armd6_sdram_size(int, u32);
+u32 dram_interleave_size(void);
+
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
+int cpu_is_ax(void);
+int cpu_is_bx(void);
+
+/* armada620 special mmc tuning register */
+#define SD_FIFO_PARAM			0x104
+#define  DIS_PAD_SD_CLK_GATE	(1 << 10)
+#define  CLK_GATE_ON		(1 << 9)
+#define  CLK_GATE_CTL		(1 << 8)
+#define  WTC_DEF		0x1
+#define  WTC(x)			((x & 0x3) << 2)
+#define  RTC_DEF		0x1
+#define  RTC(x)			(x & 0x3)
+
+#define SD_CLOCK_AND_BURST_SIZE_SETUP	0x10a
+#define  SDCLK_DELAY(x)		((x & 0x1f) << 9)
+#define  SDCLK_SEL		(1 << 8)
+#define  WR_ENDIAN		(1 << 7)
+#define  RD_ENDIAN		(1 << 6)
+#define  DMA_FIFO_128		1
+#define  DMA_SIZE(x)		((x & 0x3) << 2)
+#define  BURST_64		1
+#define  BURST_SIZE(x)		(x & 0x3)
+
+#define RX_CFG_REG              0x114
+#define TUNING_DLY_INC(x)       ((x & 0x1ff) << 17)
+#define SDCLK_DELAY(x)          ((x & 0x1ff) << 8)
+#define SDCLK_SEL0(x)           ((x & 0x3) << 0)
+#define SDCLK_SEL1(x)           ((x & 0x3) << 2)
+
+#define TX_CFG_REG              0x118
+#define TX_HOLD_DELAY0(x)       ((x & 0x1ff) << 0)
+#define TX_HOLD_DELAY1(x)       ((x & 0x1ff) << 16)
+#endif /* _AMAD6_CPU_H */
diff --git a/arch/arm/include/asm/arch-armada620/gpio.h b/arch/arm/include/asm/arch-armada620/gpio.h
new file mode 100644
index 0000000000..d8257194d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/gpio.h
@@ -0,0 +1,44 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _ASM_ARCH_GPIO_H
+#define _ASM_ARCH_GPIO_H
+
+#include <asm/types.h>
+#include <asm/arch/armada620.h>
+#include <mvgpio.h>
+
+#define GPIO_TO_REG(gp)		(gp >> 5)
+#define GPIO_TO_BIT(gp)		(1 << (gp & 0x1F))
+#define GPIO_VAL(gp, val)	((val >> (gp & 0x1F)) & 0x01)
+
+static inline void *get_gpio_base(int bank)
+{
+	const unsigned int offset[6] = {0, 4, 8, 0x100, 0x104, 0x108};
+	/* gpio register bank offset - refer Appendix A.36 */
+	return (struct gpio_reg *)(AMAD6_GPIO_BASE + offset[bank]);
+}
+
+#endif /* _ASM_ARCH_GPIO_H */
+
diff --git a/arch/arm/include/asm/arch-armada620/mfp.h b/arch/arm/include/asm/arch-armada620/mfp.h
new file mode 100644
index 0000000000..91e772395f
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/mfp.h
@@ -0,0 +1,131 @@
+/*
+ * Based on arch/arm/include/asm/arch-armada100/mfp.h
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __AMAD6_MFP_H
+#define __AMAD6_MFP_H
+
+/*
+ * Frequently used MFP Configuration macros for all PANTHEON family of SoCs
+ *
+ * offset, pull,pF, drv,dF, edge,eF ,afn,aF
+ */
+/* UART3 */
+#define UART3_RXD		(MFP_REG(0x120) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define UART3_TXD		(MFP_REG(0x124) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+/* TWSI1 */
+#define TWSI1_SCL		(MFP_REG(0x140) | MFP_AF0 | MFP_DRIVE_SLOW)
+#define TWSI1_SDA		(MFP_REG(0x144) | MFP_AF0 | MFP_DRIVE_SLOW)
+
+/* TWSI3 */
+#define TWSI3_SCL		(MFP_REG(0x2B0) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define TWSI3_SDA		(MFP_REG(0x2B4) | MFP_AF1 | MFP_DRIVE_SLOW)
+
+
+/* TWSI53 */
+#define TWSI3_SCL		(MFP_REG(0x2B0) | MFP_AF1 | MFP_DRIVE_SLOW)
+#define TWSI3_SDA		(MFP_REG(0x2B4) | MFP_AF1 | MFP_DRIVE_SLOW)
+
+/* TWSI5 */
+#define TWSI5_SCL		(MFP_REG(0x1D4) | MFP_AF4 | MFP_DRIVE_SLOW)
+#define TWSI5_SDA		(MFP_REG(0x1D8) | MFP_AF4 | MFP_DRIVE_SLOW)
+
+/* TWSI6 */
+#define TWSI6_SCL		(MFP_REG(0x1CC) | MFP_AF2 | MFP_DRIVE_SLOW)
+#define TWSI6_SDA		(MFP_REG(0x1D0) | MFP_AF2 | MFP_DRIVE_SLOW)
+
+/* MMC1 */
+#define MMC1_DATA3		(MFP_REG(0x28) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA2		(MFP_REG(0x2c) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA1		(MFP_REG(0x30) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_DATA0		(MFP_REG(0x34) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CLK		(MFP_REG(0x38) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CMD		(MFP_REG(0x3c) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define MMC1_CD			(MFP_REG(0x4c) | MFP_AF1 | MFP_PULL_HIGH)
+#define MMC1_WP			(MFP_REG(0x50) | MFP_AF1 | MFP_PULL_HIGH)
+#define MMC1_GPIO13		(MFP_REG(0x80) | MFP_AF0 | MFP_PULL_LOW)
+#define MMC1_GPIO138		(MFP_REG(0x44) | MFP_AF0 | MFP_PULL_LOW)
+/* MMC3 */
+#define MMC3_DATA7		(MFP_REG(0x21c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA6		(MFP_REG(0x218) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA5		(MFP_REG(0x210) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA4		(MFP_REG(0x208) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA3		(MFP_REG(0x200) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA2		(MFP_REG(0x214) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA1		(MFP_REG(0x20c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA0		(MFP_REG(0x204) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CLK		(MFP_REG(0x228) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CMD		(MFP_REG(0x22c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+#define MMC3_DATA7_NDIO15	(MFP_REG(0x21c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA6_NDIO14	(MFP_REG(0x218) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA5_NDIO12	(MFP_REG(0x210) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA4_NDIO10	(MFP_REG(0x208) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA3_NDIO8	(MFP_REG(0x200) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA2_NDIO13	(MFP_REG(0x214) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA1_NDIO11	(MFP_REG(0x20c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_DATA0_NDIO9	(MFP_REG(0x204) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CLK_SMNCS1		(MFP_REG(0x22c) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+#define MMC3_CMD_SMNCS0		(MFP_REG(0x228) | MFP_AF2 | MFP_DRIVE_MEDIUM)
+
+/* Fast Ethernet */
+#define FE_LED0_N               (MFP_REG(0x020) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define FE_LED1_N               (MFP_REG(0x024) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+#define FE_LED2_N               (MFP_REG(0x048) | MFP_AF1 | MFP_DRIVE_MEDIUM)
+
+/* LCD */
+#define LCD_RESET		(MFP_REG(0x01C) | MFP_AF0 | MFP_DRIVE_FAST)
+#define BACK_LIGHT_PWM3    (MFP_REG(0x128) | MFP_AF5 | MFP_DRIVE_MEDIUM)
+#define BL_POWER_EN		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
+#define GPIO152_VLCD_3V3		(MFP_REG(0x248) | MFP_AF1 | MFP_DRIVE_FAST | MFP_PULL_LOW)
+
+/* HDMI 5v Power */
+#define GPIO_160                (MFP_REG(0x250) | MFP_AF1 | MFP_PULL_HIGH)
+
+/* Backlight  enable*/
+#define GPIO_17                 (MFP_REG(0x98) | MFP_AF0 | MFP_PULL_HIGH)
+
+/* LVDS mode detection*/
+#define GPIO_19                 (MFP_REG(0xA0) | MFP_AF0 | MFP_PULL_HIGH)
+
+/* MENU Key*/
+#define GPIO_147		(MFP_REG(0x230) | MFP_AF1 | MFP_PULL_HIGH) 
+
+/*PWM3*/
+#define GPIO53_PWM3             (MFP_REG(0x128) | MFP_AF5 | MFP_DRIVE_MEDIUM) //MFP_CFG_X(GPIO53, AF5, SLOW, PULL_LOW)
+#define GPIO53_GPIO             (MFP_REG(0x128) | MFP_AF0 | MFP_PULL_HIGH) 
+
+/*MODEM power control pins, William Liu*/
+#define GPIO93_GPIO (MFP_REG(0x1bc) | MFP_AF0 | MFP_PULL_NONE)
+#define GPIO94_GPIO (MFP_REG(0x1c0) | MFP_AF0 | MFP_PULL_HIGH)
+#define GPIO95_GPIO (MFP_REG(0x1c4) | MFP_AF0 | MFP_PULL_HIGH)
+#define GPIO129_GPIO (MFP_REG(0x020) | MFP_AF0 | MFP_PULL_HIGH)
+
+/* More macros can be defined here... */
+
+#define MFP_GPIO150		(MFP_REG(0x23C) | MFP_AF1 | MFP_PULL_LOW)
+
+#define MFP_PIN_MAX	117
+#endif /* __AMAD6_MFP_H */
diff --git a/arch/arm/include/asm/arch-armada620/usb.h b/arch/arm/include/asm/arch-armada620/usb.h
new file mode 100644
index 0000000000..ba6611530a
--- /dev/null
+++ b/arch/arm/include/asm/arch-armada620/usb.h
@@ -0,0 +1,83 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _AMAD6_USB_H
+#define _AMAD6_USB_H
+
+/*
+ * Main Power Management (MPMU) Registers
+ * Refer Register Datasheet 9.1
+ */
+struct usb_file {
+	u32 usb_id;		/* 0x00 */
+#define REFDIV_MASK	0x0f00
+#define FB_DIV_MASK	0x00ff
+#define REFDIV_MASK_B0	0x3E00
+#define FB_DIV_MASK_B0	0x01ff
+#define VDD18(x)	((x & 0x3) << 14)
+#define VDD12(x)	((x & 0x3) << 12)
+#define REFDIV(x)	((x << 8) & REFDIV_MASK)
+#define FB_DIV(x)	(x & FB_DIV_MASK)
+#define REFDIV_B0(x)	((x << 9) & REFDIV_MASK_B0)
+#define FB_DIV_B0(x)	(x & FB_DIV_MASK_B0)
+	u32 pll_reg0;		/* 0x04 */
+#define PLL_READY	0x8000
+#define PLL_ICP_MASK	0x0700
+#define PLL_KVCO_MASK	0x0070
+#define PLL_CALI12_MASK	0x0003
+#define UTMI_PLL_PU	0x2000
+#define PLL_ICP(x)	((x << 8) & PLL_ICP_MASK)
+#define PLL_KVCO(x)	((x << 4) & PLL_KVCO_MASK)
+#define VCOCAL_START	0x0004
+#define PLL_CALI12(x)	(x & PLL_CALI12_MASK)
+	u32 pll_reg1;		/* 0x08 */
+	u32 pad0;
+#define RCAL_START	0x2000
+#define IMPCAL_VTH_MASK	0x0700
+#define IMPCAL_VTH(x)	((x << 8) & IMPCAL_VTH_MASK)
+	u32 tx_reg0;		/* 0x10 */
+#define CK60_PHSEL_MASK	0x000f
+#define AMP_MASK	0x0070
+#define TX_VDD12_MASK	0x0300
+#define CK60_PHSEL(x)	(x & CK60_PHSEL_MASK)
+#define AMP(x)		((x << 4) & AMP_MASK)
+#define TX_VDD12(x)	((x << 8) & TX_VDD12_MASK)
+	u32 tx_reg1;		/* 0x14 */
+#define DRV_SLEWRATE(x)	((x & 0x3) << 10)
+	u32 tx_reg2;		/* 0x18 */
+	u32 pad1;
+#define SQ_LENGTH_MASK	0x0c00
+#define SQ_THRESH_MASK	0x00f0
+#define SQ_LENGTH(x)	((x << 10) & SQ_LENGTH_MASK)
+#define SQ_THRESH(x)	((x << 4) & SQ_THRESH_MASK)
+	u32 rx_reg0;		/* 0x20 */
+	u32 pad2[4];
+#define ANA_PU		0x4000
+	u32 ana_reg1;		/* 0x34 */
+	u32 pad3[9];
+#define PU_OTG		0x0008
+	u32 otg_reg0;		/* 0x5c */
+};
+
+#endif /* _AMAD6_CPU_H */
diff --git a/arch/arm/include/asm/arch-kirkwood/config.h b/arch/arm/include/asm/arch-kirkwood/config.h
index b7dae1e2dc..ab7201b0ef 100644
--- a/arch/arm/include/asm/arch-kirkwood/config.h
+++ b/arch/arm/include/asm/arch-kirkwood/config.h
@@ -39,6 +39,7 @@
 #error "SOC Name not defined"
 #endif /* CONFIG_KW88F6281 */
 
+#include <asm/arch/kirkwood.h>
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
 
 #define CONFIG_MD5	/* get_random_hex on krikwood needs MD5 support */
diff --git a/arch/arm/include/asm/arch-kirkwood/kirkwood.h b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
index 3c843a0baa..0035ed50a2 100644
--- a/arch/arm/include/asm/arch-kirkwood/kirkwood.h
+++ b/arch/arm/include/asm/arch-kirkwood/kirkwood.h
@@ -27,13 +27,7 @@
 #ifndef _ASM_ARCH_KIRKWOOD_H
 #define _ASM_ARCH_KIRKWOOD_H
 
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif /* __ASSEMBLY__ */
-
 #if defined (CONFIG_FEROCEON_88FR131) || defined (CONFIG_SHEEVA_88SV131)
-#include <asm/arch/cpu.h>
 
 /* SOC specific definations */
 #define INTREG_BASE			0xd0000000
diff --git a/arch/arm/include/asm/arch-pantheon/config.h b/arch/arm/include/asm/arch-pantheon/config.h
index 5658592f83..224dfc7f9b 100644
--- a/arch/arm/include/asm/arch-pantheon/config.h
+++ b/arch/arm/include/asm/arch-pantheon/config.h
@@ -25,6 +25,8 @@
 #ifndef _PANTHEON_CONFIG_H
 #define _PANTHEON_CONFIG_H
 
+#include <asm/arch/pantheon.h>
+
 #define CONFIG_ARM926EJS	1	/* Basic Architecture */
 
 #define CONFIG_SYS_TCLK		(14745600)	/* NS16550 clk config */
@@ -45,4 +47,58 @@
 #define CONFIG_SYS_I2C_SLAVE		0xfe
 #endif
 
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_CMD_FAT			1
+#define CONFIG_MMC			1
+#define CONFIG_GENERIC_MMC		1
+#define CONFIG_SDHCI			1
+#define CONFIG_MMC_SDHCI_IO_ACCESSORS	1
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT	0x1000
+#define CONFIG_MMC_SDMA			1
+#define CONFIG_MV_SDHCI			1
+#define CONFIG_DOS_PARTITION		1
+#define CONFIG_EFI_PARTITION		1
+#define CONFIG_SYS_MMC_NUM		2
+#define CONFIG_SYS_MMC_BASE		{0xD4280000, 0xd4281000}
+#endif
+
+/*
+ * MMC definition
+ */
+#ifdef CONFIG_USB_ETHER
+#define CONFIG_USB_GADGET_MV	1
+#define CONFIG_USB_GADGET_DUALSPEED	1
+#define CONFIG_CMD_NET		1
+#define CONFIG_IPADDR		192.168.1.101
+#define CONFIG_SERVERIP		192.168.1.100
+#define CONFIG_ETHADDR		08:00:3e:26:0a:5b
+#define CONFIG_NET_MULTI	1
+#define CONFIG_USBNET_DEV_ADDR 	"00:0a:fa:63:8b:e8"
+#define CONFIG_USBNET_HOST_ADDR	"0a:fa:63:8b:e8:0a"
+#define CONFIG_MV_UDC		1
+#define CONFIG_URB_BUF_SIZE	256
+#define CONFIG_USB_REG_BASE	0xd4208000
+#define CONFIG_USB_PHY_BASE	0xd4207000
+#endif
+
+#ifdef CONFIG_CMD_FASTBOOT
+#define CONFIG_USBD_VENDORID		0x18d1
+#define CONFIG_USBD_PRODUCTID		0x4e11
+#define CONFIG_USBD_MANUFACTURER	"Marvell Inc."
+#define CONFIG_USBD_PRODUCT_NAME	"Android 2.1"
+#define CONFIG_SERIAL_NUM		"MRUUUVLs001"
+#define CONFIG_USBD_CONFIGURATION_STR	"fastboot"
+#define CONFIG_SYS_FB_YAFFS		{"cache", "system", "userdata", "telephony"}
+#define CONFIG_SYS_FASTBOOT_ONFLY_SZ	0x40000
+#define USB_LOADADDR			0x100000
+#endif
+
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"autostart=yes\0"				\
+	"verify=no\0"					\
+	"cdc_connect_timeout=60\0"
+
 #endif /* _PANTHEON_CONFIG_H */
diff --git a/arch/arm/include/asm/arch-pantheon/cpu.h b/arch/arm/include/asm/arch-pantheon/cpu.h
index 60955c5a55..b30112a816 100644
--- a/arch/arm/include/asm/arch-pantheon/cpu.h
+++ b/arch/arm/include/asm/arch-pantheon/cpu.h
@@ -43,6 +43,19 @@ struct panthmpmu_registers {
 };
 
 /*
+ * Application Power Management (APMU) Registers
+ * Refer Register Datasheet 9.2
+ */
+struct panthapmu_registers {
+	u8 pad0[0x0054];
+	u32 sd1;	/*0x0054*/
+	u8 pad1[0x005c - 0x054 - 4];
+	u32 usb;	/*0x005c*/
+	u8 pad2[0x00e0 - 0x05c - 4];
+	u32 sd3;	/*0x00e0*/
+};
+
+/*
  * APB Clock Reset/Control Registers
  * Refer Register Datasheet 6.14
  */
@@ -77,5 +90,6 @@ struct panthcpu_registers {
  */
 u32 panth_sdram_base(int);
 u32 panth_sdram_size(int);
+int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks);
 
 #endif /* _PANTHEON_CPU_H */
diff --git a/arch/arm/include/asm/arch-pantheon/mfp.h b/arch/arm/include/asm/arch-pantheon/mfp.h
index e9391961b1..b868ab8f65 100644
--- a/arch/arm/include/asm/arch-pantheon/mfp.h
+++ b/arch/arm/include/asm/arch-pantheon/mfp.h
@@ -38,6 +38,18 @@
 #define MFP54_CI2C_SDA		(MFP_REG(0x1b4) | MFP_AF2 | MFP_DRIVE_MEDIUM)
 
 /* More macros can be defined here... */
+#define MFP_MMC1_DAT7		(MFP_REG(0x84) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT6		(MFP_REG(0x88) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT5		(MFP_REG(0x8c) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT4		(MFP_REG(0x90) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_DAT3		(MFP_REG(0x94) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT2		(MFP_REG(0x98) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT1		(MFP_REG(0x9c) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_DAT0		(MFP_REG(0xa0) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CMD		(MFP_REG(0xa4) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CLK		(MFP_REG(0xa8) | MFP_AF0 | MFP_DRIVE_FAST)
+#define MFP_MMC1_CD		(MFP_REG(0xac) | MFP_AF0 | MFP_DRIVE_MEDIUM)
+#define MFP_MMC1_WP		(MFP_REG(0xb0) | MFP_AF0 | MFP_DRIVE_MEDIUM)
 
 #define MFP_PIN_MAX	117
 #endif
diff --git a/arch/arm/include/asm/arch-pantheon/pantheon.h b/arch/arm/include/asm/arch-pantheon/pantheon.h
index e4ed087b0c..d5e9ba048e 100644
--- a/arch/arm/include/asm/arch-pantheon/pantheon.h
+++ b/arch/arm/include/asm/arch-pantheon/pantheon.h
@@ -25,13 +25,6 @@
 #ifndef _PANTHEON_H
 #define _PANTHEON_H
 
-#ifndef __ASSEMBLY__
-#include <asm/types.h>
-#include <asm/io.h>
-#endif	/* __ASSEMBLY__ */
-
-#include <asm/arch/cpu.h>
-
 /* Common APB clock register bit definitions */
 #define APBC_APBCLK     (1<<0)  /* APB Bus Clock Enable */
 #define APBC_FNCLK      (1<<1)  /* Functional Clock Enable */
@@ -39,6 +32,12 @@
 /* Functional Clock Selection Mask */
 #define APBC_FNCLKSEL(x)        (((x) & 0xf) << 4)
 
+/* Common APMU register bit definitions */
+#define APMU_PERI_CLK	(1<<4)	/* Peripheral Clock Enable */
+#define APMU_AXI_CLK	(1<<3)	/* AXI Clock Enable*/
+#define APMU_PERI_RST	(1<<1)	/* Peripheral Reset */
+#define APMU_AXI_RST	(1<<0)	/* AXI Reset */
+
 /* Register Base Addresses */
 #define PANTHEON_DRAM_BASE	0xB0000000
 #define PANTHEON_TIMER_BASE	0xD4014000
@@ -49,6 +48,7 @@
 #define PANTHEON_GPIO_BASE	0xD4019000
 #define PANTHEON_MFPR_BASE	0xD401E000
 #define PANTHEON_MPMU_BASE	0xD4050000
+#define PANTHEON_APMU_BASE	0xD4282800
 #define PANTHEON_CPU_BASE	0xD4282C00
 
 #endif /* _PANTHEON_H */
diff --git a/arch/arm/include/asm/arch-pantheon/usb.h b/arch/arm/include/asm/arch-pantheon/usb.h
new file mode 100644
index 0000000000..54adce8817
--- /dev/null
+++ b/arch/arm/include/asm/arch-pantheon/usb.h
@@ -0,0 +1,106 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef _PANTHEON_USB_H
+#define _PANTHEON_USB_H
+
+/*
+ * USB OTG PHY(UTMI) Registers
+ * Refer Register Datasheet A.38
+ */
+struct usb_file {
+	u32 pad0;		/* 0x00 */
+#define BIT160			0x1
+#define USB_CTL_29_28(x)	((x & 0x3) << 28)
+#define PU_REF			(1 << 20)
+#define REG_ARC_DPDM_MODE	(1 << 12)
+#define PU_PLL			(1 << 1)
+#define PU			(1 << 0)
+	u32 UTMI_CTRL;		/* 0x04 */
+#define ALLSET			0x3
+#define PLLCALI12(x)		((x & 0x3) << 29)
+#define PLLVDD18(x)		((x & 0x3) << 27)
+#define PLLVDD12(x)		((x & 0x3) << 25)
+#define PLLREADY		(1 << 23)
+#define MIDKVCO			0x3
+#define KVCO(x)			((x & 0x7) << 15)
+#define MUA10			1
+#define ICP(x)			((x & 0x7) << 12)
+#define DIV240			0xee
+#define FBDIV(x)		((x & 0xff) << 4)
+#define DIV13			0xb
+#define REFDIV(x)		(x & 0xf)
+	u32 UTMI_PLL;		/* 0x08 */
+#define FS_DEF			0x8
+#define REG_EXT_FS_RCAL(x)	((x & 0xf) << 27)
+#define VDD_DEF			0x1
+#define VDD_ALL			0x3
+#define TXVDD18(x)		((x & 0x3) << 24)
+#define TXVDD12(x)		((x & 0x3) << 22)
+#define TXDATA_BLOCK_EN		(1 << 21)
+#define CLK60VAL		0x4
+#define CK60_PHSEL(x)		((x & 0xf) << 17)
+#define VTH45OHM		0x4
+#define IMPCAL_VTH(x)		((x & 0x7) << 14)
+#define HSVAL			0xf
+#define HSDRV_EN(x)		((x & 0xf) << 7)
+#define HS45OHM			0x8
+#define REG_EXT_HS_RCAL(x)	((x & 0xf) << 3)
+#define MA18			0x3
+#define AMP(x)			(x & 0x7)
+	u32 UTMI_TX;		/* 0x0c */
+#define EARLY_VOS_ON_EN		(1 << 31)
+#define RXDATA_BLOCK_EN		(1 << 30)
+#define DEFLEN			0x2
+#define RXDATA_BLOCK_LENGTH(x)	((x & 0x3) << 28)
+#define EDGE_DET_EN		(1 << 27)
+#define CLK_16CYCLE		0x2
+#define S2TO3_DLY_SEL(x)	((x & 0x3) << 25)
+#define PHASE_FREEZE_DLY	(1 << 20)
+#define REG_USQ_LENGTH		(1 << 19)
+#define REG_ACQ_LENGTH(x)	((x & 0x3) << 17)
+#define SQUELCH_9HIGH		0x2
+#define REQ_SQ_LENGTH(x)	((x & 0x3) << 15)
+#define VL2425_VH2925		0x2
+#define DISCON_THRESH(x)	((x & 0x3) << 8)
+#define VOSL360_V100H450_V150H583	0x7
+#define SQ_THRESH(x)		((x & 0xf) << 4)
+#define MU20			1
+#define INTPI(x)		(x & 0x3)
+	u32 UTMI_RX;		/* 0x10 */
+#define V145			0x1
+#define RXVDD12(x)		((x & 0x3) << 6)
+#define ALLEN			0xf
+#define FSDRV_EN(x)		((x & 0xf) << 2)
+#define REGDEF			0x2
+#define REG_IMP_CAL_DLY(x)	(x & 0x3)
+	u32 UTMI_IVREF;		/* 0x14 */
+	u32 pad1[(0x30 - 0x14 - 4) / 4];
+	u32 UTMI_CTL1;		/* 0x30 */
+	u32 pad2[(0x3c - 0x30 - 4) / 4];
+#define TEST_GRP_5_VALUE	0xfedcba98
+	u32 UTMI_TEST_GRP_5;	/* 0x3c */
+};
+
+#endif /* _PANTHEON_USB_H */
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h
index d0518be28c..eef6a5a8f2 100644
--- a/arch/arm/include/asm/cache.h
+++ b/arch/arm/include/asm/cache.h
@@ -42,4 +42,15 @@ static inline void invalidate_l2_cache(void)
 void l2_cache_enable(void);
 void l2_cache_disable(void);
 
+/*
+ * The current upper bound for ARM L1 data cache line sizes is 64 bytes.  We
+ * use that value for aligning DMA buffers unless the board config has specified
+ * an alternate cache line size.
+ */
+#ifdef CONFIG_SYS_CACHELINE_SIZE
+#define ARCH_DMA_MINALIGN	CONFIG_SYS_CACHELINE_SIZE
+#else
+#define ARCH_DMA_MINALIGN	64
+#endif
+
 #endif /* _ASM_CACHE_H */
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h
index a1fd03a1c1..b18a9cc87a 100644
--- a/arch/arm/include/asm/mach-types.h
+++ b/arch/arm/include/asm/mach-types.h
@@ -3312,6 +3312,7 @@ extern unsigned int __machine_arch_type;
 #define MACH_TYPE_T5388P               3336
 #define MACH_TYPE_DINGO                3337
 #define MACH_TYPE_GOFLEXHOME           3338
+#define MACH_TYPE_G50                  3339
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
diff --git a/arch/arm/include/asm/setup.h b/arch/arm/include/asm/setup.h
index 89df4dc708..8c8578221e 100644
--- a/arch/arm/include/asm/setup.h
+++ b/arch/arm/include/asm/setup.h
@@ -205,6 +205,16 @@ struct tag_memclk {
 	u32 fmemclk;
 };
 
+#ifdef CONFIG_MARVELL_TAG
+/* Marvell SoC profile info, including stepping, profile... */
+#define ATAG_PROFILE	0x41000403
+
+struct tag_mv_profile {
+	u32 soc_prof;
+	u32 soc_stepping;
+};
+#endif
+
 struct tag {
 	struct tag_header hdr;
 	union {
@@ -227,6 +237,12 @@ struct tag {
 		 * DC21285 specific
 		 */
 		struct tag_memclk	memclk;
+#ifdef CONFIG_MARVELL_TAG
+		/*
+		 * Marvell PXA specific
+		 */
+		struct tag_mv_profile	mv_prof;
+#endif
 	} u;
 };
 
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index 802e833a2e..8aaf84f348 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -48,6 +48,10 @@ static void setup_commandline_tag (bd_t *bd, char *commandline);
 static void setup_initrd_tag (bd_t *bd, ulong initrd_start,
 			      ulong initrd_end);
 # endif
+
+# ifdef CONFIG_MARVELL_TAG
+void setup_mv_prof_tag(void);
+# endif
 static void setup_end_tag (bd_t *bd);
 
 static struct tag *params;
@@ -129,7 +133,8 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
     defined (CONFIG_CMDLINE_TAG) || \
     defined (CONFIG_INITRD_TAG) || \
     defined (CONFIG_SERIAL_TAG) || \
-    defined (CONFIG_REVISION_TAG)
+    defined (CONFIG_REVISION_TAG) || \
+    defined (CONFIG_MARVELL_TAG)
 	setup_start_tag (bd);
 #ifdef CONFIG_SERIAL_TAG
 	setup_serial_tag (&params);
@@ -147,6 +152,9 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images)
 	if (images->rd_start && images->rd_end)
 		setup_initrd_tag (bd, images->rd_start, images->rd_end);
 #endif
+#ifdef CONFIG_MARVELL_TAG
+	setup_mv_prof_tag();
+#endif
 	setup_end_tag(bd);
 #endif
 
@@ -328,6 +336,19 @@ void setup_revision_tag(struct tag **in_params)
 }
 #endif  /* CONFIG_REVISION_TAG */
 
+#ifdef CONFIG_MARVELL_TAG
+extern unsigned int mv_soc_stepping;
+extern unsigned int mv_profile;
+void setup_mv_prof_tag(void)
+{
+	params->hdr.tag = ATAG_PROFILE;
+	params->hdr.size = tag_size(tag_mv_profile);
+	params->u.mv_prof.soc_stepping = mv_soc_stepping;
+	params->u.mv_prof.soc_prof = mv_profile;
+	params = tag_next(params);
+}
+#endif /* CONFIG_MARVELL_TAG */
+
 static void setup_end_tag (bd_t *bd)
 {
 	params->hdr.tag = ATAG_NONE;
diff --git a/board/Marvell/abilene/Makefile b/board/Marvell/abilene/Makefile
new file mode 100644
index 0000000000..c702d9710e
--- /dev/null
+++ b/board/Marvell/abilene/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+# Lei Wen, <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= abilene.o
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/abilene/abilene.c b/board/Marvell/abilene/abilene.c
new file mode 100644
index 0000000000..45b9bb889c
--- /dev/null
+++ b/board/Marvell/abilene/abilene.c
@@ -0,0 +1,591 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+#if defined(CONFIG_PXA168_FB)
+#include <pxa168fb.h>
+#include <video_fb.h>
+#if defined(CONFIG_HDMI)
+#include <hdmi.h>
+#endif
+#include "../common/marvell.h"
+#endif
+#ifdef CONFIG_ARMADA100_FEC
+#include <net.h>
+#include <netdev.h>
+#include <miiphy.h>
+#endif /* CONFIG_ARMADA100_FEC */
+#include <mmp_freq.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX8925_SLAVE_ADDR		0x3c
+#define MAX77601_SLAVE_ADDR 		0x1c
+
+#define MAX77601_VDVSSD0_REG 		0x1B
+#define MAX77601_CNFG1_L1_REG		0x25
+#define MAX77601_CNFG1_L7_REG		0x31
+#define MAX77601_CNFG_GPIO5		0x3B
+#define MAX77601_AME_GPIO_REG 		0x40
+#define MAX77601_FPS_L1_REG 		0x47
+#define MAX77601_FPS_L7_REG 		0x4D
+
+#define MAX77601_FPSSRC_NOTFPS		(0x3 << 6)
+#define MAX77601_MODE_NORMAL		(0x3 << 6)
+#define MAX77601_L1_1P2V		0x10
+#define MAX77601_L7_1P2V		0x08
+#define MAX77601_VSD3_REG		0x19
+#define MAX77601_SD0_1P25V		0x34
+#define MAX77601_SD3_2P8V		0xB0
+
+#define MAX77601_ONOFFCNFG2		0x42
+#define MAX77601_ONOFFCNFG1		0x41
+#define MAX77601_SFT_RST_WK		0x80
+#define MAX77601_SFT_RST		0x80
+
+#if defined(CONFIG_PXA168_FB)
+static struct dsi_info abilene_dsi = {
+	.id			= 1,
+	.lanes			= 2,
+	.bpp			= 24,
+	.burst_mode		= DSI_BURST_MODE_SYNC_EVENT,
+	.hbp_en			= 1,
+	.hfp_en			= 1,
+};
+
+static struct fb_videomode video_modes[] = {
+	[0] = {
+		.pixclock	= 62500,
+		.refresh	= 60,
+		.xres		= FB_XRES,
+		.yres		= FB_YRES,
+		.hsync_len	= 2,
+
+		.left_margin	= 10,
+		.right_margin	= 116,
+		.vsync_len	= 2,
+		.upper_margin	= 10,
+		.lower_margin	= 4,
+		.sync		= FB_SYNC_VERT_HIGH_ACT \
+				  | FB_SYNC_HOR_HIGH_ACT,
+	},
+};
+
+static struct pxa168fb_mach_info mmp2_mipi_lcd_info = {
+	.id			= "GFX Layer",
+	.sclk_src		= 500000000,
+	.sclk_div		= 0xe0001210,
+	.num_modes		= ARRAY_SIZE(video_modes),
+	.modes			= video_modes,
+	.pix_fmt		= PIX_FMT_RGB565,
+	.burst_len		= 16,
+	/*
+	 * don't care about io_pin_allocation_mode and dumb_mode
+	 * since the panel is hard connected with lcd panel path
+	 * and dsi1 output
+	 */
+	.panel_rgb_reverse_lanes = 0,
+	.invert_composite_blank = 0,
+	.invert_pix_val_ena     = 0,
+	.invert_pixclock        = 0,
+	.panel_rbswap           = 0,
+	.active			= 1,
+	.enable_lcd             = 1,
+	.spi_gpio_cs            = -1,
+	.spi_gpio_reset         = -1,
+	.max_fb_size		= FB_XRES * FB_YRES * 8 + 4096,
+	.phy_type		= DSI2DPI,
+	.phy_info		= &abilene_dsi,
+	.twsi_id		= 4,
+};
+#if defined(CONFIG_HDMI)
+static struct pxa168fb_mach_info mmp2_hdmi_info = {
+	.id			= "GFX Layer",
+	.index			= 1,
+	.sclk_src		= 500000000,
+	.sclk_div		= 0xe0001210,
+	.num_modes		= ARRAY_SIZE(video_modes),
+	.modes			= &cea_modes[4],
+	.pix_fmt		= PIX_FMT_RGB565,
+	.burst_len		= 16,
+	/*
+	 * don't care about io_pin_allocation_mode and dumb_mode
+	 * since the panel is hard connected with lcd panel path
+	 * and dsi1 output
+	 */
+	.panel_rgb_reverse_lanes = 0,
+	.invert_composite_blank = 0,
+	.invert_pix_val_ena     = 0,
+	.invert_pixclock        = 0,
+	.panel_rbswap           = 0,
+	.active			= 1,
+	.enable_lcd             = 1,
+	.spi_gpio_cs            = -1,
+	.spi_gpio_reset         = -1,
+	.max_fb_size		= FB_XRES * FB_YRES * 8 + 4096,
+	.phy_type		= DPI,
+};
+#endif
+#endif
+
+#if defined(CONFIG_PXA168_FB)
+static GraphicDevice ctfb;
+void *lcd_init(void)
+{
+	void *ret;
+
+	ret = (void *)pxa168fb_init(&mmp2_mipi_lcd_info);
+#if defined(CONFIG_HDMI)
+	pxa168fb_init(&mmp2_hdmi_info);
+#endif
+
+	return ret;
+}
+
+void *video_hw_init(void)
+{
+	struct pxa168fb_info *fbi;
+	struct fb_var_screeninfo *var;
+	unsigned long t1, hsynch, vsynch;
+	fbi = lcd_init();
+	var = fbi->var;
+
+	ctfb.winSizeX = var->xres;
+	ctfb.winSizeY = var->yres;
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (var->left_margin + var->xres +
+	      var->right_margin + var->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= var->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (var->upper_margin + var->yres +
+	       var->lower_margin + var->vsync_len);
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(ctfb.modeIdent, "%dx%dx%d %ldkHz %ldHz", ctfb.winSizeX,
+		ctfb.winSizeY, var->bits_per_pixel, (hsynch / 1000),
+		vsynch);
+
+	ctfb.frameAdrs = (unsigned int) fbi->fb_start;
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 2;
+	ctfb.gdfIndex = GDF_16BIT_565RGB;
+
+	ctfb.isaBase = 0x9000000;
+	ctfb.pciBase = (unsigned int) fbi->fb_start;
+	ctfb.memSize = fbi->fb_size;
+
+	/* Cursor Start Address */
+	ctfb.dprBase = (unsigned int) fbi->fb_start + (ctfb.winSizeX \
+			* ctfb.winSizeY * ctfb.gdfBytesPP);
+	if ((ctfb.dprBase & 0x0fff) != 0) {
+		/* allign it */
+		ctfb.dprBase &= 0xfffff000;
+		ctfb.dprBase += 0x00001000;
+	}
+	ctfb.vprBase = (unsigned int) fbi->fb_start;
+	ctfb.cprBase = (unsigned int) fbi->fb_start;
+
+	return &ctfb;
+}
+#endif
+
+static u32 boardid;
+static u8 boardrev, boardtype;
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* Enable TWSI1 for PMIC */
+		TWSI1_SCL,
+		TWSI1_SDA,
+
+		/* Enable TWSI5 */
+		TWSI5_SCL,
+		TWSI5_SDA,
+
+		/* Enable TWSI6 */
+		TWSI6_SCL,
+		TWSI6_SDA,
+
+		/* Enable LCD */
+		LCD_RESET,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+		MMC1_WP,
+		MMC1_GPIO13, /* EN_3P3V_MMC_N */
+
+		/* MMC3 */
+		MMC3_DATA7,
+		MMC3_DATA6,
+		MMC3_DATA5,
+		MMC3_DATA4,
+		MMC3_DATA3,
+		MMC3_DATA2,
+		MMC3_DATA1,
+		MMC3_DATA0,
+		MMC3_CLK,
+		MMC3_CMD,
+
+		/* Fast Ethernet */
+#if defined(CONFIG_ARMADA100_FEC)
+		FE_LED0_N,
+		FE_LED1_N,
+		FE_LED2_N,
+#endif
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+
+	return 0;
+}
+
+#define LDOCTL17	0x14
+#define LDO17VOUT	0x16
+#define LDOCTL3		0x20
+#define LDO3VOUT	0x22
+#define FASTBOOT_KEY	20
+int board_init(void)
+{
+	u8 data;
+
+#if defined(CONFIG_PXA168_FB)
+	/* TC358765 reset */
+	gpio_direction_output(LCD_RST_GPIO, 0);
+	udelay(100000);
+#endif
+
+	i2c_set_bus_num(0);
+
+	/* set ame for gpio 4/5/7 */
+	data = 0xb0;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_AME_GPIO_REG, 1, &data, 1);
+
+	/* Set GPIO5 active low, VCXO_EN is low when suspend */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_CNFG_GPIO5, 1, &data, 1);
+	data &= ~0x1;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG_GPIO5, 1, &data, 1);
+
+	/* Enable 1.2V pmic_1p2v_mipi (Max77601 LDO1) at first */
+	/* not configured as part of a flexible power sequence */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_FPS_L1_REG, 1, &data, 1);
+	data |= MAX77601_FPSSRC_NOTFPS;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_FPS_L1_REG, 1, &data, 1);
+
+	data = MAX77601_MODE_NORMAL | MAX77601_L1_1P2V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG1_L1_REG, 1, &data, 1);
+
+	/* Then enable 1.2V pmic_1p2v_mipi_logic (Max77601 LDO7)  */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_FPS_L7_REG, 1, &data, 1);
+	data |= MAX77601_FPSSRC_NOTFPS;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_FPS_L7_REG, 1, &data, 1);
+
+	data = MAX77601_MODE_NORMAL | MAX77601_L7_1P2V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG1_L7_REG, 1, &data, 1);
+
+	gpio_direction_input(FASTBOOT_KEY);
+
+	#define GPIO_EN_3P3V_MMC_N	13
+	gpio_direction_output(GPIO_EN_3P3V_MMC_N, 0);
+
+	/* OEM UniqueID in the NTIM
+	 * 32bit format: NN NN NN TV
+	 * NNNNNN: board name
+	 *	0x594553 (YES, YellowStone)
+	 *	0x414249 (ABI, Abilene)
+	 * T: type
+	 *	0x1 (Pop board)
+	 *	0x0 (Discrete board)
+	 * V: revision
+	*/
+	boardid = *(volatile unsigned int *)0xd1020010;
+	boardrev = boardid & 0xF;
+	boardtype = (boardid >> 4) & 0xF;
+	boardid = boardid >> 8;
+
+	if (boardid == 0x414249)
+		gd->bd->bi_arch_number = MACH_TYPE_ABILENE;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x3c00;
+
+	return 0;
+}
+
+#if defined(CONFIG_PXA168_FB)
+void show_logo(void)
+{
+	char cmd[100];
+	int wide, high;
+
+	/* Show marvell logo */
+	wide = 213;
+	high = 125;
+	sprintf(cmd, "bmp display %p %d %d", MARVELL, \
+		(FB_XRES - wide) / 2, (FB_YRES - high) / 2);
+	run_command(cmd, 0);
+}
+#endif
+
+int misc_init_r(void)
+{
+	int i;
+	ulong sz;
+#if defined(CONFIG_PXA168_FB)
+	show_logo();
+#endif
+	if (boardid == 0x414249)
+		printf("\nBoard: Abilene (%s)\n",
+			boardtype ? "Pop" : "Discrete");
+
+#if defined(CONFIG_MMP_POWER)
+	set_volt(1250);	/* set 1.25v for vcc_core */
+	setop(18); 	/* set op for 1GHz */
+#endif
+
+	setenv("fbenv", "mmc0");
+
+	/* If Volumn down key is pressed, launch fastboot */
+	if (!gpio_get_value(FASTBOOT_KEY))
+		run_command("fb", 0);
+
+	for (i = 0, sz = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		sz += gd->bd->bi_dram[i].size;
+
+	setenv("bootargs", "rdinit=/busybox/rdinit androidboot.console=ttyS2 console=ttyS2,115200 emmc_boot fb_share");
+	if (sz > 0x20000000)
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xc000000", 0);
+	else
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xA000000", 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+#define I2CEN		0x7
+#define LDOSEQ(x)	((x & 0x7) << 2)
+#define LDO_DC		0x2
+#define LDO_EN		0x1
+#define LDOCTL_11	0x40
+#define LDO_3V		0x2d
+#define LDOVOUT_11	0x42
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i, data;
+	i2c_set_bus_num(0);
+
+	/*
+	 * Set 2.8V power (pmic_sdmmc - max77601_SD3) for sd/mmc
+	 * The power domain is shared with other components' power
+	 * the voltage should be 2.8V on B0, will default enabled when
+	 * booting up
+	 */
+	data = MAX77601_SD3_2P8V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_VSD3_REG, 1, &data, 1);
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+		writel(DIS_PAD_SD_CLK_GATE | CLK_GATE_ON | CLK_GATE_CTL \
+		       | WTC(WTC_DEF) | RTC(RTC_DEF),
+		       mmc_base_address[i] + SD_FIFO_PARAM);
+	}
+	writew(SDCLK_DELAY(0x1f) | SDCLK_SEL | WR_ENDIAN | RD_ENDIAN \
+	       | DMA_SIZE(DMA_FIFO_128) | BURST_SIZE(BURST_64),
+	       mmc_base_address[1] + SD_CLOCK_AND_BURST_SIZE_SETUP);
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count;
+
+	if (cpu_is_ax()) {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK | REFDIV_MASK),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | VDD12(1) | REFDIV(0xd)
+		       | FB_DIV(0xf0)), &file->pll_reg0);
+	} else {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK_B0 | REFDIV_MASK_B0),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | REFDIV_B0(0xd)
+		       | FB_DIV_B0(0xf0)), &file->pll_reg0);
+	}
+
+	writel(readl(&file->pll_reg1) & ~(UTMI_PLL_PU | PLL_ICP_MASK
+	       | PLL_KVCO_MASK | PLL_CALI12_MASK), &file->pll_reg1);
+	writel(readl(&file->pll_reg1) | (UTMI_PLL_PU | PLL_ICP(2)
+	       | PLL_KVCO(3) | PLL_CALI12(3)), &file->pll_reg1);
+
+
+	writel(readl(&file->tx_reg0) & ~IMPCAL_VTH_MASK, &file->tx_reg0);
+	writel(readl(&file->tx_reg0) | IMPCAL_VTH(2), &file->tx_reg0);
+
+	writel(readl(&file->tx_reg1) & ~(CK60_PHSEL_MASK | AMP_MASK
+	       | TX_VDD12_MASK), &file->tx_reg1);
+	writel(readl(&file->tx_reg1) | (CK60_PHSEL(4) | AMP(4)
+	       | TX_VDD12(3)), &file->tx_reg1);
+
+	writel(readl(&file->tx_reg2) & ~DRV_SLEWRATE(3), &file->tx_reg2);
+	writel(readl(&file->tx_reg2) | DRV_SLEWRATE(3), &file->tx_reg2);
+
+	writel(readl(&file->rx_reg0) & ~(SQ_LENGTH_MASK | SQ_THRESH_MASK),
+	       &file->rx_reg0);
+	writel(readl(&file->rx_reg0) | (SQ_LENGTH(0x2) | SQ_THRESH(0xa)),
+	       &file->rx_reg0);
+
+	writel(readl(&file->ana_reg1) | ANA_PU, &file->ana_reg1);
+
+	writel(readl(&file->otg_reg0) | PU_OTG, &file->otg_reg0);
+
+	udelay(200);
+	writel(readl(&file->pll_reg1) | VCOCAL_START, &file->pll_reg1);
+
+	udelay(200);
+	writel(readl(&file->tx_reg0) | RCAL_START, &file->tx_reg0);
+	udelay(40);
+	writel(readl(&file->tx_reg0) & ~RCAL_START, &file->tx_reg0);
+	udelay(400);
+
+	/* make sure phy is ready */
+	count = 100;
+	while(((readl(&file->pll_reg1) & PLL_READY)==0) && count--)
+		udelay(1000);
+	if (count <= 0) {
+		printf("%s %d: calibrate timeout, UTMI_PLL %x\n",
+				__func__, __LINE__, readl(&file->pll_reg1));
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_ARMADA100_FEC)
+	res = armada100_fec_register(AMAD6_FEC_BASE);
+#endif
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
+
+#ifdef CONFIG_ARMADA100_FEC
+void fe_phy_regs_set(char *name, int phy_adr)
+{
+	/*
+         * MMP3_A0 Fast Ethernet PHY register settings which is to
+         * adjust to basic mode voltage and auto-negotiation
+         */
+        miiphy_write(name, phy_adr, 0x10, 0x138);
+        miiphy_write(name, phy_adr, 0x1D, 4);
+        miiphy_write(name, phy_adr, 0x1E, 0x51C);
+        miiphy_write(name, phy_adr, 0x1D, 9);
+        miiphy_write(name, phy_adr, 0x1E, 0x2081);
+        miiphy_write(name, phy_adr, 0x1C, 0xC03);
+}
+#endif
+
+/*
+ * Reset the cpu by set pmic register
+ */
+void reset_cpu(ulong ignored)
+{
+	u8 data;
+	i2c_set_bus_num(0);
+
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG2, 1, &data, 1);
+	data |= MAX77601_SFT_RST_WK;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG2, 1, &data, 1);
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG1, 1, &data, 1);
+	data |= MAX77601_SFT_RST;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG1, 1, &data, 1);
+	udelay(10*1000);
+
+	while (1);
+}
+
+#ifdef CONFIG_DISPLAY_BOARDINFO
+extern u32 smp_hw_cpuid(void);
+extern u32 smp_config(void);
+int checkboard(void)
+{
+	u32 val;
+
+	val = smp_hw_cpuid();
+	printf("Boot Core: %s\n"
+			, ((val == 0)
+			? ("MP1")
+			: ((val == 2)
+				? ("MM")
+				: ((val == 1)
+					? ("MP1")
+					: ("UNKNOWN")))));
+	val = smp_config();
+	printf("Available Cores: %s %s %s\n"
+			, (val & 0x1) ? ("MP1") : ("")
+			, (val & 0x2) ? ("MP2") : ("")
+			, (val & 0x4) ? ("MM") : ("")
+	);
+
+	printf("DRAM interleave size: 0x%08x\n", dram_interleave_size());
+
+	return 0;
+}
+#endif
diff --git a/board/Marvell/aspenite/aspenite.c b/board/Marvell/aspenite/aspenite.c
index 34ac7aa553..3be33bf773 100644
--- a/board/Marvell/aspenite/aspenite.c
+++ b/board/Marvell/aspenite/aspenite.c
@@ -25,6 +25,7 @@
 
 #include <common.h>
 #include <mvmfp.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/mfp.h>
 #include <asm/arch/armada100.h>
 
diff --git a/board/Marvell/brownstone/Makefile b/board/Marvell/brownstone/Makefile
new file mode 100644
index 0000000000..ff996bfcba
--- /dev/null
+++ b/board/Marvell/brownstone/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+# Lei Wen, <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= brownstone.o plat_ver.o
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/brownstone/brownstone.c b/board/Marvell/brownstone/brownstone.c
new file mode 100644
index 0000000000..d536e8996b
--- /dev/null
+++ b/board/Marvell/brownstone/brownstone.c
@@ -0,0 +1,680 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+#if defined(CONFIG_PXA168_FB)
+#include <pxa168fb.h>
+#include <video_fb.h>
+#include "../common/marvell.h"
+#endif
+#include <mv_wtm.h>
+#include "plat_ver.h"
+#ifdef CONFIG_MV_RECOVERY
+#include <mv_recovery.h>
+#define RECOVERY_KEY	17
+#define RTC_CLK_REG	0xD4015000
+#endif	/* CONFIG_MV_RECOVERY */
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MAX8925_SLAVE_ADDR	0x3c
+
+void show_charge_logo(unsigned char *logo, int wide, int high, int offset)
+{
+	int i = 0;
+	unsigned char *ptrBuf_bmp = NULL;
+
+	ptrBuf_bmp = DEFAULT_FB_BASE+(FB_XRES*FB_YRES)
+		- FB_XRES*high - wide - offset;
+
+	/* ensure the base address is not a odd number */
+	if ((int)ptrBuf_bmp & 1)
+		ptrBuf_bmp += 1;
+
+	for (i = 0; i < high; i++) {
+		memcpy(ptrBuf_bmp, logo, wide*2);
+		logo += wide*2;
+		ptrBuf_bmp += FB_XRES * 2;
+	}
+}
+
+void lcd_flush(void)
+{
+	memset((unsigned char *) (DEFAULT_FB_BASE),
+			0x0, FB_XRES * FB_YRES*6);
+}
+
+#if defined(CONFIG_PXA168_FB)
+static struct dsi_info brownstone_dsi = {
+	.id			= 1,
+	.lanes			= 4,
+	.bpp			= 16,
+	.burst_mode		= DSI_BURST_MODE_BURST,
+	.hbp_en			= 1,
+	.hfp_en			= 1,
+};
+
+static struct fb_videomode video_modes[] = {
+	[0] = {
+		.pixclock	= 62500,
+		.refresh	= 60,
+		.xres		= FB_XRES,
+		.yres		= FB_YRES,
+		.hsync_len	= 2,
+
+		.left_margin	= 12,
+		.right_margin	= 315,
+		.vsync_len	= 2,
+		.upper_margin	= 10,
+		.lower_margin	= 4,
+		.sync		= FB_SYNC_VERT_HIGH_ACT \
+				  | FB_SYNC_HOR_HIGH_ACT,
+	},
+};
+
+static struct pxa168fb_mach_info mmp2_mipi_lcd_info = {
+	.id			= "GFX Layer",
+	.sclk_src		= 260000000,
+	.sclk_div		= 0x40000104,
+	.num_modes		= ARRAY_SIZE(video_modes),
+	.modes			= video_modes,
+	.pix_fmt		= PIX_FMT_RGB565,
+	.burst_len		= 16,
+	/*
+	 * don't care about io_pin_allocation_mode and dumb_mode
+	 * since the panel is hard connected with lcd panel path
+	 * and dsi1 output
+	 */
+	.panel_rgb_reverse_lanes = 0,
+	.invert_composite_blank = 0,
+	.invert_pix_val_ena     = 0,
+	.invert_pixclock        = 0,
+	.panel_rbswap           = 0,
+	.active			= 1,
+	.enable_lcd             = 1,
+	.spi_gpio_cs            = -1,
+	.spi_gpio_reset         = -1,
+	.max_fb_size		= FB_XRES * FB_YRES * 8 + 4096,
+	.phy_type		= DSI2DPI,
+	.phy_info		= &brownstone_dsi,
+	.twsi_id		= 4,
+};
+#endif
+
+#define PWM3_BASE	0xD401A800
+#define APB_CLK_REG_BASE	0xD4015000
+
+#define GPIO83_LCD_RST		83
+#define GPIO128			128
+#define GPIO89			89
+#define GPIO82			82
+
+#define PMUM_CGR_PJ		0x1024
+#define MFP_GPIO53		(MV_MFPR_BASE + 0x128)
+
+#define APBC_PWM3_CLK_RST	(APB_CLK_REG_BASE + 0x0044)
+#define PWM_CR3			(PWM3_BASE + 0x00)
+#define PWM_DCR			(PWM3_BASE + 0x04)
+#define PWM_PCR			(PWM3_BASE + 0x08)
+
+#if defined(CONFIG_PXA168_FB)
+void set_LCD_5V_power(int on)
+{
+	if (on)
+		gpio_direction_output(GPIO89, 1);
+	else
+		gpio_direction_output(GPIO89, 0);
+
+}
+void turn_off_backlight(void)
+{
+	__raw_writel(0, PWM_CR3);
+	__raw_writel(0, PWM_DCR);
+
+	/* set panel 5V power off */
+	set_LCD_5V_power(0);
+}
+
+void turn_on_backlight(void)
+{
+	int duty_ns = 1000000, period_ns = 2000000;
+	unsigned long period_cycles, prescale, pv, dc;
+
+	period_cycles = 52000;
+	if (period_cycles < 1)
+		period_cycles = 1;
+
+	prescale = (period_cycles - 1) / 1024;
+	pv = period_cycles / (prescale + 1) - 1;
+
+	if (prescale > 63)
+		return ;
+
+	if (duty_ns == period_ns)
+		dc = (1 << 10);
+	else
+		dc = (pv + 1) * duty_ns / period_ns;
+
+	__raw_writel(prescale, PWM_CR3);
+	__raw_writel(dc, PWM_DCR);
+	__raw_writel(pv, PWM_PCR);
+
+	/* set panel 5V power */
+	set_LCD_5V_power(1);
+}
+
+void close_lcd(void)
+{
+	turn_off_backlight();
+}
+
+static GraphicDevice ctfb;
+void *lcd_init(void)
+{
+	void *ret;
+
+	turn_off_backlight();
+
+	ret = (void *)pxa168fb_init(&mmp2_mipi_lcd_info);
+
+	turn_on_backlight();
+	return ret;
+}
+
+void *video_hw_init(void)
+{
+	struct pxa168fb_info *fbi;
+	struct fb_var_screeninfo *var;
+	unsigned long t1, hsynch, vsynch;
+	fbi = lcd_init();
+	var = fbi->var;
+
+	ctfb.winSizeX = var->xres;
+	ctfb.winSizeY = var->yres;
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (var->left_margin + var->xres +
+	      var->right_margin + var->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= var->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (var->upper_margin + var->yres +
+	       var->lower_margin + var->vsync_len);
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(ctfb.modeIdent, "%dx%dx%d %ldkHz %ldHz", ctfb.winSizeX,
+		ctfb.winSizeY, var->bits_per_pixel, (hsynch / 1000),
+		vsynch);
+
+	ctfb.frameAdrs = (unsigned int) fbi->fb_start;
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 2;
+	ctfb.gdfIndex = GDF_16BIT_565RGB;
+
+	ctfb.isaBase = 0x9000000;
+	ctfb.pciBase = (unsigned int) fbi->fb_start;
+	ctfb.memSize = fbi->fb_size;
+
+	/* Cursor Start Address */
+	ctfb.dprBase = (unsigned int) fbi->fb_start + (ctfb.winSizeX \
+			* ctfb.winSizeY * ctfb.gdfBytesPP);
+	if ((ctfb.dprBase & 0x0fff) != 0) {
+		/* allign it */
+		ctfb.dprBase &= 0xfffff000;
+		ctfb.dprBase += 0x00001000;
+	}
+	ctfb.vprBase = (unsigned int) fbi->fb_start;
+	ctfb.cprBase = (unsigned int) fbi->fb_start;
+
+	return &ctfb;
+}
+#endif
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* Enable TWSI5 */
+		TWSI5_SCL,
+		TWSI5_SDA,
+
+		/* Enable TWSI6 */
+		TWSI6_SCL,
+		TWSI6_SDA,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+		MMC1_WP,
+
+		/* MMC3 */
+		MMC3_DATA7,
+		MMC3_DATA6,
+		MMC3_DATA5,
+		MMC3_DATA4,
+		MMC3_DATA3,
+		MMC3_DATA2,
+		MMC3_DATA1,
+		MMC3_DATA0,
+		MMC3_CLK,
+		MMC3_CMD,
+
+		/* Back light PWM3 */
+		BACK_LIGHT_PWM3,
+
+		/* Enable volume up and down */
+		VOLUME_UP,
+		VOLUME_DOWN,
+
+		/* VERS */
+		PLAT_VERS_PIN0,
+		PLAT_VERS_PIN1,
+		PLAT_VERS_PIN2,
+		PLAT_VERS_PIN3,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	wtm_read_profile();
+	wtm_read_stepping();
+	return 0;
+}
+
+#define LDOCTL17	0x14
+#define LDO17VOUT	0x16
+#define LDOCTL3		0x20
+#define LDO3VOUT	0x22
+#define FASTBOOT_KEY	16
+
+int display_marvell_banner (void)
+{
+	printf("\n");
+	printf(" __  __                      _ _\n");
+	printf("|  \\/  | __ _ _ ____   _____| | |\n");
+	printf("| |\\/| |/ _` | '__\\ \\ / / _ \\ | |\n");
+	printf("| |  | | (_| | |   \\ V /  __/ | |\n");
+	printf("|_|  |_|\\__,_|_|    \\_/ \\___|_|_|\n");
+	printf(" _   _     ____              _\n");
+	printf("| | | |   | __ )  ___   ___ | |_ \n");
+	printf("| | | |___|  _ \\ / _ \\ / _ \\| __| \n");
+	printf("| |_| |___| |_) | (_) | (_) | |_ \n");
+	printf(" \\___/    |____/ \\___/ \\___/ \\__| ");
+	printf("\n\nMARVELL MMP2 AP.");
+
+	if(cpu_is_armada610_a2())
+		printf("\nBased on MMP2 A2 CPU.\n\n");
+	if(cpu_is_armada610_a1())
+		printf("\nBased on MMP2 A1 CPU.\n\n");
+	if(cpu_is_armada610_a0())
+		printf("\nBased on MMP2 A0 CPU.\n\n");
+	else if(cpu_is_armada610_z1())
+		printf("\nBased on MMP2 Z1 CPU.\n\n");
+	else if(cpu_is_armada610_z0())
+		printf("\nBased on MMP2 Z0 CPU.\n\n");
+
+	if (board_is_mmp2_brownstone_rev5())
+		printf("Board info: BROWNSTONE REV5\n");
+	else if (board_is_mmp2_brownstone_rev4())
+		printf("Board info: BROWNSTONE REV4\n");
+	else if (board_is_mmp2_brownstone_rev2())
+		printf("Board info: BROWNSTONE REV2(3)\n");
+
+#if defined (CONFIG_RECOVERY_MODE) && defined (CONFIG_TRUST_BOOT)
+	if (R_uboot)
+		printf("\nEntering Maverll Recovery Uboot.\n");
+#endif
+	return 0;
+}
+
+static void vbus_en(unsigned int enable)
+{
+	if (board_is_mmp2_brownstone_rev5()) {
+		if (!enable) {
+			/* set GPIO82 output low, otherwise vbus
+			* will pull 5v regualtor output high even
+			* regulator not enabled. */
+			gpio_direction_output(GPIO82, 0);
+			udelay(10000);
+		}
+	}
+	return;
+}
+
+int checkboard (void)
+{
+	display_marvell_banner();
+	wtm_dump_info();
+	return 0;
+}
+
+int board_init(void)
+{
+	u8 data;
+
+	/* arch number of FPGA Board */
+	gd->bd->bi_arch_number = MACH_TYPE_BROWNSTONE;
+	gd->bd->bi_boot_params = 0x3c00;
+
+#if defined(CONFIG_PXA168_FB)
+	/* TC358765 reset */
+	gpio_direction_output(LCD_RST_GPIO, 0);
+	udelay(100000);
+#endif
+
+	i2c_set_bus_num(0);
+	/* Set V_LDO17 to enable power to MMC1 */
+	data = 0x1f;
+	i2c_write(MAX8925_SLAVE_ADDR, LDOCTL17, 1, &data, 1);
+	data = 0x16;
+	i2c_write(MAX8925_SLAVE_ADDR, LDO17VOUT, 1, &data, 1);
+
+	/* Set V_LDO3 to enable power to MMC1 */
+	data = 0x1f;
+	i2c_write(MAX8925_SLAVE_ADDR, LDOCTL3, 1, &data, 1);
+	data = 0x16;
+	i2c_write(MAX8925_SLAVE_ADDR, LDO3VOUT, 1, &data, 1);
+
+	gpio_direction_input(FASTBOOT_KEY);
+	gpio_direction_input(RECOVERY_KEY);
+
+#ifdef CONFIG_MV_RECOVERY
+	/* release RTC from reset state to support recovery function */
+	__raw_writel(0x81, RTC_CLK_REG);
+	/* read magic key from WTM */
+	magic_read();
+#endif
+
+	return 0;
+}
+
+#if defined(CONFIG_PXA168_FB)
+void show_logo(void)
+{
+	char cmd[100];
+	int wide, high;
+
+	/* Show marvell logo */
+	wide = 213;
+	high = 125;
+	sprintf(cmd, "bmp display %p %d %d", MARVELL, \
+		(FB_XRES - wide) / 2, (FB_YRES - high) / 2);
+	run_command(cmd, 0);
+}
+#endif
+
+void send_cmd_to_max8925(unsigned long addr, unsigned int val)
+{
+	/* send pmic slave address with start bit */
+	*(volatile u32 *)0xD4011008 = 0x78;
+	*(volatile u32 *)0xD4011010 = 0x69;
+
+	while (!(*(volatile u32 *)0xD4011018 & 0x40))
+		nop();
+	*(volatile u32 *)0xD4011018 |= 0x40;
+	if (*(volatile u32 *)0xD4011018 & 0x20)
+		*(volatile u32 *)0xD4011018 |= 0x20;
+
+	*(volatile u32 *)0xD4011008 = addr;
+	*(volatile u32 *)0xD4011010 = 0x68;
+
+	while (!(*(volatile u32 *)0xD4011018 & 0x40))
+		nop();
+	*(volatile u32 *)0xD4011018 |= 0x40;
+	if (*(volatile u32 *)0xD4011018 & 0x20)
+		*(volatile u32 *)0xD4011018 |= 0x20;
+
+	*(volatile u32 *)0xD4011008 = val;
+	*(volatile u32 *)0xD4011010 = 0x6A;
+
+	while (!(*(volatile u32 *)0xD4011018 & 0x40))
+		nop();
+	*(volatile u32 *)0xD4011018 |= 0x40;
+	if (*(volatile u32 *)0xD4011018 & 0x20)
+		*(volatile u32 *)0xD4011018 |= 0x20;
+
+	*(volatile u32 *)0xD4011010 = *(volatile u32 *)0xD4011010 & ~0x2;
+	return;
+}
+
+void max8925_power_off(void)
+{
+	printf("\nSystem is shuting down\n");
+	udelay(1000000);
+	send_cmd_to_max8925(0x0f, 0x40);
+	while (1);
+}
+
+#ifdef CONFIG_MMP_POWER
+#define DVFM_BASE_ADDR		0xd1020000
+#define DVFM_STACK_ADDR		0xd1028000
+extern void freq_init_sram(int addr);
+extern void freq_chg_seq(int vaddr, int vstack, int op, int flag);
+extern int set_volt(u32 vol);
+extern int cpu_is_armada610_z1(void);
+extern int cpu_is_armada610_a0(void);
+
+void init_freq(void)
+{
+	/* set voltage to 1350mV by default */
+	set_volt(1350);
+	udelay(10);
+
+	dcache_disable();
+	freq_init_sram(DVFM_BASE_ADDR);
+
+	if (cpu_is_armada610_z1()) {
+		freq_chg_seq(DVFM_BASE_ADDR, DVFM_STACK_ADDR, 2, 1);
+	} else {
+		if (cpu_is_armada610_a0())
+			freq_chg_seq(DVFM_BASE_ADDR, DVFM_STACK_ADDR, 3, 2);
+		else
+			freq_chg_seq(DVFM_BASE_ADDR, DVFM_STACK_ADDR, 3, 3);
+	}
+	dcache_enable();
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_POWEROFF_CHARGE
+	/* Turn off vbus. And 5v enable will be done
+	 * in charge_detect(). Regulator's enable pin
+	 * need a low=>high logic.*/
+	vbus_en(0);
+	if (board_is_mmp2_brownstone_rev5())
+		charge_detect();
+#endif
+
+#if defined(CONFIG_PXA168_FB)
+	show_logo();
+#endif
+
+#ifdef CONFIG_MMP_POWER
+	init_freq();
+#endif
+	setenv("fbenv", "mmc0");
+	setenv("autostart", "no");
+
+	/* If Volume up key is pressed, launch fastboot */
+	if (!gpio_get_value(FASTBOOT_KEY))
+		run_command("fb", 0);
+
+#ifdef CONFIG_MV_RECOVERY
+	mv_recovery();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+#define MAX8925_I2C_SLAVE_ADDR 0x3c
+#define I2CEN          0x7
+#define LDOSEQ(x)      ((x & 0x7) << 2)
+#define LDO_DC         0x2
+#define LDO_EN         0x1
+#define LDOCTL_11      0x40
+#define LDO_3V         0x2d
+#define LDOVOUT_11     0x42
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i, data;
+	i2c_set_bus_num(0);
+	data = LDOSEQ(I2CEN) | LDO_DC | LDO_EN;
+	i2c_write(MAX8925_I2C_SLAVE_ADDR, LDOCTL_11, 1, &data, 1);
+	data = LDO_3V;
+	i2c_write(MAX8925_I2C_SLAVE_ADDR, LDOVOUT_11, 1, &data, 1);
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count = 0;
+	int reg;
+
+	/* initialize the usb phy power */
+	writel(readl(&file->ctrl_reg) | POWER_UP | PLL_POWER_UP |
+			PU_REF |USB_CTL_29_28(1), &file->ctrl_reg );
+	/* UTMI_PLL settings */
+	writel(readl(&file->pll_reg) & ~(REFDIV_MASK | FBDIV_MASK | ICP_MASK |
+				PLLVDD12_MASK | PLLVDD18_MASK |
+				PLLCALLI12_MASK), &file->pll_reg);
+	writel(readl(&file->pll_reg) | REFDIV(13) | FBDIV(240) | ICP(10) |
+			PLL_READY | PLLVDD12(3) | PLLVDD18(3) | PLLCALLI12(3),
+			&file->pll_reg);
+	/* UTMI_TX */
+	writel(readl(&file->tx_reg) & ~(IMPCAL_VTH_MASK | CK60_PHSEL_Mask |
+				TXVDD12_MASK), &file->tx_reg);
+	writel(readl(&file->tx_reg) | IMPCAL_VTH(5) | CK60_PHSEL(4) |
+			TXVDD12(3) | TXDATA_BLOCK_EN , &file->tx_reg);
+	/* calibrate */
+	count = 10000;
+	while(((readl(&file->pll_reg) & PLL_READY)==0) && count--);
+	if (count <= 0)
+		printf("Calibrate timeout, UTMI_PLL:%x\n",
+				readl(&file->pll_reg));
+
+	/* toggle VCOCAL_START bit of UTMI_PLL */
+	udelay(200);
+	reg = readl(&file->pll_reg);
+	writel(reg | VCOCAL_START, &file->pll_reg);
+	udelay(40);
+	writel(reg & (~VCOCAL_START), &file->pll_reg);
+
+	/* toggle REG_RCAL_START bit of UTMI_TX */
+	udelay(200);
+	reg = readl(&file->tx_reg);
+	writel(reg | REG_RCAL_START, &file->tx_reg);
+	udelay(40);
+	writel(reg & (~REG_RCAL_START), &file->tx_reg);
+	udelay(200);
+
+	/* make sure phy is ready */
+	count = 1000;
+	while(((readl(&file->pll_reg) & PLL_READY)==0) && count--);
+	if (count <= 0)
+		printf("Calibrate timeout, UTMI_PLL %x\n",
+				readl(&file->pll_reg));
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
+
+/*
+ * Reset the cpu by set max8925 pmic register
+ */
+#define RESET_CNFG		0x0f
+#define nBBPMUEN_DST		(1 << 2)
+#define RSTIN_DLY		(1 << 4)
+#define SFT_RST			(1 << 5)
+void reset_cpu(ulong ignored)
+{
+	u8 data;
+	data = nBBPMUEN_DST | RSTIN_DLY | SFT_RST;
+	i2c_set_bus_num(0);
+	i2c_write(MAX8925_SLAVE_ADDR, RESET_CNFG, 1, &data, 1);
+	while (1)
+		;
+}
+
+#ifdef CONFIG_MV_RECOVERY
+inline int magic_key_detect_recovery(void)
+{
+	/* If Volumn down key is pressed, go recovery flow */
+	if (!gpio_get_value(RECOVERY_KEY))
+		return 1;
+	else
+		return 0;
+}
+#endif
+
+void arch_preboot_os(void)
+{
+#if defined(CONFIG_PXA168_FB)
+	turn_off_backlight();
+#endif
+}
+
diff --git a/board/Marvell/brownstone/plat_ver.c b/board/Marvell/brownstone/plat_ver.c
new file mode 100644
index 0000000000..fd9003b6b6
--- /dev/null
+++ b/board/Marvell/brownstone/plat_ver.c
@@ -0,0 +1,57 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ */
+
+#include <asm/gpio.h>
+#include <asm/mach-types.h>
+
+#define GPIO125		125
+#define GPIO126		126
+#define GPIO127		127
+#define GPIO128		128
+
+static inline int mmp2_get_bs_vers(void)
+{
+	int vers = 0;
+	int vers0 = !!gpio_get_value(GPIO125);
+	int vers1 = !!gpio_get_value(GPIO126);
+	int vers2 = !!gpio_get_value(GPIO127);
+	int vers3 = !!gpio_get_value(GPIO128);
+
+	if (!machine_is_brownstone()) {
+		return 0;
+	}
+
+	vers = (vers3 << 3) | (vers2 << 2) |
+			(vers1 << 1) | (vers0 << 0);
+	return vers;
+}
+
+inline int board_is_mmp2_brownstone_rev1(void)
+{
+	return (0x9 == mmp2_get_bs_vers());
+}
+
+inline int board_is_mmp2_brownstone_rev2(void)
+{
+	return (0x7 == mmp2_get_bs_vers());
+}
+
+inline int board_is_mmp2_brownstone_rev4(void)
+{
+	return (0x3 == mmp2_get_bs_vers());
+}
+
+inline int board_is_mmp2_brownstone_rev5(void)
+{
+	return (0xe == mmp2_get_bs_vers());
+}
+
diff --git a/board/Marvell/brownstone/plat_ver.h b/board/Marvell/brownstone/plat_ver.h
new file mode 100644
index 0000000000..49b64c3279
--- /dev/null
+++ b/board/Marvell/brownstone/plat_ver.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_ARCH_MMP2_PLAT_VER_H
+#define __ASM_ARCH_MMP2_PLAT_VER_H
+inline int board_is_mmp2_brownstone_rev5(void);
+inline int board_is_mmp2_brownstone_rev4(void);
+inline int board_is_mmp2_brownstone_rev2(void);
+#endif
diff --git a/board/Marvell/common/marvell.h b/board/Marvell/common/marvell.h
new file mode 100644
index 0000000000..80ce5d8f4e
--- /dev/null
+++ b/board/Marvell/common/marvell.h
@@ -0,0 +1,639 @@
+const unsigned char MARVELL[] = {
+ 0x1f, 0x8b, 0x08, 0x08, 0xbf, 0x0d, 0xa1, 0x4e, 0x00, 0x03, 0x32, 0x32,
+ 0x32, 0x32, 0x32, 0x32, 0x2e, 0x62, 0x6d, 0x70, 0x00, 0xec, 0x5d, 0x09,
+ 0x70, 0x54, 0xd5, 0xb6, 0x45, 0x06, 0x45, 0x70, 0x40, 0xc5, 0x2a, 0x29,
+ 0x5f, 0x7d, 0xcb, 0xa1, 0x28, 0x85, 0x24, 0xdd, 0x21, 0xcc, 0x10, 0x02,
+ 0x61, 0x34, 0x3c, 0xbf, 0xd6, 0x53, 0x94, 0x67, 0x7a, 0x0a, 0x91, 0x29,
+ 0x21, 0x88, 0x22, 0xfa, 0x04, 0x31, 0x0c, 0x3e, 0x14, 0x25, 0xcc, 0x18,
+ 0x06, 0x07, 0x54, 0x10, 0x82, 0x20, 0x22, 0x84, 0x04, 0x12, 0x04, 0x44,
+ 0x19, 0x14, 0x01, 0x41, 0xc3, 0x64, 0x88, 0x02, 0x09, 0x43, 0xd2, 0xc3,
+ 0x9d, 0xe7, 0xf6, 0xaf, 0xdb, 0x97, 0xb4, 0x31, 0x60, 0xfa, 0x76, 0xa7,
+ 0x07, 0xac, 0x7f, 0x57, 0x9d, 0x0e, 0xa9, 0xa6, 0x7b, 0xdf, 0xb3, 0xcf,
+ 0x59, 0x67, 0xed, 0xbd, 0xcf, 0xb9, 0xdd, 0x49, 0x7d, 0xac, 0xb8, 0xfb,
+ 0x0d, 0x4d, 0x54, 0x74, 0xc5, 0xe3, 0x61, 0x3c, 0x7e, 0xc6, 0x63, 0x2a,
+ 0x1e, 0x37, 0x34, 0xb9, 0xc7, 0xf7, 0xfc, 0x0c, 0xfc, 0xff, 0x9d, 0xad,
+ 0x9b, 0xf8, 0x1e, 0xb5, 0xf8, 0xdd, 0x80, 0x81, 0x18, 0xa1, 0xfd, 0x03,
+ 0xff, 0x63, 0xf0, 0xcf, 0x40, 0xcc, 0xd0, 0xd5, 0x1c, 0x67, 0xf0, 0xcf,
+ 0x40, 0xcc, 0xd0, 0xa7, 0x6b, 0xa2, 0xc1, 0x3f, 0x03, 0x31, 0x43, 0xff,
+ 0x1e, 0x5d, 0x0c, 0xfe, 0x19, 0x88, 0x19, 0x06, 0xf7, 0xec, 0x6a, 0xf0,
+ 0xcf, 0x40, 0xcc, 0x30, 0xa4, 0xa7, 0xa1, 0x7f, 0x06, 0x62, 0x87, 0xc1,
+ 0x06, 0xff, 0x0c, 0xc4, 0x10, 0x83, 0x8d, 0xfc, 0xcf, 0x40, 0x0c, 0x31,
+ 0xa8, 0x47, 0x67, 0x83, 0x7f, 0x06, 0x62, 0x86, 0x81, 0x3d, 0x92, 0x02,
+ 0xf0, 0x4f, 0x51, 0x14, 0xd9, 0x2b, 0xed, 0xf8, 0x8e, 0x5b, 0x57, 0xc2,
+ 0xa3, 0x55, 0x5c, 0x94, 0x14, 0x45, 0xc2, 0x53, 0x2e, 0x5a, 0x58, 0xbf,
+ 0x53, 0x58, 0x5f, 0xca, 0xfc, 0x50, 0xc6, 0x09, 0x12, 0x9e, 0x51, 0x64,
+ 0x59, 0xde, 0x7d, 0x84, 0x2d, 0x28, 0xe1, 0xd1, 0xca, 0x2a, 0x44, 0x45,
+ 0x16, 0x64, 0x45, 0x69, 0xd8, 0xb8, 0xac, 0x48, 0xbc, 0xac, 0x7c, 0x7f,
+ 0x9c, 0x5d, 0x57, 0xc2, 0x14, 0x94, 0x88, 0x5b, 0xf6, 0x70, 0x34, 0x0b,
+ 0x5b, 0x92, 0xd7, 0xeb, 0xbd, 0x72, 0x75, 0xaf, 0x7c, 0xa9, 0x46, 0x58,
+ 0x5d, 0x22, 0xae, 0xdf, 0xc1, 0x6e, 0x28, 0x65, 0x8f, 0x9f, 0xe3, 0x45,
+ 0x29, 0x80, 0x4d, 0x3f, 0xce, 0x5d, 0x12, 0xd6, 0xed, 0xa0, 0xd7, 0x97,
+ 0xd0, 0x1b, 0x76, 0x73, 0x04, 0x2d, 0xc8, 0xe8, 0xa1, 0x57, 0xfd, 0xf1,
+ 0xdd, 0x31, 0x6e, 0xed, 0x0e, 0x5a, 0x75, 0x67, 0x17, 0x5b, 0xed, 0x91,
+ 0x75, 0x5a, 0xab, 0x07, 0x51, 0x96, 0x0b, 0xf7, 0x72, 0xeb, 0x4b, 0x98,
+ 0x3d, 0x87, 0x59, 0x38, 0x2f, 0x7b, 0xf5, 0xf6, 0xaa, 0x2e, 0x38, 0xc1,
+ 0xbb, 0x61, 0x27, 0xb7, 0xb6, 0x94, 0x5d, 0x5b, 0xca, 0x17, 0x94, 0x0a,
+ 0x7f, 0xb4, 0x12, 0x01, 0x03, 0xf2, 0xe5, 0xd7, 0x82, 0x20, 0x79, 0x83,
+ 0x32, 0xf8, 0xd3, 0xaf, 0xc2, 0x17, 0xa5, 0x0c, 0x0c, 0xd6, 0xb5, 0x86,
+ 0x41, 0xd8, 0x73, 0x44, 0x80, 0xef, 0xba, 0x4c, 0x28, 0x0a, 0x2b, 0x4b,
+ 0xbb, 0x0e, 0xfd, 0xc9, 0x02, 0xda, 0xda, 0x12, 0x7e, 0x6d, 0x09, 0x87,
+ 0x9f, 0xa7, 0xcf, 0xa2, 0x53, 0x70, 0x37, 0x14, 0x7f, 0xaf, 0xc6, 0x80,
+ 0xee, 0x9d, 0x02, 0xf0, 0x0f, 0x6c, 0x10, 0x15, 0x69, 0xf8, 0x34, 0xce,
+ 0xe4, 0x20, 0x4d, 0x76, 0xb2, 0x78, 0x3f, 0xa7, 0xc8, 0x2a, 0x05, 0xbf,
+ 0xfd, 0x91, 0x4f, 0x1c, 0x45, 0x77, 0xb0, 0x91, 0xff, 0x7c, 0x89, 0x63,
+ 0xc0, 0x0a, 0x50, 0x49, 0x92, 0x46, 0xbf, 0x43, 0x27, 0x38, 0x48, 0xb4,
+ 0x0f, 0x0b, 0x59, 0xd0, 0x51, 0x92, 0x03, 0xf8, 0x0c, 0x3b, 0xb2, 0x24,
+ 0x16, 0xee, 0x17, 0x4d, 0x0e, 0x36, 0xd1, 0x41, 0x76, 0x19, 0x45, 0x1d,
+ 0x3e, 0x2e, 0x71, 0x32, 0xe7, 0xad, 0x9d, 0x4e, 0x4c, 0xf3, 0x27, 0xc5,
+ 0x4c, 0x9c, 0x9d, 0x4c, 0xb0, 0x51, 0xa6, 0x4c, 0xfa, 0xd0, 0x49, 0x5e,
+ 0x92, 0x38, 0x9d, 0xbe, 0xed, 0x3c, 0xc8, 0x3d, 0x92, 0x41, 0xc7, 0xdb,
+ 0xe8, 0x94, 0x71, 0x74, 0x65, 0x35, 0x2f, 0xcb, 0x02, 0xac, 0x5d, 0x76,
+ 0x8b, 0x8f, 0xbd, 0xcc, 0x26, 0xda, 0x99, 0x04, 0x3b, 0xe1, 0x98, 0xc9,
+ 0x78, 0x28, 0x52, 0xa7, 0xb5, 0x7a, 0x38, 0xf1, 0x9b, 0xd8, 0x25, 0x93,
+ 0xea, 0x60, 0xa5, 0xfa, 0x3f, 0xcf, 0x52, 0xb4, 0xa0, 0x84, 0xc4, 0x3f,
+ 0x27, 0xe1, 0xed, 0x9d, 0x45, 0x9a, 0x6d, 0x74, 0x82, 0x9d, 0xd4, 0xc6,
+ 0x4d, 0x6b, 0xf1, 0x76, 0xca, 0xec, 0xf0, 0x3c, 0xfa, 0x02, 0x4d, 0xb1,
+ 0xc1, 0xf1, 0xef, 0xfd, 0x2d, 0x98, 0x26, 0x26, 0xde, 0xf1, 0x27, 0x6b,
+ 0x26, 0x2b, 0xf5, 0x6a, 0x3e, 0xa7, 0xe8, 0x63, 0x0c, 0x5e, 0x06, 0x39,
+ 0xc9, 0xca, 0x13, 0x12, 0xfe, 0x6c, 0xc4, 0xd7, 0x2b, 0x02, 0x3f, 0x57,
+ 0x15, 0x31, 0xa2, 0x24, 0x06, 0x54, 0x16, 0x9d, 0x08, 0xcc, 0x3f, 0x51,
+ 0x06, 0xb7, 0x24, 0xdb, 0x74, 0xa1, 0x93, 0x8d, 0x48, 0xb4, 0x12, 0xdb,
+ 0x0f, 0x88, 0x2a, 0xff, 0x24, 0x79, 0xc9, 0xe7, 0x7c, 0x17, 0x2b, 0x15,
+ 0x67, 0x73, 0x26, 0xda, 0x3c, 0x07, 0x8f, 0xf3, 0xa0, 0x9a, 0xa0, 0x48,
+ 0x39, 0x79, 0x8c, 0xc9, 0x46, 0x98, 0x6d, 0xc4, 0x87, 0x5b, 0x39, 0x59,
+ 0x11, 0x02, 0xf2, 0x0f, 0x7a, 0x04, 0xeb, 0x0c, 0x23, 0x0c, 0x9b, 0x4c,
+ 0x24, 0x58, 0x48, 0x93, 0x85, 0x9a, 0xbd, 0x9a, 0xc5, 0x53, 0xfe, 0xe9,
+ 0x94, 0x64, 0x31, 0x7d, 0x26, 0x9b, 0x68, 0xf5, 0xc4, 0x5b, 0x89, 0x8c,
+ 0x37, 0x49, 0x9a, 0x87, 0xd4, 0x8a, 0x3a, 0x7d, 0xdb, 0x7d, 0x90, 0x05,
+ 0xc9, 0xcc, 0x56, 0x77, 0xdf, 0x6c, 0xbe, 0xaa, 0x46, 0xc0, 0x2a, 0xc2,
+ 0xd5, 0xd6, 0x7e, 0x45, 0x62, 0x6a, 0x4d, 0x16, 0x77, 0x92, 0x83, 0xd8,
+ 0x73, 0x44, 0x35, 0xa7, 0xd3, 0x5a, 0x3d, 0x4c, 0x5a, 0x48, 0xc7, 0xdb,
+ 0x3d, 0x66, 0x9b, 0x3b, 0xde, 0xe6, 0x79, 0x6f, 0x33, 0xaf, 0xe8, 0x54,
+ 0x97, 0x3f, 0x03, 0xfc, 0x4b, 0x1e, 0x43, 0x99, 0xd2, 0x29, 0x93, 0xcd,
+ 0x83, 0x71, 0xab, 0xdb, 0x12, 0x6c, 0x9e, 0xc1, 0xe3, 0x99, 0x60, 0xf9,
+ 0xf7, 0x61, 0x21, 0x67, 0x56, 0xdf, 0xeb, 0xfa, 0x93, 0x35, 0xab, 0x6b,
+ 0xf2, 0x32, 0x41, 0x2f, 0xff, 0x64, 0x85, 0x13, 0xe5, 0xec, 0x3c, 0xaa,
+ 0x5e, 0x7f, 0xb4, 0x06, 0xe3, 0x6b, 0xb6, 0xb3, 0x3c, 0xf4, 0x47, 0x09,
+ 0x71, 0xdc, 0xea, 0x61, 0x60, 0x40, 0xfe, 0x29, 0xd0, 0x22, 0xc5, 0x9b,
+ 0x3e, 0x03, 0xc4, 0xf2, 0x98, 0xed, 0x44, 0xf1, 0x01, 0x41, 0x52, 0x44,
+ 0x60, 0x78, 0x2e, 0x63, 0x7a, 0x96, 0x8c, 0xb3, 0x3b, 0xbb, 0xd9, 0x88,
+ 0xfc, 0x2f, 0xb0, 0xbc, 0xbc, 0xe8, 0xfa, 0xe8, 0x3c, 0x16, 0xaf, 0x41,
+ 0xfb, 0xa0, 0x90, 0xf3, 0x05, 0x6e, 0xbd, 0xab, 0xa4, 0x68, 0x9f, 0x90,
+ 0x98, 0x41, 0x24, 0x58, 0x3d, 0x7d, 0xb3, 0x3d, 0xc5, 0x07, 0xf8, 0x5d,
+ 0x87, 0xc5, 0xdd, 0x47, 0x24, 0xb4, 0xaf, 0x0e, 0x09, 0x9d, 0x1c, 0x44,
+ 0xbc, 0xbd, 0xa6, 0xf3, 0x08, 0xe2, 0xf0, 0x69, 0x46, 0x94, 0x25, 0xc9,
+ 0xab, 0x97, 0x7f, 0x7b, 0x0e, 0x49, 0x58, 0xb2, 0x26, 0xbb, 0xa7, 0x6f,
+ 0x16, 0x7b, 0xc1, 0xa9, 0x2a, 0xed, 0x05, 0xb7, 0x30, 0x28, 0x87, 0x8c,
+ 0xb3, 0x7a, 0x12, 0xed, 0xc4, 0x1b, 0x2b, 0xb1, 0x8e, 0x41, 0x3f, 0x41,
+ 0xa7, 0xb5, 0x2b, 0xa3, 0xa1, 0x28, 0xe8, 0xc3, 0x99, 0x4a, 0xb1, 0xe7,
+ 0x68, 0x32, 0xc1, 0xea, 0x46, 0xc3, 0x9a, 0x1c, 0x30, 0x9e, 0x70, 0x12,
+ 0x92, 0x3a, 0x29, 0x72, 0x70, 0xaa, 0xa0, 0xf2, 0x2f, 0x8b, 0x4a, 0xb0,
+ 0xc3, 0x0e, 0x95, 0xbb, 0x8c, 0xc9, 0x5d, 0xc1, 0x4d, 0x7b, 0x4f, 0x44,
+ 0xcb, 0x5d, 0x21, 0xbe, 0xfe, 0x1e, 0x97, 0xb7, 0x9a, 0x47, 0x80, 0x0e,
+ 0xca, 0xe0, 0xca, 0xad, 0x82, 0xc9, 0xee, 0x36, 0xd9, 0x5c, 0x29, 0xa3,
+ 0xa9, 0xa9, 0xef, 0xd3, 0x9a, 0xb5, 0xd7, 0x56, 0x08, 0x1b, 0x77, 0x32,
+ 0xb2, 0xbe, 0xbe, 0x79, 0x15, 0x2f, 0x2f, 0xc8, 0xd9, 0xf3, 0x58, 0x93,
+ 0x95, 0xec, 0x64, 0x75, 0xfd, 0x6b, 0x32, 0x93, 0x8b, 0xfe, 0xf8, 0xba,
+ 0xa4, 0x59, 0xdb, 0x7b, 0x94, 0x13, 0x25, 0x49, 0x6f, 0x34, 0x0f, 0x84,
+ 0x81, 0xdd, 0x03, 0xe6, 0x7f, 0xf5, 0xf9, 0xc7, 0x79, 0x65, 0xe5, 0xa7,
+ 0x0a, 0x31, 0xc1, 0x41, 0x25, 0xda, 0x9c, 0xa6, 0x74, 0x8f, 0xc9, 0xe1,
+ 0x1c, 0x31, 0xeb, 0x0a, 0xff, 0xc6, 0xcc, 0xe5, 0x42, 0xe3, 0x1f, 0xc2,
+ 0xe2, 0xe3, 0xaf, 0x30, 0x09, 0xe9, 0x64, 0xbc, 0xcd, 0x95, 0x94, 0xe9,
+ 0xea, 0x9c, 0x41, 0x74, 0xc9, 0x20, 0xd5, 0x96, 0x59, 0x93, 0x68, 0x75,
+ 0x9b, 0xac, 0xee, 0xe7, 0xde, 0xa4, 0x10, 0xd0, 0x91, 0x51, 0x7a, 0x75,
+ 0x2b, 0x56, 0x3d, 0xfe, 0x09, 0x92, 0x38, 0x77, 0x2d, 0x93, 0x60, 0x55,
+ 0xe5, 0x01, 0xa1, 0xed, 0xfc, 0x25, 0x49, 0x4d, 0x10, 0x82, 0xd4, 0x3f,
+ 0xb8, 0x29, 0x2a, 0xca, 0xda, 0xaf, 0x54, 0x37, 0x7d, 0xa2, 0xa5, 0x4a,
+ 0x60, 0xa2, 0x83, 0x2a, 0xfe, 0x8e, 0xf7, 0x2a, 0x62, 0xc8, 0xfc, 0xeb,
+ 0x92, 0xe1, 0xa2, 0x28, 0x99, 0x97, 0x90, 0xa4, 0x22, 0x24, 0x78, 0xd5,
+ 0x14, 0x58, 0x16, 0x39, 0xcc, 0xb2, 0x37, 0x34, 0xfe, 0x79, 0xac, 0xb9,
+ 0x82, 0x20, 0x8a, 0x9a, 0x35, 0x38, 0x0e, 0x6b, 0x3a, 0x33, 0x36, 0x3f,
+ 0xff, 0x12, 0x2d, 0xee, 0x78, 0xbb, 0x7b, 0x61, 0x01, 0xa5, 0x19, 0xf1,
+ 0x37, 0x58, 0x15, 0xbd, 0x41, 0x7b, 0xfa, 0x57, 0x08, 0x9a, 0x7f, 0xdb,
+ 0xf7, 0x8b, 0x82, 0xc8, 0xcf, 0x5a, 0xc9, 0x41, 0x8d, 0xe3, 0xec, 0xee,
+ 0x3e, 0x59, 0x08, 0x9a, 0x44, 0x8f, 0x91, 0xc4, 0x85, 0x6a, 0xa8, 0xb2,
+ 0x3c, 0x7a, 0x4e, 0x88, 0xfa, 0xc7, 0x8a, 0xe2, 0x5b, 0xab, 0x58, 0x93,
+ 0xc5, 0x03, 0x0a, 0xc2, 0x2c, 0xa6, 0x04, 0xbc, 0x41, 0x83, 0x22, 0x76,
+ 0xb4, 0xba, 0x3b, 0x59, 0xa9, 0x35, 0x3b, 0x58, 0x95, 0xe2, 0x5e, 0x4c,
+ 0x8c, 0x5e, 0x9b, 0x57, 0xf8, 0xa7, 0xc6, 0x5f, 0xa6, 0xb2, 0x46, 0xac,
+ 0xbc, 0xcc, 0xa5, 0x4d, 0xa4, 0xcc, 0x36, 0x17, 0x12, 0x89, 0x0f, 0x0a,
+ 0x69, 0x75, 0x11, 0x2b, 0x6a, 0xdd, 0xa4, 0xd3, 0x9a, 0x06, 0x78, 0x04,
+ 0xd1, 0xcc, 0x9c, 0x4d, 0x27, 0x60, 0xed, 0xd9, 0xc8, 0xff, 0x7d, 0x05,
+ 0xd9, 0x1b, 0x72, 0x03, 0xd7, 0x94, 0x77, 0x19, 0x4e, 0x61, 0x91, 0x99,
+ 0x04, 0x65, 0xed, 0x0f, 0xfe, 0x65, 0x12, 0x24, 0xa5, 0xca, 0x31, 0x26,
+ 0xd6, 0xd7, 0xd4, 0x85, 0xa1, 0x92, 0x26, 0x24, 0xfe, 0x99, 0xed, 0xee,
+ 0x7f, 0xbf, 0xae, 0xaa, 0x94, 0xa4, 0xa6, 0x4a, 0x6a, 0x61, 0xa8, 0xa8,
+ 0x25, 0x5d, 0x90, 0xfa, 0x67, 0x21, 0x90, 0x95, 0xce, 0x5b, 0xc3, 0x69,
+ 0x46, 0xfc, 0x0d, 0xd3, 0x0a, 0x01, 0xf2, 0x27, 0x48, 0xa0, 0x87, 0x5a,
+ 0x8c, 0xa0, 0x29, 0xea, 0xaf, 0xbe, 0x7f, 0x14, 0x9d, 0xb1, 0x1e, 0xe8,
+ 0xdf, 0x2d, 0xc8, 0xf8, 0xbb, 0xed, 0x80, 0xe8, 0x24, 0xf8, 0xa1, 0x13,
+ 0x99, 0x4e, 0x56, 0xa2, 0xb3, 0x83, 0x5c, 0xf1, 0x25, 0x65, 0xb2, 0x30,
+ 0x20, 0xca, 0xbc, 0x35, 0x34, 0xc6, 0x6b, 0xf4, 0x1c, 0x3a, 0x34, 0xfe,
+ 0x89, 0x12, 0x77, 0xba, 0x92, 0x35, 0x3b, 0xd4, 0xa0, 0xd6, 0x35, 0x83,
+ 0x28, 0xd8, 0x26, 0x7c, 0x75, 0x50, 0xf8, 0xea, 0x7b, 0x71, 0x52, 0x3e,
+ 0x66, 0xba, 0xba, 0xd3, 0x28, 0xa6, 0xca, 0xc9, 0xeb, 0x34, 0xe5, 0x47,
+ 0x2d, 0xff, 0x5c, 0xa6, 0x0c, 0x76, 0xe2, 0x3c, 0x6e, 0xc4, 0x4c, 0x26,
+ 0xde, 0xea, 0x06, 0xb9, 0x9f, 0x78, 0x89, 0xa9, 0x26, 0x79, 0x51, 0x41,
+ 0xce, 0x8a, 0xe1, 0x0c, 0x2e, 0xfe, 0x62, 0x7a, 0x7e, 0xfe, 0x15, 0xa9,
+ 0x30, 0x9d, 0x64, 0xa5, 0xbb, 0x67, 0xb8, 0x4e, 0x5c, 0xe4, 0xfb, 0x8d,
+ 0x27, 0xe3, 0xd3, 0x89, 0x5e, 0xcf, 0x11, 0xd5, 0x6e, 0x51, 0x0c, 0x92,
+ 0xcd, 0x7e, 0xfe, 0x75, 0xb5, 0x93, 0x33, 0xde, 0x23, 0xdf, 0xfe, 0x88,
+ 0xfb, 0xef, 0xc7, 0x14, 0xda, 0xac, 0x8f, 0xc8, 0xe9, 0x1f, 0x32, 0x65,
+ 0xe5, 0x42, 0xc8, 0xfc, 0x1b, 0x3e, 0x0d, 0x49, 0x74, 0x28, 0x12, 0x55,
+ 0x27, 0xfe, 0x22, 0xed, 0x21, 0x17, 0x14, 0x04, 0x18, 0x76, 0x4e, 0x52,
+ 0x55, 0x5b, 0x92, 0x59, 0x4a, 0x10, 0x2f, 0x38, 0x45, 0x12, 0xc9, 0xa3,
+ 0x80, 0x04, 0x5e, 0xef, 0x3a, 0x0c, 0x9a, 0x7f, 0x45, 0xfb, 0xf9, 0x83,
+ 0x27, 0xf9, 0x2e, 0x23, 0x3d, 0x71, 0x36, 0x62, 0xfc, 0x5c, 0xfa, 0xb7,
+ 0x4b, 0x52, 0xb7, 0xe7, 0xa0, 0x01, 0xee, 0x7e, 0xd9, 0x94, 0x93, 0x94,
+ 0xb2, 0xe6, 0x52, 0xa1, 0xf1, 0x4f, 0xf2, 0x2d, 0xf8, 0x29, 0x60, 0x9b,
+ 0xdd, 0x9d, 0x68, 0x23, 0xdf, 0xfb, 0x12, 0xc1, 0x87, 0x47, 0x96, 0x69,
+ 0x99, 0x46, 0x9a, 0xad, 0xe4, 0xfc, 0xf5, 0x8c, 0x14, 0x7c, 0xa1, 0x50,
+ 0xcb, 0x3f, 0x4f, 0x82, 0x85, 0x40, 0x6f, 0x51, 0xc1, 0xe0, 0x77, 0x94,
+ 0x32, 0xb8, 0xc4, 0xc0, 0x09, 0xe4, 0xa7, 0xc8, 0xa3, 0x05, 0x21, 0x58,
+ 0xfd, 0x43, 0xf4, 0x79, 0x61, 0x09, 0x05, 0x55, 0x46, 0x1c, 0xb7, 0xbe,
+ 0x41, 0x22, 0x7f, 0xfc, 0xcf, 0x52, 0x35, 0x02, 0xc0, 0xf8, 0xdb, 0x9f,
+ 0x92, 0x08, 0x4d, 0x41, 0x59, 0xf3, 0xf3, 0x0f, 0x22, 0x8d, 0xc4, 0x23,
+ 0x4e, 0xcd, 0x0d, 0x48, 0x5f, 0xf3, 0xa0, 0xb2, 0x2e, 0xdc, 0x4b, 0x5d,
+ 0xff, 0xfc, 0x43, 0x34, 0xfc, 0xa9, 0x9c, 0x9b, 0xb2, 0x8c, 0xb3, 0x4f,
+ 0x67, 0x47, 0xcf, 0xa6, 0x1d, 0x33, 0x98, 0x09, 0x8b, 0x98, 0x03, 0x65,
+ 0x7a, 0xf7, 0x28, 0x06, 0x04, 0x1b, 0x7f, 0x37, 0xef, 0x17, 0x97, 0x6f,
+ 0x42, 0x5d, 0xa9, 0xe6, 0x3d, 0xdf, 0x1f, 0x13, 0xc0, 0x91, 0x17, 0x17,
+ 0x8b, 0xe8, 0x6b, 0x9c, 0x8d, 0xda, 0x77, 0x8c, 0xcd, 0x0e, 0xb5, 0xfe,
+ 0x50, 0x7c, 0x80, 0x27, 0x49, 0xcf, 0x11, 0x9d, 0x6c, 0x9e, 0xb4, 0x09,
+ 0x2c, 0xc9, 0x8a, 0x87, 0xca, 0x58, 0x93, 0x9d, 0xea, 0x97, 0xe3, 0x81,
+ 0x5a, 0x05, 0x9b, 0xa8, 0xfd, 0x5e, 0xcb, 0x3f, 0x94, 0x6c, 0x08, 0xeb,
+ 0x66, 0x1b, 0x0a, 0x3a, 0x26, 0xde, 0x46, 0x77, 0xb4, 0x53, 0x89, 0xd6,
+ 0x1a, 0xb3, 0x15, 0xb3, 0x4e, 0x17, 0x1f, 0xe6, 0x04, 0xdd, 0x75, 0x9c,
+ 0x1a, 0x56, 0x24, 0xe5, 0x4c, 0x95, 0x90, 0x92, 0x23, 0x80, 0x2b, 0x08,
+ 0xbb, 0x8b, 0xbf, 0x60, 0x10, 0x2f, 0x0b, 0xf7, 0xf1, 0x89, 0x16, 0xc6,
+ 0x6c, 0x25, 0x52, 0xc6, 0x33, 0x17, 0xaa, 0x43, 0xe4, 0x9f, 0xd9, 0xea,
+ 0x8a, 0x77, 0xb8, 0xe3, 0xd3, 0xdd, 0x5a, 0x4e, 0x89, 0x02, 0x02, 0x15,
+ 0x49, 0xe1, 0x37, 0xcc, 0x75, 0xcb, 0x3f, 0x49, 0xa5, 0x85, 0x1a, 0x6e,
+ 0xcf, 0x55, 0xb3, 0x43, 0x5e, 0x24, 0xe6, 0x17, 0x50, 0x4e, 0x8a, 0x63,
+ 0x45, 0x81, 0x62, 0xf9, 0x4d, 0xbb, 0xb9, 0xe4, 0x71, 0xec, 0xee, 0xc3,
+ 0x9c, 0x9a, 0x24, 0x06, 0x5a, 0xde, 0x83, 0x7a, 0x77, 0x0f, 0x32, 0xff,
+ 0xdb, 0xc7, 0x0f, 0x7f, 0x9d, 0x88, 0xb3, 0x78, 0x1e, 0x7f, 0x99, 0xaa,
+ 0xa1, 0x78, 0x28, 0xef, 0xcf, 0x15, 0x5c, 0x92, 0x03, 0x92, 0xe0, 0x5e,
+ 0xb2, 0x81, 0x1d, 0xf3, 0x4e, 0x88, 0xf5, 0x87, 0x2f, 0x7b, 0xf0, 0x52,
+ 0x8c, 0x82, 0x0b, 0xf9, 0x24, 0xca, 0xb3, 0xe9, 0x6b, 0x2e, 0x7b, 0x9e,
+ 0x1a, 0xd9, 0x5f, 0x5b, 0xc1, 0x6a, 0x5b, 0x77, 0x3a, 0x4d, 0xf9, 0xa1,
+ 0xf1, 0x0f, 0xa2, 0xd2, 0x67, 0x0c, 0xb1, 0xf7, 0x18, 0x77, 0xf2, 0x2c,
+ 0x7f, 0xac, 0x5c, 0xf8, 0x72, 0x0f, 0xfd, 0xe8, 0x04, 0x44, 0x79, 0x74,
+ 0xd2, 0xf5, 0xca, 0x22, 0x0e, 0x76, 0x75, 0x5a, 0x93, 0xd5, 0xfd, 0x4c,
+ 0xe1, 0xb3, 0x9d, 0x7c, 0xa2, 0x9d, 0x35, 0x21, 0xf9, 0xcb, 0xa0, 0x7f,
+ 0x3e, 0x23, 0x88, 0x8a, 0x50, 0xed, 0x16, 0x7a, 0x8f, 0xa3, 0x41, 0xf1,
+ 0x4e, 0x19, 0x9e, 0xc2, 0xbd, 0xc1, 0x45, 0x73, 0x3f, 0xff, 0x3a, 0x3b,
+ 0x3c, 0xcb, 0x0b, 0xf9, 0x4f, 0xb6, 0xb1, 0xab, 0xb6, 0x89, 0x68, 0x9f,
+ 0x14, 0xf3, 0x9f, 0x14, 0x89, 0xa7, 0xce, 0xf3, 0xd7, 0x2d, 0xff, 0x40,
+ 0x0a, 0xcc, 0x08, 0xc3, 0x49, 0x96, 0x37, 0xd8, 0xb9, 0x6b, 0xd8, 0xad,
+ 0xdf, 0xd2, 0x53, 0x96, 0x51, 0x82, 0xa0, 0x4c, 0x5b, 0xc1, 0xbd, 0x9a,
+ 0x4f, 0x7f, 0x54, 0xc8, 0x0e, 0xcf, 0xa5, 0x5d, 0x84, 0x10, 0xb0, 0x0f,
+ 0x69, 0xfd, 0x92, 0x83, 0xe3, 0xdf, 0x8a, 0x2f, 0xc1, 0x30, 0x4f, 0xbc,
+ 0xcd, 0xfd, 0xda, 0x52, 0x9e, 0x41, 0xbc, 0x01, 0x01, 0x45, 0xe5, 0xe9,
+ 0xa9, 0x1e, 0xa4, 0x83, 0xe9, 0xb9, 0x54, 0xf6, 0xbc, 0x10, 0xe3, 0xaf,
+ 0x36, 0xd0, 0xd0, 0x98, 0x75, 0x25, 0x5c, 0x07, 0x08, 0x80, 0x85, 0x7a,
+ 0xe2, 0x55, 0xaa, 0xe7, 0x48, 0x88, 0x96, 0x7b, 0xff, 0x8f, 0x82, 0xa4,
+ 0xee, 0x78, 0x87, 0xc8, 0x3f, 0xb3, 0x85, 0xe8, 0x3b, 0x9e, 0xad, 0xaa,
+ 0x46, 0x39, 0xa8, 0x16, 0xbc, 0x48, 0x4d, 0xa6, 0x7e, 0xc0, 0xa3, 0x04,
+ 0x86, 0x86, 0x8d, 0x9a, 0xc5, 0x12, 0x9c, 0x7e, 0xfe, 0x89, 0x82, 0xc4,
+ 0xdb, 0x67, 0xd2, 0x66, 0xab, 0xb3, 0xa3, 0x95, 0xca, 0x9c, 0x45, 0xa9,
+ 0x5b, 0x91, 0xb2, 0x3a, 0x02, 0xcb, 0x36, 0x60, 0x40, 0x48, 0xb3, 0xdd,
+ 0x39, 0x6e, 0xae, 0xaa, 0x58, 0x3e, 0xe8, 0xb2, 0xf9, 0x47, 0xfe, 0xe7,
+ 0xa0, 0x9d, 0x8c, 0xc8, 0x4b, 0x22, 0xf4, 0x18, 0x8d, 0x93, 0x25, 0x5e,
+ 0xcd, 0xa3, 0xae, 0xdf, 0xfc, 0x4f, 0xdd, 0x00, 0x94, 0x85, 0xef, 0xcb,
+ 0xb8, 0xa4, 0x4c, 0xfa, 0xd4, 0x6f, 0xfc, 0xc6, 0x5d, 0xe4, 0xc4, 0x85,
+ 0xa4, 0xdb, 0x2d, 0x0e, 0x9f, 0x49, 0xae, 0xdc, 0x08, 0x1d, 0x64, 0x1f,
+ 0xff, 0x0f, 0x75, 0xf0, 0xa4, 0x14, 0x70, 0x9b, 0x70, 0xe8, 0x80, 0xbe,
+ 0xc1, 0xf1, 0x2f, 0xed, 0x05, 0x0f, 0xb2, 0x13, 0x93, 0x83, 0x2c, 0xfe,
+ 0x0e, 0x39, 0x19, 0x2a, 0x2b, 0xe4, 0x50, 0x72, 0xde, 0x5a, 0x36, 0xce,
+ 0xe6, 0xea, 0xe2, 0xf0, 0x0c, 0x7e, 0x91, 0x08, 0x8d, 0x7f, 0xb5, 0xd7,
+ 0x52, 0x5c, 0xb4, 0x90, 0xf6, 0x12, 0x05, 0xd9, 0xd3, 0xec, 0x60, 0x6e,
+ 0x68, 0x3e, 0xc4, 0x52, 0x5f, 0xe3, 0x5f, 0x82, 0xcd, 0xdd, 0x27, 0x87,
+ 0xaa, 0xaa, 0x01, 0xf1, 0x54, 0x1e, 0x5f, 0x74, 0x0b, 0xb6, 0x19, 0xb4,
+ 0x16, 0xe3, 0x46, 0xbf, 0xc3, 0x52, 0xbc, 0xde, 0x88, 0x89, 0xac, 0xfa,
+ 0xc7, 0x32, 0x31, 0xd1, 0x41, 0x99, 0xad, 0x6a, 0xdf, 0xbe, 0x3e, 0x0a,
+ 0xed, 0x17, 0x20, 0xcc, 0x20, 0xe1, 0x59, 0xa7, 0x90, 0x32, 0x96, 0x8a,
+ 0xb7, 0xd6, 0x74, 0xcb, 0xa4, 0x7f, 0xfa, 0x15, 0x2a, 0xc0, 0xc3, 0x73,
+ 0x3d, 0x36, 0xfd, 0xfc, 0xeb, 0xe1, 0x20, 0x2e, 0xb8, 0x39, 0x86, 0x91,
+ 0x58, 0x5e, 0x56, 0x1b, 0x27, 0xb1, 0x9c, 0x4c, 0x73, 0xd2, 0x75, 0xcc,
+ 0x3f, 0xb0, 0x42, 0xde, 0xf2, 0xad, 0xd8, 0x6d, 0x24, 0xe5, 0xa2, 0x84,
+ 0x4d, 0x7b, 0xe8, 0xbe, 0x39, 0xd4, 0x73, 0x33, 0xd9, 0xfe, 0xcf, 0xd3,
+ 0xbf, 0x9c, 0xe3, 0x10, 0x2a, 0xb2, 0xe7, 0xd3, 0x45, 0xfb, 0x03, 0x6f,
+ 0x7a, 0xa7, 0x0d, 0x4c, 0xd5, 0xc5, 0x3f, 0xcb, 0x0c, 0x46, 0xdb, 0xf1,
+ 0x52, 0x67, 0xd4, 0xea, 0x4e, 0x19, 0xcd, 0x78, 0x58, 0x9f, 0xa0, 0x28,
+ 0xaa, 0x00, 0xee, 0xfd, 0x89, 0x37, 0xd9, 0x91, 0xb2, 0x10, 0x71, 0xcf,
+ 0x86, 0xa8, 0x7f, 0x57, 0x9c, 0xf7, 0xc9, 0xfa, 0xca, 0xad, 0xbc, 0x66,
+ 0x04, 0x2d, 0xc9, 0x46, 0xeb, 0xdc, 0x38, 0xbd, 0x1a, 0xfe, 0xfc, 0xaf,
+ 0xb3, 0x9d, 0x1a, 0x97, 0xc7, 0x3c, 0x3f, 0x4f, 0x18, 0x3d, 0x47, 0xe8,
+ 0x9f, 0xed, 0x44, 0xe6, 0x6a, 0xb6, 0xd2, 0x89, 0x36, 0x2a, 0xff, 0x73,
+ 0x3e, 0xe0, 0x09, 0x8d, 0x1f, 0xac, 0xc4, 0x4d, 0x5c, 0x44, 0x23, 0x9a,
+ 0x9b, 0x6d, 0xce, 0xc7, 0x5f, 0xa1, 0x18, 0x56, 0x90, 0x7d, 0xf9, 0x0d,
+ 0x78, 0x29, 0x08, 0x7c, 0xce, 0x1c, 0x2e, 0xd1, 0x4a, 0x41, 0x53, 0x27,
+ 0x2d, 0x61, 0x55, 0x9a, 0xeb, 0x2b, 0x44, 0xfc, 0xfc, 0x7b, 0xc4, 0x42,
+ 0x26, 0x65, 0xd6, 0x98, 0x32, 0xc0, 0x6c, 0x0c, 0x20, 0x9e, 0xf1, 0x24,
+ 0xda, 0x5d, 0xaf, 0xe6, 0xb3, 0x92, 0x3e, 0x1e, 0xfb, 0x11, 0x3d, 0xfe,
+ 0x79, 0xd5, 0x5d, 0x9d, 0x92, 0xfd, 0x7c, 0xf7, 0x4c, 0xf2, 0xa2, 0x53,
+ 0xf9, 0xe2, 0x5b, 0x76, 0xc2, 0x62, 0x9a, 0x25, 0xe5, 0xb1, 0xf3, 0xe8,
+ 0xa9, 0xcb, 0x38, 0x5e, 0x90, 0x32, 0x66, 0x31, 0xbb, 0x7e, 0x10, 0x02,
+ 0x1e, 0x0b, 0xa5, 0x0d, 0xea, 0x1f, 0x88, 0x7f, 0x08, 0x5a, 0x92, 0x60,
+ 0x99, 0x81, 0xc2, 0xc2, 0xb7, 0xdd, 0xaa, 0x16, 0x6b, 0x44, 0xde, 0x5a,
+ 0xba, 0x76, 0xa7, 0x07, 0x9c, 0x91, 0x29, 0x4e, 0x19, 0x32, 0x81, 0x8c,
+ 0xb3, 0xb9, 0xe3, 0xac, 0x70, 0x5e, 0x95, 0x87, 0xf7, 0xb7, 0x70, 0xb2,
+ 0xc2, 0x07, 0x7b, 0x4a, 0x08, 0x5b, 0x28, 0x48, 0x4f, 0x9f, 0xe5, 0xfa,
+ 0x8e, 0x03, 0xf9, 0xdc, 0x09, 0x56, 0xd7, 0xb0, 0x5c, 0x2a, 0xb4, 0x71,
+ 0x04, 0x76, 0x1f, 0x12, 0x12, 0xec, 0x94, 0xb6, 0x30, 0xd4, 0xa6, 0xa6,
+ 0xf9, 0x6a, 0xdf, 0xb0, 0x7e, 0xcc, 0x0e, 0x72, 0xe4, 0x6c, 0xfa, 0xb2,
+ 0x1b, 0xea, 0xa5, 0x97, 0x7f, 0xbf, 0x55, 0x89, 0xc9, 0xcf, 0x43, 0xfc,
+ 0x9c, 0x66, 0x8b, 0x67, 0xc6, 0x87, 0xb4, 0x24, 0xab, 0x0b, 0x53, 0xdd,
+ 0x58, 0x53, 0xf7, 0xc3, 0xbc, 0x9f, 0xed, 0x60, 0x3b, 0x58, 0x69, 0x54,
+ 0x4e, 0x83, 0xb3, 0xe9, 0x8a, 0x2a, 0x9e, 0xd7, 0x77, 0xac, 0xe2, 0x24,
+ 0x94, 0xe4, 0xd1, 0xa8, 0x8a, 0xaa, 0x13, 0xb1, 0xb0, 0xd5, 0x43, 0x33,
+ 0x75, 0xe3, 0x13, 0x2d, 0xde, 0xea, 0x4a, 0xb4, 0xba, 0x5f, 0x79, 0x97,
+ 0x91, 0x83, 0xe4, 0xdf, 0x07, 0x5b, 0x39, 0xf8, 0x18, 0x6f, 0x77, 0xa7,
+ 0xe7, 0x82, 0x45, 0xa1, 0x1c, 0x91, 0xc1, 0x21, 0x08, 0x30, 0x12, 0x09,
+ 0x54, 0x54, 0x1d, 0xed, 0x9e, 0x45, 0x05, 0xf4, 0x35, 0x5f, 0xa6, 0xce,
+ 0xba, 0x2c, 0x9f, 0xbf, 0x24, 0x74, 0x1b, 0x43, 0x95, 0x1e, 0xe0, 0x36,
+ 0xee, 0x14, 0x86, 0xbd, 0x4e, 0x2d, 0xdf, 0x2c, 0xfd, 0xf3, 0x25, 0x06,
+ 0xe9, 0xe0, 0xb1, 0x72, 0x6e, 0xc8, 0x44, 0xe6, 0xd7, 0x2a, 0x31, 0xa0,
+ 0xfe, 0x0d, 0x1d, 0x3c, 0x20, 0xd0, 0xf9, 0xaf, 0xa2, 0x86, 0xd9, 0x31,
+ 0x6f, 0xb3, 0x7d, 0xb3, 0x19, 0xb4, 0xe4, 0x6c, 0xbe, 0xff, 0x0b, 0xee,
+ 0x13, 0xe7, 0xea, 0xaf, 0xef, 0x8f, 0xb6, 0xb9, 0x53, 0xc6, 0xd1, 0xbd,
+ 0xb3, 0xae, 0xbc, 0x6c, 0x4d, 0x31, 0xa7, 0x6d, 0x58, 0xea, 0xf7, 0xdc,
+ 0xe7, 0x95, 0x82, 0xec, 0x47, 0x94, 0x84, 0x29, 0xef, 0x92, 0x7d, 0xc6,
+ 0x82, 0x85, 0xec, 0xf2, 0x8d, 0x6c, 0x68, 0x47, 0xab, 0xc0, 0xb7, 0x3f,
+ 0xb2, 0x5d, 0xb3, 0x59, 0xf4, 0x4a, 0xeb, 0x52, 0xdf, 0x6c, 0xb6, 0xdf,
+ 0x38, 0x6a, 0xc0, 0x78, 0xea, 0x89, 0x49, 0x6c, 0xfe, 0x06, 0x92, 0x64,
+ 0x78, 0x68, 0x97, 0xa4, 0xbb, 0xfe, 0x2d, 0x3a, 0xc0, 0xf6, 0x1d, 0x4b,
+ 0xa6, 0x66, 0xf3, 0x3d, 0xc6, 0xb2, 0xfb, 0x8f, 0xb2, 0xf5, 0x22, 0x63,
+ 0x95, 0x93, 0x1f, 0x9c, 0xc3, 0xf5, 0x1c, 0xe7, 0xe9, 0x95, 0x43, 0x17,
+ 0xee, 0x83, 0xef, 0xba, 0xf8, 0xe7, 0x22, 0xbd, 0x43, 0x27, 0x09, 0x7d,
+ 0x73, 0xc8, 0x94, 0x2c, 0xa6, 0xb6, 0x93, 0x6a, 0xeb, 0x97, 0xcd, 0xa4,
+ 0x64, 0xf1, 0xaf, 0x7f, 0x40, 0x07, 0xab, 0x7f, 0xab, 0x4a, 0xd9, 0xe4,
+ 0x2c, 0x36, 0x79, 0x1c, 0x33, 0xe6, 0x6d, 0x81, 0xd7, 0x7d, 0x50, 0x5e,
+ 0x17, 0x98, 0x6e, 0x56, 0x50, 0x5e, 0x5e, 0x22, 0xf4, 0xc1, 0x6c, 0x8e,
+ 0xe5, 0x96, 0x6d, 0x64, 0xae, 0xfd, 0x3a, 0x2f, 0x26, 0x4b, 0x96, 0xbc,
+ 0xf2, 0xc7, 0x85, 0xdc, 0xf0, 0x5c, 0x6e, 0x7f, 0x19, 0xfb, 0xee, 0x06,
+ 0x66, 0x7e, 0x01, 0x51, 0xb4, 0x97, 0x3f, 0x77, 0x89, 0xb3, 0xcd, 0xe4,
+ 0xa7, 0x2f, 0x67, 0x18, 0x51, 0x3d, 0xb2, 0x6a, 0xf8, 0x72, 0xba, 0xf8,
+ 0x87, 0x14, 0xfb, 0x6c, 0xb5, 0xf0, 0xcb, 0x05, 0x11, 0xed, 0x4c, 0x25,
+ 0xff, 0x6b, 0x25, 0xcf, 0x71, 0xf5, 0x65, 0xd9, 0xc3, 0x08, 0xe5, 0xe7,
+ 0xf8, 0x5f, 0xd0, 0x2e, 0x88, 0xe5, 0x17, 0x24, 0x27, 0x29, 0x7a, 0xd5,
+ 0xdb, 0x5f, 0x82, 0xe5, 0x9f, 0x7a, 0x43, 0x02, 0x5a, 0xb5, 0x47, 0x3c,
+ 0x5d, 0x25, 0x9e, 0xae, 0x14, 0x5c, 0xb4, 0x18, 0x32, 0xff, 0x08, 0x5a,
+ 0x38, 0x75, 0x5e, 0xf8, 0xa5, 0x52, 0xd4, 0x7a, 0xfe, 0x4b, 0x95, 0x78,
+ 0xe6, 0x82, 0x74, 0xf6, 0xb2, 0xec, 0x61, 0xd5, 0x9c, 0x55, 0x3d, 0xff,
+ 0xf0, 0x1d, 0xc0, 0xe9, 0xb4, 0x76, 0xd1, 0xcd, 0xab, 0xa6, 0xaa, 0x84,
+ 0x8a, 0xf3, 0x22, 0x02, 0x4c, 0x3d, 0xfe, 0x61, 0x8c, 0xce, 0x5e, 0xe4,
+ 0x2b, 0xce, 0xf3, 0xa7, 0x2a, 0xc5, 0x1a, 0x0f, 0x06, 0x4c, 0xd7, 0xdc,
+ 0x83, 0x5e, 0xe5, 0x55, 0xc2, 0x99, 0x4a, 0x01, 0xce, 0x5e, 0xe9, 0xa4,
+ 0xd6, 0x2a, 0x05, 0x3c, 0x7f, 0xb1, 0x06, 0xfa, 0x11, 0x1c, 0xff, 0x9c,
+ 0x84, 0x58, 0x5e, 0xc9, 0x97, 0x9f, 0xe7, 0xce, 0x5d, 0x02, 0xfd, 0x82,
+ 0xde, 0xb1, 0xff, 0xdd, 0x17, 0xee, 0x58, 0x49, 0xac, 0xaa, 0x66, 0x61,
+ 0xe7, 0x74, 0x95, 0x84, 0x10, 0x71, 0xcd, 0x97, 0xa9, 0x25, 0x96, 0x2f,
+ 0x02, 0xf2, 0x9c, 0xb0, 0xf8, 0x73, 0xee, 0xb1, 0x49, 0xf4, 0x7f, 0x3f,
+ 0xe2, 0x3f, 0xde, 0xca, 0xce, 0x5d, 0xcd, 0xfc, 0x6b, 0x0a, 0xf7, 0xe6,
+ 0xc7, 0x5c, 0x0d, 0x81, 0xe4, 0x58, 0x0e, 0x78, 0x5b, 0x50, 0xe0, 0xf8,
+ 0x6b, 0xc0, 0x40, 0x03, 0x50, 0x0f, 0x31, 0x15, 0xf9, 0xe4, 0x6f, 0xec,
+ 0xec, 0xd5, 0xf4, 0xf3, 0x79, 0xec, 0xb4, 0x15, 0xdc, 0xbe, 0x9f, 0x19,
+ 0x5e, 0xf7, 0xae, 0x56, 0xda, 0x80, 0x40, 0xf5, 0x87, 0x01, 0x03, 0x0d,
+ 0xc0, 0x77, 0x53, 0xaf, 0xa2, 0x6d, 0x6c, 0xa9, 0xb7, 0xea, 0xf9, 0xa0,
+ 0xff, 0x1c, 0x72, 0x48, 0xff, 0x40, 0xfb, 0x2f, 0x06, 0x0c, 0x34, 0x00,
+ 0xb5, 0x10, 0xfe, 0x5d, 0xcd, 0x64, 0xbc, 0x3e, 0x22, 0x2a, 0xda, 0x5d,
+ 0x32, 0xba, 0xd3, 0x86, 0x21, 0xa9, 0x29, 0x06, 0xff, 0x0c, 0xc4, 0x0c,
+ 0x06, 0xff, 0x0c, 0xc4, 0x12, 0x8f, 0x06, 0x3c, 0xff, 0x30, 0x60, 0x20,
+ 0x72, 0x18, 0x3a, 0xc8, 0xa8, 0x3f, 0x0c, 0xc4, 0x0e, 0xc6, 0xfe, 0x8b,
+ 0x81, 0x58, 0x22, 0x6d, 0xb0, 0xc1, 0x3f, 0x03, 0xb1, 0xc3, 0xa3, 0x46,
+ 0xfc, 0x35, 0x10, 0x43, 0x0c, 0x19, 0xd8, 0xcf, 0xe0, 0x9f, 0x81, 0x98,
+ 0xc1, 0xa8, 0x7f, 0x0d, 0xc4, 0x12, 0x8f, 0x19, 0xf9, 0x9f, 0x81, 0x18,
+ 0xe2, 0xb1, 0x80, 0xf5, 0xaf, 0xec, 0x03, 0x45, 0x51, 0xae, 0x5a, 0xb8,
+ 0xa3, 0x08, 0x8f, 0xc7, 0xa3, 0xff, 0xc3, 0xa4, 0x01, 0x1d, 0xe1, 0x38,
+ 0x0e, 0xfd, 0x77, 0x3a, 0x9d, 0xd1, 0x77, 0x84, 0x61, 0xd4, 0x8f, 0xf0,
+ 0x05, 0xbc, 0x1f, 0xe9, 0xff, 0x1b, 0x86, 0xa6, 0xf6, 0xd1, 0xc5, 0xbf,
+ 0xc2, 0xc2, 0x42, 0x93, 0xc9, 0xf4, 0xc0, 0x03, 0x0f, 0xdc, 0x1f, 0x5d,
+ 0x74, 0xec, 0xd8, 0x31, 0x5c, 0xfc, 0xc3, 0xf4, 0x57, 0x54, 0x54, 0x0c,
+ 0x19, 0x32, 0xe4, 0x01, 0x1f, 0xa2, 0xec, 0x88, 0xc5, 0x62, 0xc1, 0x5a,
+ 0x32, 0xf8, 0x57, 0x0f, 0x83, 0x7a, 0x75, 0x0b, 0xc0, 0x3f, 0xf5, 0x9e,
+ 0x64, 0x49, 0x12, 0x45, 0xf1, 0xad, 0xb7, 0xde, 0x6a, 0xdd, 0xba, 0xce,
+ 0x9f, 0xad, 0x89, 0x0a, 0x6e, 0xb8, 0xe1, 0x86, 0x4f, 0x3f, 0xfd, 0x34,
+ 0x88, 0x8f, 0xf4, 0xfc, 0x35, 0xb4, 0x85, 0x54, 0x56, 0x56, 0xf6, 0xd0,
+ 0x43, 0x0f, 0xc1, 0x6c, 0x94, 0x1d, 0x01, 0x9e, 0x7a, 0xea, 0x29, 0x88,
+ 0x6e, 0x58, 0x7c, 0xa9, 0x07, 0xed, 0x6e, 0x64, 0x31, 0x2a, 0x50, 0x6f,
+ 0x35, 0x08, 0x9f, 0x0b, 0xa9, 0x5d, 0xcd, 0xba, 0xf2, 0x3f, 0x5c, 0x8f,
+ 0xe7, 0xf9, 0xfc, 0xfc, 0xfc, 0x5b, 0x6f, 0xbd, 0x35, 0xca, 0xd3, 0x76,
+ 0xd7, 0x5d, 0x77, 0x15, 0x14, 0x14, 0x84, 0x4b, 0x39, 0x60, 0xe7, 0x87,
+ 0x1f, 0x7e, 0x80, 0xac, 0x36, 0xf1, 0x91, 0x3b, 0x9a, 0x44, 0xc4, 0xb5,
+ 0x9e, 0x79, 0xe6, 0x19, 0x0c, 0x63, 0xd8, 0x55, 0x10, 0x21, 0x62, 0xc9,
+ 0x92, 0x25, 0xc3, 0x86, 0x0d, 0x7b, 0x2a, 0xf2, 0xd8, 0xbc, 0x79, 0xb3,
+ 0xf6, 0xa9, 0x8b, 0xb0, 0xf4, 0x3c, 0xb5, 0x8b, 0x6e, 0xfe, 0x61, 0xd4,
+ 0x30, 0x76, 0x31, 0x51, 0xc1, 0x66, 0xcd, 0x9a, 0xad, 0x59, 0xb3, 0x26,
+ 0x2c, 0x0e, 0x6b, 0x72, 0x7e, 0xe4, 0xc8, 0x91, 0xf6, 0xed, 0xdb, 0xc7,
+ 0x44, 0x05, 0x9f, 0x7c, 0xf2, 0xc9, 0x9a, 0x9a, 0x9a, 0xb0, 0xf8, 0xe2,
+ 0x07, 0xa6, 0x66, 0xc4, 0x88, 0x11, 0x4d, 0x6a, 0x57, 0x54, 0x44, 0x31,
+ 0x7f, 0xfe, 0x7c, 0xed, 0xcb, 0x02, 0xc2, 0xd2, 0xf3, 0xd4, 0xce, 0x09,
+ 0x7a, 0xf9, 0xa7, 0xdd, 0x71, 0x0d, 0x05, 0xc6, 0x52, 0x6b, 0xd9, 0xb2,
+ 0x65, 0x94, 0xa7, 0x2d, 0x5c, 0x2a, 0xe8, 0x77, 0xe4, 0xe8, 0xd1, 0xa3,
+ 0x1d, 0x3a, 0x74, 0xd0, 0x8c, 0x3f, 0xf2, 0xc8, 0x23, 0x7d, 0x22, 0x86,
+ 0xfb, 0xee, 0xbb, 0xaf, 0x9e, 0x2f, 0xcf, 0x3e, 0xfb, 0xac, 0x16, 0xc8,
+ 0xc2, 0x25, 0x84, 0x70, 0x47, 0xe3, 0xdf, 0x6d, 0xb7, 0xdd, 0x96, 0xec,
+ 0x43, 0xd8, 0xbd, 0xe8, 0xd6, 0xad, 0x5b, 0xd3, 0xa6, 0x4d, 0x63, 0xc6,
+ 0x3f, 0x3f, 0xd4, 0x2f, 0x41, 0x13, 0x84, 0xd9, 0xb3, 0x67, 0xdf, 0x7e,
+ 0xfb, 0xed, 0xe8, 0x50, 0x34, 0x29, 0x78, 0xd3, 0x4d, 0x37, 0x81, 0x82,
+ 0xe1, 0xf2, 0x1c, 0x2c, 0x2c, 0x2d, 0x2d, 0x6d, 0xd5, 0xaa, 0x15, 0x2c,
+ 0x6f, 0xd8, 0xb0, 0x41, 0x8b, 0x29, 0x61, 0x07, 0xcc, 0xe6, 0xe6, 0xe6,
+ 0x5e, 0xed, 0xcb, 0xd3, 0x4f, 0x3f, 0x5d, 0x5d, 0x5d, 0x1d, 0x46, 0xfe,
+ 0x65, 0x66, 0x66, 0xc2, 0x6c, 0xcf, 0x9e, 0x3d, 0x51, 0x68, 0xfb, 0x53,
+ 0xb4, 0x30, 0xe2, 0xcc, 0x99, 0x33, 0x2d, 0x5a, 0xb4, 0xc0, 0x25, 0xc0,
+ 0x3f, 0xed, 0x99, 0xb0, 0xf4, 0x3c, 0x14, 0xfe, 0x69, 0x1b, 0x19, 0x4b,
+ 0x97, 0x2e, 0xbd, 0xf9, 0xe6, 0x9b, 0xa3, 0xc9, 0x3f, 0x2c, 0x3e, 0xa8,
+ 0xe0, 0xfa, 0xf5, 0xeb, 0xc3, 0xe2, 0x39, 0xbc, 0x38, 0x74, 0xe8, 0xd0,
+ 0x9d, 0x77, 0xde, 0x09, 0xcb, 0x9f, 0x7d, 0xf6, 0x59, 0x94, 0xf9, 0x07,
+ 0x5f, 0xa0, 0x82, 0x21, 0x7c, 0xa9, 0xd2, 0x35, 0xe1, 0xe7, 0x5f, 0x8f,
+ 0x1e, 0x3d, 0x68, 0x9a, 0x8e, 0x84, 0x2f, 0xd7, 0x0b, 0xff, 0xfc, 0x00,
+ 0x05, 0xe7, 0xcc, 0x99, 0x03, 0xc1, 0xd7, 0x46, 0x33, 0x6a, 0x2c, 0x04,
+ 0xe9, 0xd7, 0xad, 0x5b, 0xa7, 0x2d, 0xf1, 0xc6, 0x78, 0x8e, 0xb7, 0xa3,
+ 0x10, 0x81, 0x8a, 0xc3, 0xe6, 0xe4, 0xc9, 0x93, 0x8b, 0x8a, 0x8a, 0xb6,
+ 0x46, 0x06, 0xe9, 0xe9, 0xe9, 0xd7, 0x1c, 0x1f, 0x3c, 0x69, 0xb1, 0x58,
+ 0x2e, 0x5f, 0xbe, 0xac, 0x7e, 0x4e, 0xac, 0x71, 0xa2, 0xee, 0xe7, 0x1f,
+ 0xea, 0xaa, 0x8d, 0x1b, 0x37, 0x46, 0xc2, 0x8b, 0x95, 0x2b, 0x57, 0x36,
+ 0x6f, 0xde, 0x5c, 0x8b, 0xbf, 0x61, 0xe4, 0x5f, 0xff, 0x90, 0xf9, 0xa7,
+ 0x15, 0xfc, 0xc8, 0x05, 0xa3, 0x1c, 0x85, 0x31, 0x04, 0x6d, 0xda, 0xb4,
+ 0x81, 0x62, 0x85, 0x91, 0x7f, 0x18, 0xd9, 0x9b, 0x22, 0x06, 0x14, 0x4f,
+ 0x7f, 0xc5, 0x3f, 0x0c, 0x1d, 0x54, 0xb0, 0xf1, 0x6b, 0xc9, 0xcf, 0x3f,
+ 0xd8, 0xbc, 0xf1, 0xc6, 0x1b, 0x23, 0xe1, 0x05, 0xcc, 0x6a, 0x5e, 0x5c,
+ 0x2f, 0xfc, 0xd3, 0x92, 0x50, 0xe4, 0x82, 0x50, 0xc1, 0x3b, 0xee, 0xb8,
+ 0x23, 0x9a, 0x14, 0x04, 0x40, 0x41, 0x24, 0x6d, 0x8d, 0x19, 0x08, 0x74,
+ 0x1e, 0xf1, 0xf7, 0xee, 0xbb, 0xef, 0xae, 0x3b, 0xc4, 0x91, 0xe8, 0x6a,
+ 0xc0, 0xe0, 0x00, 0x81, 0x44, 0x45, 0xdc, 0x98, 0xa4, 0x1e, 0x6f, 0x1c,
+ 0x35, 0x6a, 0x14, 0x8a, 0xc2, 0x48, 0x30, 0xaf, 0x1e, 0x16, 0x2d, 0x5a,
+ 0x14, 0xc6, 0xfa, 0x63, 0x40, 0xc8, 0xfc, 0xf3, 0x7b, 0xae, 0xa9, 0xe0,
+ 0x5f, 0xad, 0xf2, 0xc8, 0xa1, 0x75, 0xeb, 0xd6, 0x9b, 0x36, 0x6d, 0x0a,
+ 0x39, 0x85, 0x07, 0x71, 0x91, 0x2a, 0x21, 0xad, 0x29, 0xaf, 0xc5, 0xc9,
+ 0x93, 0x27, 0xdb, 0xb7, 0x6f, 0x1f, 0x4d, 0x17, 0x34, 0x40, 0x05, 0x11,
+ 0x88, 0xd5, 0xaf, 0xcb, 0x09, 0xd5, 0x17, 0xbc, 0xf1, 0xd2, 0xa5, 0x4b,
+ 0xe5, 0x51, 0x81, 0xcb, 0xe5, 0xba, 0xbe, 0xf8, 0xa7, 0x95, 0x23, 0x58,
+ 0x16, 0xd0, 0xa4, 0x68, 0x4e, 0x1b, 0xe8, 0xde, 0xb6, 0x6d, 0x5b, 0xa4,
+ 0x3b, 0xa1, 0xf5, 0x5c, 0xfd, 0xf2, 0x03, 0xdf, 0xb9, 0x8e, 0x56, 0x51,
+ 0x69, 0xbf, 0xef, 0xdb, 0xb7, 0x2f, 0x26, 0xa7, 0x23, 0xb8, 0xa2, 0xcd,
+ 0x66, 0x0b, 0x79, 0x5f, 0x50, 0xfd, 0x36, 0x34, 0x1f, 0xe4, 0xc8, 0x43,
+ 0xbb, 0x4a, 0xb8, 0xf8, 0xd7, 0xbf, 0x73, 0x7c, 0xa3, 0xf8, 0xe7, 0xaf,
+ 0x8f, 0x10, 0x88, 0x91, 0x19, 0x44, 0x79, 0xda, 0x9a, 0xf8, 0x36, 0x65,
+ 0xb6, 0x6c, 0xd9, 0x12, 0xc2, 0x8e, 0x3c, 0xde, 0x72, 0xfc, 0xf8, 0xf1,
+ 0x94, 0x94, 0x94, 0xa4, 0xa4, 0xa4, 0x4e, 0x75, 0xf0, 0xf0, 0xc3, 0x0f,
+ 0xc7, 0x64, 0x5f, 0x1a, 0x17, 0x75, 0x38, 0x1c, 0xfe, 0x39, 0x0e, 0xca,
+ 0x17, 0xbc, 0x65, 0xda, 0xb4, 0x69, 0x49, 0xb5, 0xe8, 0x14, 0x19, 0x68,
+ 0x96, 0x57, 0xad, 0x5a, 0xd5, 0xf8, 0x84, 0xd5, 0x8f, 0xc6, 0xf2, 0xcf,
+ 0x0f, 0x6d, 0x5f, 0x70, 0xf1, 0xe2, 0xc5, 0x50, 0xc1, 0x28, 0xcf, 0xdf,
+ 0x3d, 0xf7, 0xdc, 0x13, 0x42, 0x20, 0xd6, 0xf2, 0xbf, 0x06, 0x34, 0x3b,
+ 0x2c, 0xa7, 0x05, 0xfa, 0xbd, 0xd0, 0x5e, 0x9f, 0x91, 0x91, 0xe1, 0x76,
+ 0xbb, 0x43, 0x58, 0x4b, 0x78, 0x63, 0x38, 0xc6, 0x32, 0x70, 0x27, 0xc3,
+ 0xbd, 0xff, 0x1c, 0x26, 0xfe, 0x69, 0x81, 0x18, 0x14, 0x5c, 0xb8, 0x70,
+ 0x61, 0x84, 0x12, 0xf9, 0x06, 0x80, 0xec, 0x73, 0xeb, 0xd6, 0xad, 0x7e,
+ 0x31, 0xd6, 0xd3, 0xe1, 0xba, 0xf5, 0x2f, 0xea, 0xa7, 0x7f, 0x44, 0x0c,
+ 0x41, 0x9d, 0x98, 0x6b, 0x14, 0x44, 0x26, 0x10, 0x94, 0x2f, 0xfe, 0xfa,
+ 0x17, 0x23, 0x7f, 0xef, 0xbd, 0xf7, 0x46, 0xc2, 0x8b, 0x76, 0xed, 0xda,
+ 0x69, 0xcb, 0x69, 0xde, 0xbc, 0x79, 0x61, 0xd4, 0xbf, 0xb0, 0xf1, 0x4f,
+ 0x03, 0xba, 0x85, 0x5c, 0x30, 0x3f, 0x3f, 0x5f, 0x9b, 0xd7, 0x68, 0x0a,
+ 0x21, 0x54, 0x10, 0x81, 0x58, 0xff, 0xd0, 0xd4, 0xe5, 0x5f, 0x41, 0x41,
+ 0x81, 0xa0, 0xfe, 0xbd, 0x96, 0xf0, 0x03, 0x66, 0xa7, 0x4e, 0x9d, 0x1a,
+ 0xac, 0x2f, 0x23, 0x46, 0x8c, 0x20, 0x08, 0x42, 0xbf, 0x2f, 0x75, 0xf7,
+ 0x9f, 0xf1, 0xc6, 0x48, 0xf8, 0x72, 0xfa, 0xf4, 0xe9, 0xe6, 0xcd, 0x9b,
+ 0x37, 0x09, 0xff, 0xfe, 0x73, 0xb8, 0xf9, 0xa7, 0xa5, 0x2f, 0x79, 0x79,
+ 0x79, 0xd1, 0x57, 0x41, 0x5c, 0x11, 0x2a, 0xa8, 0x33, 0x34, 0xd4, 0xe5,
+ 0x5f, 0xe4, 0xce, 0xdf, 0x80, 0x6b, 0x9e, 0x7f, 0x04, 0xc4, 0xa8, 0x51,
+ 0xa3, 0x18, 0x46, 0xef, 0xf7, 0xdf, 0xd7, 0x3d, 0x7f, 0x63, 0x59, 0x36,
+ 0x12, 0x5e, 0x54, 0x54, 0x54, 0x44, 0xe6, 0xfc, 0x23, 0xdc, 0xfc, 0xf3,
+ 0xfa, 0x0e, 0x9d, 0xb0, 0x04, 0x97, 0x2e, 0x5d, 0x1a, 0xfd, 0xd3, 0x11,
+ 0x44, 0x9f, 0x6d, 0xdb, 0xb6, 0xe9, 0xd9, 0xcb, 0xf0, 0xd6, 0xe1, 0x1f,
+ 0xf4, 0x66, 0x51, 0xc4, 0x90, 0x96, 0x96, 0x16, 0xda, 0x08, 0x8c, 0x1c,
+ 0x39, 0x12, 0xc1, 0x44, 0x4f, 0xb2, 0xe5, 0xe7, 0xdf, 0xfd, 0xf7, 0xdf,
+ 0x0f, 0x7e, 0x2c, 0x58, 0xb0, 0x20, 0xec, 0x5e, 0x4c, 0x9f, 0x3e, 0xfd,
+ 0x6f, 0xa0, 0x7f, 0x7e, 0x68, 0x2a, 0x38, 0x67, 0xce, 0x9c, 0xd6, 0xad,
+ 0x5b, 0x07, 0x9b, 0x89, 0x37, 0x12, 0x50, 0xc1, 0xa2, 0xa2, 0xa2, 0x80,
+ 0x25, 0x64, 0x5d, 0xfe, 0x45, 0x1a, 0x21, 0xbb, 0x0f, 0x15, 0x24, 0x49,
+ 0x52, 0x3f, 0xff, 0x22, 0x07, 0xbf, 0x0b, 0x1a, 0xff, 0xc2, 0xc5, 0x93,
+ 0x08, 0xf2, 0x4f, 0xf6, 0xdd, 0x2f, 0xb8, 0x7c, 0xf9, 0xf2, 0x5b, 0x6e,
+ 0xb9, 0x25, 0xa2, 0x43, 0x53, 0x0f, 0x4d, 0x9b, 0x36, 0x45, 0xbe, 0x5c,
+ 0x5a, 0x5a, 0xda, 0x70, 0x0f, 0xa3, 0xc6, 0xbf, 0xc6, 0x2c, 0x3f, 0xf8,
+ 0x02, 0x0a, 0x22, 0x98, 0x34, 0xec, 0x4b, 0x3d, 0xfe, 0x45, 0x62, 0xb5,
+ 0xff, 0xcd, 0xf8, 0xe7, 0x07, 0x28, 0x08, 0x15, 0x8c, 0x32, 0x05, 0x9b,
+ 0xf8, 0xf6, 0x05, 0x8b, 0x8b, 0x8b, 0x1b, 0xd8, 0x29, 0xc5, 0xf3, 0x34,
+ 0x4d, 0x9f, 0x38, 0x71, 0xe2, 0xb8, 0x3e, 0xec, 0xda, 0xb5, 0xcb, 0x64,
+ 0x32, 0x45, 0xd9, 0x8b, 0x26, 0xbe, 0x89, 0xcf, 0xca, 0xca, 0x72, 0xbb,
+ 0xdd, 0x0d, 0xfb, 0x72, 0xfe, 0xfc, 0xf9, 0xb2, 0xb2, 0x32, 0x9d, 0xbe,
+ 0x34, 0x06, 0x8d, 0x3c, 0x2a, 0xac, 0x87, 0x88, 0xf3, 0x4f, 0xf6, 0xdd,
+ 0xa6, 0xb0, 0x6c, 0xd9, 0xb2, 0x56, 0xad, 0x5a, 0x45, 0x79, 0x5f, 0x10,
+ 0x2a, 0x08, 0xd2, 0xfc, 0xd5, 0x48, 0x69, 0x0a, 0xad, 0xe8, 0x06, 0x5e,
+ 0x5c, 0x5e, 0x5e, 0xde, 0xbd, 0x7b, 0xf7, 0x68, 0xba, 0xa0, 0x01, 0x2a,
+ 0x38, 0x76, 0xec, 0xd8, 0x86, 0xf9, 0x17, 0x05, 0x68, 0x69, 0x9f, 0x7f,
+ 0xd0, 0xc2, 0x42, 0x8f, 0x88, 0xf3, 0x4f, 0xeb, 0xab, 0xa6, 0x82, 0x5a,
+ 0x39, 0x12, 0x35, 0x80, 0xee, 0xd0, 0xdd, 0xed, 0xdb, 0xb7, 0x6b, 0x25,
+ 0xd1, 0xd5, 0x1d, 0x3b, 0x79, 0xf2, 0xe4, 0xa0, 0x41, 0x83, 0x7a, 0xf7,
+ 0xee, 0x9d, 0x9c, 0x9c, 0xdc, 0x5b, 0x07, 0x50, 0x5d, 0x76, 0xec, 0xd8,
+ 0x31, 0xca, 0xab, 0x48, 0xbb, 0x4d, 0x06, 0xd0, 0x54, 0xf0, 0x9a, 0xb9,
+ 0x3f, 0x38, 0x31, 0x6b, 0xd6, 0x2c, 0xbf, 0x23, 0x3a, 0xdd, 0x09, 0x0a,
+ 0xc9, 0xb5, 0xf0, 0xdf, 0x2b, 0x19, 0x16, 0x7a, 0x44, 0x9c, 0x7f, 0x1a,
+ 0x14, 0x5f, 0x45, 0xbc, 0x62, 0xc5, 0x8a, 0x96, 0x2d, 0x5b, 0x46, 0xf9,
+ 0x7e, 0xad, 0x76, 0xed, 0xda, 0x41, 0x05, 0xaf, 0x2e, 0x47, 0xa2, 0x59,
+ 0x7f, 0x34, 0x1e, 0x60, 0x61, 0xb3, 0x66, 0xcd, 0x40, 0x41, 0xc5, 0x77,
+ 0xd4, 0x7b, 0xf5, 0xf0, 0xfa, 0xef, 0xbf, 0x6a, 0x12, 0xb1, 0x0d, 0x07,
+ 0xff, 0xe7, 0x3f, 0xfe, 0x4e, 0xf9, 0x9f, 0x06, 0x6f, 0xed, 0xc7, 0x97,
+ 0xe6, 0xce, 0x9d, 0x1b, 0xfd, 0x29, 0x6f, 0xdb, 0xb6, 0x6d, 0x49, 0x49,
+ 0xc9, 0xd5, 0x5d, 0xd2, 0xf8, 0x87, 0x31, 0x4d, 0x48, 0x48, 0xe8, 0x1f,
+ 0x19, 0xa4, 0xa6, 0xa6, 0x3e, 0xf8, 0xe0, 0x83, 0x61, 0x21, 0x84, 0x36,
+ 0xfd, 0xe3, 0xc7, 0x8f, 0x87, 0x0a, 0xd6, 0xf3, 0xc5, 0xcf, 0xbf, 0x36,
+ 0x6d, 0xda, 0xf4, 0xeb, 0xd7, 0x6f, 0xc0, 0x80, 0x01, 0x61, 0x77, 0x04,
+ 0x12, 0xa8, 0x09, 0xc7, 0xdf, 0x95, 0x7f, 0x1a, 0x90, 0x0b, 0xe6, 0xe7,
+ 0xe7, 0x47, 0x59, 0x02, 0x9b, 0xf8, 0x4e, 0x47, 0xbe, 0xf9, 0xe6, 0x9b,
+ 0xba, 0x29, 0x54, 0x5d, 0xfe, 0xad, 0x5e, 0xbd, 0x9a, 0x65, 0x59, 0x2e,
+ 0x02, 0x80, 0xd9, 0x29, 0x53, 0xa6, 0x84, 0xcb, 0x0b, 0x74, 0xb5, 0x45,
+ 0x8b, 0x16, 0x39, 0x39, 0x39, 0xa2, 0xef, 0xb6, 0x1d, 0xbf, 0x10, 0x2a,
+ 0x75, 0xce, 0x3f, 0xc0, 0xce, 0x48, 0xf8, 0x72, 0xea, 0xd4, 0x29, 0x5c,
+ 0x3a, 0xec, 0xf7, 0x3f, 0xa7, 0x76, 0x8e, 0x8b, 0xea, 0xf7, 0xbf, 0x68,
+ 0x67, 0xc4, 0x0b, 0x16, 0x2c, 0xc0, 0x4a, 0x8d, 0x7e, 0x20, 0x2e, 0x2d,
+ 0x2d, 0xbd, 0x26, 0xff, 0xb4, 0xf3, 0x8f, 0x48, 0xf8, 0xab, 0xf8, 0x3e,
+ 0xff, 0x11, 0xc6, 0x80, 0x08, 0x53, 0xcd, 0x9b, 0x37, 0x87, 0x0a, 0xd6,
+ 0xfd, 0x36, 0x05, 0x3f, 0xff, 0x7a, 0xf5, 0xea, 0x45, 0x51, 0x54, 0x24,
+ 0x7c, 0x41, 0xed, 0x15, 0x89, 0xf3, 0x8f, 0x7e, 0x49, 0xd1, 0xe5, 0x9f,
+ 0x96, 0xbe, 0xfc, 0x5f, 0x7b, 0xe7, 0x1f, 0xd3, 0xd4, 0x15, 0xc5, 0xf1,
+ 0xfe, 0xa9, 0x09, 0x92, 0x80, 0xfa, 0xa7, 0x3f, 0xfe, 0x72, 0x3f, 0x68,
+ 0xb5, 0x80, 0x14, 0x6a, 0x11, 0x81, 0x22, 0x60, 0x91, 0x88, 0xe2, 0x86,
+ 0xbf, 0x6b, 0x75, 0xe2, 0x96, 0x80, 0x80, 0x5b, 0xe2, 0x86, 0x9b, 0x73,
+ 0xd9, 0x1f, 0x26, 0xfb, 0x87, 0x44, 0x12, 0x2d, 0x28, 0x20, 0x48, 0x48,
+ 0x74, 0x40, 0x5d, 0x40, 0x37, 0xff, 0x32, 0xf1, 0x0f, 0x1c, 0x42, 0x96,
+ 0x99, 0x49, 0x0b, 0x43, 0x0b, 0x33, 0x92, 0x95, 0x19, 0x7f, 0xd0, 0x38,
+ 0x9a, 0x4c, 0x20, 0x3b, 0xf6, 0x84, 0x9b, 0x0e, 0x06, 0xaf, 0xb4, 0xef,
+ 0xde, 0x77, 0x6f, 0x79, 0xdf, 0x10, 0xa2, 0x01, 0xfa, 0xde, 0x79, 0xef,
+ 0xf3, 0xce, 0x3d, 0xe7, 0xbe, 0x73, 0xcf, 0xc5, 0xa5, 0xec, 0xec, 0xbd,
+ 0x20, 0x0c, 0xc4, 0x5d, 0x5d, 0x5d, 0x78, 0x26, 0x81, 0xf1, 0xdf, 0xa9,
+ 0x53, 0xa7, 0xae, 0x5f, 0xbf, 0xfe, 0x3d, 0x1d, 0xed, 0xdd, 0xbb, 0x57,
+ 0x46, 0x13, 0x30, 0x17, 0x81, 0x58, 0xb0, 0xbc, 0xbc, 0x7c, 0xb6, 0xff,
+ 0x5b, 0xb7, 0x6e, 0x5d, 0x4b, 0x4b, 0x0b, 0x0d, 0x2b, 0x6a, 0x6a, 0x6a,
+ 0x68, 0xbc, 0xff, 0x60, 0xcd, 0x1f, 0x11, 0x20, 0x68, 0xb7, 0xdb, 0x63,
+ 0x62, 0x62, 0x70, 0x55, 0xa9, 0x8c, 0x77, 0x68, 0x7e, 0xad, 0x5a, 0xb5,
+ 0xea, 0xce, 0x9d, 0x3b, 0x38, 0xf9, 0x02, 0xfc, 0xc9, 0xb8, 0x72, 0x80,
+ 0xa5, 0x15, 0x88, 0xe0, 0xc9, 0x93, 0x27, 0xc1, 0x0b, 0x62, 0x41, 0x28,
+ 0xed, 0xf7, 0x1f, 0x44, 0x55, 0x55, 0x55, 0x32, 0xe6, 0xbf, 0x19, 0x09,
+ 0x0a, 0xf1, 0x37, 0x31, 0xbd, 0x7c, 0x09, 0xe7, 0x17, 0xd8, 0x5c, 0x3b,
+ 0x54, 0x74, 0x74, 0x74, 0x77, 0x77, 0x37, 0x9c, 0x40, 0x4f, 0x4f, 0x8f,
+ 0xbc, 0x35, 0xdb, 0xcc, 0x10, 0xc4, 0x8b, 0x06, 0x08, 0x82, 0xe7, 0xc6,
+ 0x67, 0xc9, 0x66, 0xb3, 0xb1, 0x39, 0x3a, 0xd6, 0xff, 0xc9, 0xe7, 0xff,
+ 0x98, 0xe4, 0x1f, 0xb3, 0x45, 0xca, 0x14, 0x60, 0x20, 0x46, 0x27, 0xc4,
+ 0x92, 0xc2, 0xb5, 0x6b, 0xd7, 0xde, 0xbd, 0x7b, 0xd7, 0xeb, 0xf5, 0x02,
+ 0x88, 0xf7, 0xe4, 0x50, 0x47, 0x47, 0x87, 0x4e, 0xa7, 0x63, 0x76, 0xfe,
+ 0x44, 0x70, 0xd1, 0x2a, 0x2a, 0x2a, 0x20, 0xe6, 0x1b, 0x1c, 0x1c, 0x84,
+ 0x04, 0x4b, 0x16, 0x5b, 0xe6, 0xd7, 0xc8, 0xc8, 0x88, 0x8c, 0xf5, 0xf7,
+ 0x19, 0x09, 0x0a, 0xf1, 0x87, 0xc2, 0x24, 0xae, 0xba, 0xba, 0x1a, 0x97,
+ 0xf7, 0xb1, 0x1c, 0xc2, 0xa2, 0xa2, 0xa2, 0x00, 0x3e, 0x78, 0x00, 0xde,
+ 0xc8, 0x21, 0xf0, 0xe5, 0x1e, 0x8f, 0x47, 0xab, 0xd5, 0x32, 0x3b, 0x7f,
+ 0x14, 0xb8, 0x40, 0x40, 0xb0, 0xb2, 0xb2, 0x12, 0xe2, 0x19, 0xb9, 0x6c,
+ 0x91, 0x94, 0x8c, 0xef, 0x3f, 0x14, 0xe6, 0x6f, 0xca, 0xdf, 0x0d, 0x08,
+ 0xae, 0xdd, 0xe5, 0xcb, 0x97, 0x19, 0xcf, 0x0b, 0x02, 0xeb, 0xab, 0x57,
+ 0xaf, 0xde, 0xb1, 0x63, 0xc7, 0x4e, 0x39, 0x54, 0x50, 0x50, 0x00, 0xdf,
+ 0xf5, 0x7a, 0x3d, 0x4b, 0x13, 0x34, 0xd3, 0x93, 0x82, 0x90, 0x19, 0x98,
+ 0xcd, 0x66, 0x59, 0x0c, 0x91, 0x14, 0x2e, 0x75, 0x90, 0xed, 0xfd, 0x9b,
+ 0x52, 0xf1, 0xdf, 0x0c, 0x81, 0xff, 0x80, 0xc0, 0x02, 0xbd, 0x20, 0xfb,
+ 0x05, 0xed, 0x11, 0x70, 0x08, 0x72, 0x20, 0xda, 0xc7, 0x92, 0x79, 0xfe,
+ 0x8f, 0x13, 0xfe, 0x70, 0x08, 0xab, 0xad, 0xad, 0x85, 0xe4, 0x80, 0xfd,
+ 0x0b, 0x56, 0x93, 0xc9, 0x54, 0x44, 0x4d, 0x10, 0x17, 0x32, 0xb3, 0x68,
+ 0xc5, 0x8a, 0x15, 0x94, 0xac, 0xc8, 0xcf, 0xcf, 0xc7, 0x25, 0xde, 0xf2,
+ 0xf2, 0xb7, 0x65, 0xc3, 0x7b, 0x5c, 0xf0, 0x47, 0xca, 0x14, 0xc0, 0x3c,
+ 0xf6, 0xfd, 0x05, 0x5b, 0x5b, 0x5b, 0x29, 0xcd, 0x3f, 0xc3, 0x50, 0x15,
+ 0x5a, 0xfd, 0x7d, 0x68, 0xc2, 0xfe, 0x57, 0x34, 0x6c, 0x19, 0x1a, 0x1a,
+ 0xc2, 0xd1, 0x49, 0x5e, 0xfe, 0x4c, 0xda, 0x77, 0xb8, 0xe0, 0x0f, 0x85,
+ 0x08, 0x42, 0x2c, 0x88, 0xf5, 0x82, 0xcc, 0x06, 0x62, 0x6c, 0xe5, 0x41,
+ 0xc3, 0xa2, 0xa9, 0x50, 0xd7, 0x7f, 0x84, 0x26, 0xe0, 0xcf, 0xe7, 0xf3,
+ 0xd1, 0xb0, 0x05, 0xf8, 0xa3, 0x31, 0xff, 0xbc, 0x89, 0x2b, 0xfe, 0x30,
+ 0x1d, 0xc1, 0x45, 0x9c, 0xcb, 0x96, 0x2d, 0x03, 0x87, 0xcf, 0xe6, 0xb6,
+ 0xa9, 0xfc, 0x49, 0x8a, 0x12, 0x7f, 0x46, 0xde, 0xf8, 0xc3, 0xb9, 0x4d,
+ 0x88, 0x05, 0xc1, 0x0b, 0xe2, 0xda, 0x11, 0x06, 0xb7, 0x4d, 0xe5, 0x4f,
+ 0x52, 0xb4, 0xf8, 0xd3, 0xf1, 0x11, 0xff, 0xcd, 0x10, 0x96, 0x29, 0x80,
+ 0xa9, 0x6c, 0x7a, 0xca, 0xa8, 0xfc, 0x49, 0x8a, 0x12, 0x7f, 0xe9, 0x1b,
+ 0xe3, 0x79, 0xe4, 0x6f, 0xd2, 0x5f, 0xef, 0x0e, 0xb1, 0x60, 0x5d, 0x5d,
+ 0x1d, 0x83, 0xdb, 0xa6, 0xf2, 0x27, 0x29, 0x4a, 0xfc, 0xe5, 0x6c, 0x36,
+ 0xf2, 0xc8, 0x1f, 0x11, 0x20, 0x18, 0x13, 0x13, 0x43, 0xbb, 0xb9, 0x1b,
+ 0x03, 0xfe, 0x56, 0xae, 0x5c, 0xc9, 0xa0, 0xb3, 0x91, 0x70, 0xfc, 0x59,
+ 0x32, 0xb7, 0x70, 0xcd, 0x1f, 0xa4, 0x23, 0x10, 0x08, 0x46, 0x00, 0x7f,
+ 0x5a, 0xad, 0xd6, 0xed, 0x76, 0x1b, 0x0c, 0x06, 0x7a, 0x56, 0x68, 0x04,
+ 0xe4, 0x2f, 0x3f, 0x3b, 0x8b, 0x6b, 0xfe, 0x26, 0xfd, 0xfd, 0x2d, 0x2f,
+ 0x5c, 0xb8, 0x80, 0x35, 0x0a, 0x94, 0x28, 0x64, 0xc0, 0x5f, 0x5c, 0x5c,
+ 0xdc, 0xab, 0x57, 0xaf, 0x9c, 0x4e, 0x27, 0xd5, 0x77, 0x74, 0xc2, 0xf1,
+ 0xb7, 0x9d, 0xff, 0xfd, 0xa7, 0xb1, 0x4c, 0x06, 0xbc, 0x20, 0xbd, 0x57,
+ 0x73, 0x6c, 0xf8, 0xc3, 0xca, 0xe4, 0x97, 0x2f, 0x5f, 0x26, 0x25, 0x25,
+ 0xd1, 0xb0, 0x42, 0x23, 0x20, 0x7f, 0x79, 0xfc, 0xef, 0xff, 0x3b, 0x39,
+ 0xdd, 0xd9, 0xad, 0xb6, 0xb6, 0x36, 0x36, 0x36, 0x96, 0x86, 0x0b, 0x64,
+ 0xc9, 0x1f, 0xd8, 0xd2, 0xd7, 0xd7, 0x97, 0x98, 0x98, 0x28, 0xbb, 0x15,
+ 0x1a, 0x01, 0xf9, 0xb3, 0x64, 0x48, 0xed, 0x7f, 0xa9, 0xb8, 0xc8, 0xda,
+ 0x25, 0x88, 0x05, 0x6b, 0x6a, 0x6a, 0x68, 0xdc, 0x36, 0x66, 0xfc, 0x11,
+ 0x5b, 0xbc, 0x5e, 0x6f, 0x42, 0x42, 0x82, 0xec, 0x86, 0x08, 0xc7, 0x5f,
+ 0x6e, 0x9a, 0x89, 0x77, 0xfe, 0x88, 0xf0, 0xd5, 0x08, 0x0d, 0x2f, 0xc8,
+ 0x8c, 0xbf, 0x40, 0x5b, 0xc0, 0x0b, 0x26, 0x27, 0x27, 0xcb, 0x68, 0x85,
+ 0x46, 0x40, 0xfe, 0xa4, 0xf7, 0x5f, 0xe5, 0x47, 0x6f, 0xfc, 0x0b, 0x1d,
+ 0xe0, 0xfb, 0xc5, 0x8b, 0x17, 0x71, 0x2d, 0x96, 0x5c, 0x62, 0xcf, 0x1f,
+ 0x0e, 0xc4, 0x2f, 0x5e, 0xbc, 0x88, 0x8f, 0x8f, 0x97, 0xf1, 0x59, 0x12,
+ 0x8e, 0xbf, 0xad, 0xc6, 0x8d, 0xc2, 0xf0, 0x87, 0x9a, 0xf2, 0xf7, 0x3a,
+ 0xaf, 0xaf, 0xaf, 0x87, 0x8c, 0x58, 0xae, 0x72, 0x37, 0xf6, 0xfc, 0x91,
+ 0x9f, 0xba, 0x5c, 0xae, 0x94, 0x94, 0x14, 0xb9, 0x10, 0x14, 0x8e, 0xbf,
+ 0x2c, 0x03, 0x97, 0xef, 0x3f, 0xe6, 0xd1, 0xd4, 0xf4, 0x7e, 0xd8, 0xe0,
+ 0x05, 0x97, 0x2e, 0x5d, 0x2a, 0x4b, 0x46, 0xac, 0x20, 0x7f, 0xe0, 0x05,
+ 0x3d, 0x1e, 0x0f, 0x78, 0xc1, 0xf0, 0xad, 0xd0, 0x08, 0xc8, 0x9f, 0x79,
+ 0xe3, 0x06, 0xf1, 0xf8, 0xc3, 0x1a, 0x05, 0xa0, 0x10, 0xbc, 0x20, 0xb6,
+ 0xdb, 0x0f, 0xd3, 0x7f, 0x28, 0xc8, 0x1f, 0xda, 0xd2, 0xdf, 0xdf, 0x0f,
+ 0xe8, 0x2c, 0x42, 0xfe, 0x32, 0x13, 0xc3, 0xdb, 0x7f, 0x46, 0x41, 0x91,
+ 0x15, 0x9c, 0x51, 0x51, 0x51, 0x61, 0x2e, 0x22, 0x56, 0x8a, 0x3f, 0x22,
+ 0xa0, 0xf0, 0xc9, 0x93, 0x27, 0x38, 0x29, 0x13, 0x8e, 0x47, 0x17, 0x8e,
+ 0x3f, 0xc5, 0xd6, 0xff, 0x86, 0x2f, 0xd2, 0x03, 0xa5, 0xb1, 0xb1, 0x31,
+ 0xcc, 0xaa, 0x7d, 0xc5, 0xf9, 0xc3, 0x35, 0xbc, 0x83, 0x83, 0x83, 0xa9,
+ 0xa9, 0xa9, 0x21, 0x5b, 0x21, 0x26, 0x7f, 0x71, 0xa2, 0xf2, 0x47, 0x04,
+ 0x20, 0x9e, 0x3f, 0x7f, 0x1e, 0x11, 0x0c, 0xcd, 0x79, 0x28, 0xce, 0x1f,
+ 0x91, 0xdb, 0xed, 0x0e, 0x67, 0x5e, 0x50, 0x3c, 0xfe, 0xe2, 0xdf, 0x17,
+ 0x9e, 0x3f, 0x1c, 0x88, 0x1b, 0x1a, 0x1a, 0x70, 0x20, 0x16, 0x9a, 0x3f,
+ 0xb0, 0x05, 0x06, 0xe2, 0x90, 0xbd, 0xa0, 0x70, 0xfc, 0xa5, 0xeb, 0x23,
+ 0x82, 0x3f, 0x6c, 0x6b, 0x04, 0xb1, 0x60, 0x68, 0xf5, 0xaa, 0x5c, 0xf1,
+ 0x07, 0x7a, 0xf4, 0xe8, 0x51, 0x68, 0x5e, 0x50, 0x40, 0xfe, 0xb8, 0xac,
+ 0x7f, 0x0e, 0x41, 0x58, 0x29, 0x03, 0xb1, 0xe0, 0x92, 0x25, 0x4b, 0x16,
+ 0x3a, 0x10, 0xf3, 0xc3, 0x1f, 0xf9, 0xab, 0x91, 0x91, 0x11, 0x93, 0xc9,
+ 0xa4, 0xf2, 0x27, 0x8c, 0x48, 0x99, 0x82, 0xdd, 0x6e, 0x5f, 0xbe, 0x7c,
+ 0xf9, 0x82, 0xd2, 0x11, 0xde, 0xf8, 0x43, 0x5b, 0xfa, 0xfb, 0xfb, 0x17,
+ 0x5a, 0xa6, 0xa0, 0xf2, 0xa7, 0x98, 0xc8, 0xab, 0x7d, 0xb8, 0x79, 0x57,
+ 0xae, 0x5c, 0xc1, 0x92, 0xd5, 0x20, 0x29, 0xe4, 0x8d, 0x3f, 0x62, 0xcb,
+ 0xb3, 0x67, 0xcf, 0x8c, 0x46, 0x63, 0xf0, 0xcf, 0x92, 0xca, 0x9f, 0xf2,
+ 0xc2, 0xb7, 0x23, 0x97, 0x2e, 0x5d, 0x02, 0x2f, 0x18, 0xe4, 0x0a, 0x4e,
+ 0xde, 0xf8, 0x0b, 0xfc, 0x73, 0x97, 0xcb, 0x15, 0x7c, 0x2c, 0xa8, 0xf2,
+ 0xa7, 0xbc, 0x00, 0x3e, 0xac, 0x54, 0x80, 0x8c, 0x58, 0x50, 0xff, 0x47,
+ 0x84, 0x2d, 0xad, 0xc6, 0xc6, 0xc6, 0x82, 0xdc, 0x77, 0x44, 0xe5, 0x8f,
+ 0x23, 0xc1, 0xcd, 0x03, 0x04, 0xc1, 0x0b, 0x4a, 0xbe, 0x1d, 0xe1, 0x96,
+ 0x3f, 0x22, 0xa7, 0xd3, 0x99, 0x94, 0x94, 0x24, 0xf9, 0x38, 0xb1, 0xe7,
+ 0x6f, 0x62, 0x5a, 0xf0, 0xd8, 0x8f, 0x8f, 0x8f, 0xc3, 0x35, 0x5f, 0xd0,
+ 0xfe, 0xed, 0xe9, 0xfa, 0x77, 0x23, 0x96, 0x3f, 0xec, 0xec, 0x56, 0x5f,
+ 0x5f, 0x8f, 0x3d, 0x93, 0x85, 0xe6, 0x0f, 0x6e, 0x2a, 0x78, 0x41, 0xc9,
+ 0x74, 0x84, 0x3d, 0x7f, 0x38, 0xd4, 0xdc, 0xbc, 0x79, 0x6b, 0xd7, 0xce,
+ 0xc2, 0x78, 0x7d, 0x82, 0x65, 0x5b, 0x5e, 0x7d, 0x5d, 0x83, 0x6f, 0xdc,
+ 0x17, 0xe4, 0xc7, 0x46, 0x32, 0x7f, 0xb8, 0x7f, 0x33, 0x5c, 0x20, 0x48,
+ 0x47, 0x30, 0x23, 0x9e, 0xcb, 0x7f, 0xf0, 0xcf, 0x1f, 0xf6, 0x67, 0x82,
+ 0x8c, 0x78, 0xfe, 0x74, 0x84, 0x25, 0x7f, 0x98, 0xea, 0x8d, 0x8d, 0x79,
+ 0x4b, 0x4a, 0x4a, 0xad, 0x87, 0xac, 0x6d, 0xad, 0xed, 0x3d, 0x3d, 0xbd,
+ 0x9d, 0x9d, 0x37, 0x2b, 0xca, 0x3f, 0xb5, 0x1e, 0xb2, 0x0d, 0xb9, 0x87,
+ 0x82, 0x69, 0xd3, 0x1b, 0xc9, 0xfc, 0xa1, 0x70, 0x1d, 0x3b, 0x2e, 0xe2,
+ 0x9c, 0x6b, 0x1d, 0x27, 0xff, 0xfc, 0x91, 0x4f, 0x7b, 0xfe, 0xfc, 0x39,
+ 0xa6, 0x23, 0xff, 0x6b, 0x08, 0x4b, 0xfe, 0x70, 0x92, 0xe8, 0x74, 0xe5,
+ 0x99, 0xe2, 0x63, 0x1f, 0xdf, 0xfe, 0xe9, 0xf6, 0x57, 0x5f, 0x9e, 0x81,
+ 0xff, 0x56, 0x55, 0x55, 0x95, 0x96, 0x9c, 0x38, 0x51, 0x5a, 0x7e, 0xd8,
+ 0x6a, 0xf3, 0xf9, 0x37, 0x2f, 0x9e, 0xff, 0x63, 0x23, 0x39, 0xfe, 0x43,
+ 0x61, 0x38, 0x82, 0x53, 0xd3, 0xb1, 0xb1, 0xb1, 0x82, 0xfa, 0x3f, 0x14,
+ 0x46, 0x5a, 0xe0, 0x05, 0xe7, 0x9a, 0x9a, 0x66, 0xcc, 0xdf, 0xc0, 0xc0,
+ 0x80, 0x4e, 0xab, 0xbf, 0xd7, 0xf5, 0x73, 0x5b, 0x5b, 0x7b, 0x69, 0x49,
+ 0x19, 0x0c, 0xbb, 0x07, 0x0f, 0x1c, 0x3e, 0x77, 0xee, 0x3b, 0xcf, 0x9f,
+ 0x1e, 0x73, 0x66, 0x16, 0x9c, 0xa7, 0x24, 0x7f, 0x5b, 0x22, 0x9e, 0x3f,
+ 0x22, 0x5c, 0xbe, 0x84, 0x6f, 0x47, 0x66, 0xcc, 0xcb, 0x88, 0xc2, 0x1f,
+ 0xd1, 0xe8, 0xe8, 0x28, 0xc4, 0x82, 0xb3, 0x5d, 0x20, 0x33, 0xfe, 0x30,
+ 0x1e, 0xe8, 0xec, 0xe8, 0x5c, 0xaf, 0x8d, 0x07, 0x97, 0xec, 0x68, 0x77,
+ 0xe4, 0xe6, 0x6c, 0xff, 0xe2, 0xf3, 0xd3, 0xc6, 0x94, 0x4d, 0x0f, 0x7e,
+ 0x7d, 0x00, 0x0f, 0xc9, 0x11, 0xdb, 0x51, 0x70, 0x8a, 0x92, 0xfc, 0x09,
+ 0x5c, 0x7f, 0xb5, 0x50, 0x81, 0x0b, 0x84, 0xec, 0xac, 0xa9, 0xa9, 0x09,
+ 0x1b, 0x7a, 0x08, 0xcd, 0x1f, 0xfa, 0x9e, 0xd9, 0x65, 0x0a, 0x0c, 0xf9,
+ 0x9b, 0x80, 0xaf, 0x8e, 0x8e, 0x4e, 0x9d, 0x9f, 0xbf, 0x1b, 0x8e, 0x1f,
+ 0x76, 0x17, 0x16, 0xb5, 0xb7, 0x39, 0x3e, 0xfc, 0xa0, 0xa8, 0xa9, 0xf1,
+ 0x2a, 0x5c, 0xea, 0xa3, 0x47, 0x3e, 0xba, 0x75, 0xeb, 0x47, 0x49, 0xfe,
+ 0x32, 0x95, 0xda, 0x7f, 0x86, 0xbd, 0x70, 0x5e, 0x10, 0x64, 0xb7, 0xdb,
+ 0x67, 0xb4, 0x58, 0x6d, 0x69, 0x69, 0x79, 0xfd, 0xfa, 0xf5, 0xdf, 0x14,
+ 0x04, 0x1f, 0x5b, 0x59, 0x59, 0x29, 0x3b, 0x7f, 0x58, 0xfb, 0xf8, 0xf4,
+ 0xe9, 0xd3, 0x19, 0x19, 0x71, 0x4a, 0x4a, 0x0a, 0xd0, 0x40, 0xc3, 0x16,
+ 0x97, 0xcb, 0xf5, 0xdf, 0xf1, 0x17, 0x72, 0x8b, 0xc9, 0x87, 0x0f, 0xfb,
+ 0xd6, 0xeb, 0x12, 0x7a, 0x7b, 0x7b, 0x1d, 0xed, 0x37, 0x8a, 0x8f, 0x1d,
+ 0x1f, 0x1e, 0xfe, 0x03, 0xb0, 0x2b, 0x3b, 0x51, 0x0e, 0xe7, 0x90, 0x99,
+ 0x61, 0x76, 0x3a, 0x9d, 0x92, 0xfc, 0x65, 0x19, 0xf4, 0x8b, 0x85, 0x3f,
+ 0xd4, 0x94, 0xbf, 0xb9, 0x60, 0x73, 0x73, 0x33, 0xee, 0xfc, 0x86, 0x43,
+ 0x18, 0xc0, 0x91, 0x96, 0x96, 0xb6, 0x99, 0x82, 0xe0, 0x63, 0xd7, 0xac,
+ 0x59, 0x23, 0x3b, 0x7f, 0xc4, 0x96, 0xc7, 0x8f, 0x1f, 0xc3, 0x21, 0x08,
+ 0x7f, 0xd1, 0xd1, 0xd1, 0x10, 0x1a, 0xd2, 0x30, 0xc4, 0x60, 0x30, 0x04,
+ 0xee, 0xbf, 0x8a, 0x43, 0x30, 0x24, 0x76, 0x15, 0x65, 0x9f, 0x95, 0x97,
+ 0x55, 0xdc, 0xef, 0xbe, 0x5f, 0xf2, 0x36, 0xed, 0x28, 0xfb, 0xe6, 0xec,
+ 0xb7, 0x0f, 0x7f, 0xeb, 0x83, 0x5c, 0xe4, 0xc0, 0xfe, 0x83, 0x5e, 0xaf,
+ 0x97, 0xec, 0x50, 0x37, 0x97, 0xb6, 0x26, 0x8b, 0xb6, 0xfe, 0x28, 0x4c,
+ 0x61, 0xa5, 0x16, 0x0c, 0xc4, 0x10, 0x0b, 0xb2, 0xdc, 0x03, 0x91, 0x06,
+ 0x7f, 0x18, 0x84, 0xcd, 0x2e, 0x59, 0xa5, 0xd1, 0x22, 0x82, 0xcc, 0xe1,
+ 0x07, 0xf2, 0x07, 0xf2, 0x8e, 0x79, 0xf7, 0xef, 0x3b, 0x78, 0xfc, 0xd8,
+ 0x27, 0xbd, 0xbd, 0xbf, 0x0c, 0xb9, 0x87, 0x9d, 0x7d, 0xce, 0xaf, 0xcf,
+ 0x9c, 0xcd, 0xb3, 0x6c, 0x1f, 0xe8, 0xff, 0x3d, 0x98, 0x6d, 0x1a, 0xb2,
+ 0x8d, 0x89, 0x8b, 0x8b, 0xbf, 0xa9, 0x80, 0x16, 0xab, 0xd7, 0xae, 0x5d,
+ 0xb3, 0x58, 0x2c, 0x39, 0x4c, 0x54, 0x5c, 0x5c, 0x0c, 0xa3, 0x98, 0xa4,
+ 0x3f, 0x58, 0xa8, 0x2d, 0xa8, 0xe1, 0xe1, 0x61, 0xab, 0xd5, 0x8a, 0x07,
+ 0xca, 0xf5, 0x4b, 0xf6, 0xf3, 0x27, 0x1f, 0xeb, 0x70, 0x38, 0x10, 0x2c,
+ 0x3c, 0x34, 0xfc, 0x7b, 0x74, 0xf4, 0xaf, 0xab, 0x57, 0x9b, 0xad, 0x87,
+ 0x6c, 0x85, 0xbb, 0x3e, 0xdc, 0xb3, 0x67, 0x5f, 0x75, 0x75, 0x35, 0x04,
+ 0x06, 0xf0, 0x73, 0xfc, 0x95, 0xf9, 0x4d, 0xc8, 0xd9, 0x94, 0xb4, 0xb8,
+ 0xf8, 0x23, 0xc2, 0x8b, 0x48, 0xae, 0x23, 0x6d, 0x91, 0xc3, 0x51, 0xb2,
+ 0x25, 0x90, 0x09, 0xaa, 0xc2, 0xa3, 0x10, 0x43, 0x70, 0x16, 0xf0, 0xed,
+ 0x24, 0xd7, 0x3f, 0x13, 0xbe, 0x71, 0x1f, 0x9c, 0x05, 0x4e, 0xfb, 0x07,
+ 0x79, 0xe6, 0xb9, 0x26, 0xc3, 0x22, 0xe5, 0x6f, 0x72, 0x5a, 0x0c, 0xee,
+ 0xd9, 0xd4, 0xf4, 0x68, 0x45, 0x8f, 0x3f, 0x66, 0xb6, 0xcc, 0x30, 0x04,
+ 0xf9, 0x9b, 0x0c, 0xd0, 0x82, 0xf8, 0xdb, 0x96, 0x2a, 0x4e, 0xff, 0x0d,
+ 0x55, 0x91, 0xa7, 0xbc, 0x34, 0xbe, 0xfb, 0xef, 0xaa, 0x8a, 0x6c, 0xe5,
+ 0xa7, 0xa7, 0xaa, 0xfc, 0xa9, 0x52, 0x4c, 0x05, 0x66, 0xee, 0xfb, 0xff,
+ 0xa9, 0x8a, 0x60, 0xed, 0xda, 0xca, 0x7d, 0xff, 0x53, 0x55, 0x11, 0xac,
+ 0xc2, 0xec, 0x0c, 0x95, 0x3f, 0x55, 0x8a, 0x69, 0x77, 0x0e, 0xf7, 0xfd,
+ 0xc7, 0x55, 0x45, 0xb0, 0x8a, 0x2c, 0x7c, 0xef, 0xbf, 0xa0, 0x2a, 0xb2,
+ 0x55, 0x94, 0x97, 0xad, 0xf2, 0xa7, 0x4a, 0x31, 0xed, 0xcb, 0xdf, 0xa6,
+ 0xf2, 0xa7, 0x4a, 0x31, 0xed, 0x07, 0xfe, 0x34, 0x9a, 0x7f, 0x01, 0x2d,
+ 0x25, 0xd7, 0x6c, 0xb8, 0x38, 0x01, 0x00,
+};
diff --git a/board/Marvell/dkb/dkb.c b/board/Marvell/dkb/dkb.c
index 00f73e79f7..fa040c5544 100644
--- a/board/Marvell/dkb/dkb.c
+++ b/board/Marvell/dkb/dkb.c
@@ -24,8 +24,15 @@
 
 #include <common.h>
 #include <mvmfp.h>
+#include <i2c.h>
 #include <asm/arch/mfp.h>
 #include <asm/arch/cpu.h>
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -40,6 +47,20 @@ int board_early_init_f(void)
 		MFP53_CI2C_SCL,
 		MFP54_CI2C_SDA,
 
+		/* MMC1 */
+		MFP_MMC1_DAT7,
+		MFP_MMC1_DAT6,
+		MFP_MMC1_DAT5,
+		MFP_MMC1_DAT4,
+		MFP_MMC1_DAT3,
+		MFP_MMC1_DAT2,
+		MFP_MMC1_DAT1,
+		MFP_MMC1_DAT0,
+		MFP_MMC1_CMD,
+		MFP_MMC1_CLK,
+		MFP_MMC1_CD,
+		MFP_MMC1_WP,
+
 		MFP_EOC		/*End of configureation*/
 	};
 	/* configure MFP's */
@@ -56,3 +77,81 @@ int board_init(void)
 	gd->bd->bi_boot_params = panth_sdram_base(0) + 0x100;
 	return 0;
 }
+
+#ifdef CONFIG_GENERIC_MMC
+#define I2C_SLAVE_ADDR	0x34
+#define LDO13_REG	0x28
+#define LDO_V30		0x6
+#define LDO_VOLTAGE(x)	((x & 0x7) << 1)
+#define LDO_EN		0x1
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i, data;
+
+	/* set LDO 13 to 3.0v */
+	data = LDO_VOLTAGE(LDO_V30) | LDO_EN;
+	i2c_write(I2C_SLAVE_ADDR, LDO13_REG, 1, &data, 1);
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count;
+
+	writel(USB_CTL_29_28(BIT160) | PU_REF | REG_ARC_DPDM_MODE | PU_PLL
+	       | PU, &file->UTMI_CTRL);
+	writel(PLLCALI12(ALLSET) | PLLVDD18(ALLSET) | PLLVDD12(ALLSET)
+	       | PLLREADY | KVCO(MIDKVCO) | ICP(MUA10) | FBDIV(DIV240)
+	       | REFDIV(DIV13), &file->UTMI_PLL);
+	writel(REG_EXT_FS_RCAL(FS_DEF) | TXVDD18(VDD_DEF) | TXVDD12(VDD_ALL)
+	       | TXDATA_BLOCK_EN | CK60_PHSEL(CLK60VAL) | IMPCAL_VTH(VTH45OHM)
+	       | HSDRV_EN(HSVAL) | REG_EXT_HS_RCAL(HS45OHM) | AMP(MA18),
+	       &file->UTMI_TX);
+	writel(EARLY_VOS_ON_EN | RXDATA_BLOCK_EN | RXDATA_BLOCK_LENGTH(DEFLEN)
+	       | EDGE_DET_EN | S2TO3_DLY_SEL(CLK_16CYCLE) | PHASE_FREEZE_DLY
+	       | REG_USQ_LENGTH | REG_ACQ_LENGTH(DEFLEN)
+	       | REQ_SQ_LENGTH(SQUELCH_9HIGH) | DISCON_THRESH(VL2425_VH2925)
+	       | SQ_THRESH(VOSL360_V100H450_V150H583) | INTPI(MU20),
+	       &file->UTMI_RX);
+	writel(RXVDD12(V145) | FSDRV_EN(ALLEN) | REG_IMP_CAL_DLY(REGDEF),
+	       &file->UTMI_IVREF);
+	writel(0, &file->UTMI_CTL1);
+	writel(TEST_GRP_5_VALUE, &file->UTMI_TEST_GRP_5);
+
+	/* make sure phy is ready */
+	count = 100;
+	while (((readl(&file->UTMI_PLL) & PLLREADY) == 0) && count--)
+		udelay(1000);
+	if (count <= 0) {
+		printf("%s %d: calibrate timeout, UTMI_PLL %x\n",
+				__func__, __LINE__, readl(&file->UTMI_PLL));
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
diff --git a/board/Marvell/g50/Makefile b/board/Marvell/g50/Makefile
new file mode 100644
index 0000000000..eef53bcf51
--- /dev/null
+++ b/board/Marvell/g50/Makefile
@@ -0,0 +1,49 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+# Lei Wen, <leiwen@marvell.com>
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= g50.o
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/g50/g50.c b/board/Marvell/g50/g50.c
new file mode 100644
index 0000000000..69b7ee9088
--- /dev/null
+++ b/board/Marvell/g50/g50.c
@@ -0,0 +1,177 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+		MMC1_WP,
+
+		/* MMC3 */
+		MMC3_DATA7,
+		MMC3_DATA6,
+		MMC3_DATA5,
+		MMC3_DATA4,
+		MMC3_DATA3,
+		MMC3_DATA2,
+		MMC3_DATA1,
+		MMC3_DATA0,
+		MMC3_CLK,
+		MMC3_CMD,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+	return 0;
+}
+
+int board_init(void)
+{
+	/* arch number of FPGA Board */
+	gd->bd->bi_arch_number = MACH_TYPE_G50;
+	gd->bd->bi_boot_params = 0x3c00;
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	setenv("fbenv", "mmc1");
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i;
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+	}
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count = 0;
+	int reg;
+
+	/* initialize the usb phy power */
+	writel(readl(&file->ctrl_reg) | POWER_UP | PLL_POWER_UP |
+			PU_REF | USB_CTL_29_28(1), &file->ctrl_reg);
+	/* UTMI_PLL settings */
+	writel(readl(&file->pll_reg) & ~(REFDIV_MASK | FBDIV_MASK | ICP_MASK |
+				PLLVDD12_MASK | PLLVDD18_MASK |
+				PLLCALLI12_MASK), &file->pll_reg);
+	writel(readl(&file->pll_reg) | REFDIV(13) | FBDIV(240) | ICP(10) |
+			PLL_READY | PLLVDD12(3) | PLLVDD18(3) | PLLCALLI12(3),
+			&file->pll_reg);
+	/* UTMI_TX */
+	writel(readl(&file->tx_reg) & ~(IMPCAL_VTH_MASK | CK60_PHSEL_Mask |
+				TXVDD12_MASK), &file->tx_reg);
+	writel(readl(&file->tx_reg) | IMPCAL_VTH(5) | CK60_PHSEL(4) |
+			TXVDD12(3) | TXDATA_BLOCK_EN , &file->tx_reg);
+	/* calibrate */
+	count = 10000;
+	while (((readl(&file->pll_reg) & PLL_READY) == 0) && count--)
+		;
+	if (count <= 0)
+		printf("Calibrate timeout, UTMI_PLL:%x\n",
+				readl(&file->pll_reg));
+
+	/* toggle VCOCAL_START bit of UTMI_PLL */
+	udelay(200);
+	reg = readl(&file->pll_reg);
+	writel(reg | VCOCAL_START, &file->pll_reg);
+	udelay(40);
+	writel(reg & (~VCOCAL_START), &file->pll_reg);
+
+	/* toggle REG_RCAL_START bit of UTMI_TX */
+	udelay(200);
+	reg = readl(&file->tx_reg);
+	writel(reg | REG_RCAL_START, &file->tx_reg);
+	udelay(40);
+	writel(reg & (~REG_RCAL_START), &file->tx_reg);
+	udelay(200);
+
+	/* make sure phy is ready */
+	count = 1000;
+	while (((readl(&file->pll_reg) & PLL_READY) == 0) && count--)
+		;
+	if (count <= 0)
+		printf("Calibrate timeout, UTMI_PLL %x\n",
+				readl(&file->pll_reg));
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
+#define GPIO10		10
+void reset_cpu(ulong ignored)
+{
+	gpio_direction_output(GPIO10, 1);
+	while (1)
+		;
+}
diff --git a/board/Marvell/guruplug/guruplug.c b/board/Marvell/guruplug/guruplug.c
index 1f0e67a7fe..057c558682 100644
--- a/board/Marvell/guruplug/guruplug.c
+++ b/board/Marvell/guruplug/guruplug.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "guruplug.h"
diff --git a/board/Marvell/mk2/Makefile b/board/Marvell/mk2/Makefile
new file mode 100644
index 0000000000..168b85d89e
--- /dev/null
+++ b/board/Marvell/mk2/Makefile
@@ -0,0 +1,54 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+
+ifneq ($(TARGET_BUILD_VARIANT), user)  
+CFLAGS	+= -DNONUSERBUILD
+COBJS	:= mk2.o max77601.o runscript.o
+else 
+ifeq ($(TARGET_BUILD_DEVMODE), enable)
+CFLAGS	+= -DNONUSERBUILD
+COBJS	:= mk2.o max77601.o runscript.o
+else
+COBJS	:= mk2.o max77601.o
+endif
+endif
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/Marvell/mk2/max77601.c b/board/Marvell/mk2/max77601.c
new file mode 100644
index 0000000000..02700e9ba6
--- /dev/null
+++ b/board/Marvell/mk2/max77601.c
@@ -0,0 +1,185 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+#define KBC_SLAVE_ADDR			0x15
+
+#define MAX77601_SLAVE_ADDR		0x1c
+#define MAX77601_VDVSSD0_REG 		0x1B
+#define MAX77601_CNFG1_L1_REG		0x25
+#define MAX77601_CNFG1_L7_REG		0x31
+#define MAX77601_CNFG_GPIO5		0x3B
+#define MAX77601_AME_GPIO_REG 		0x40
+#define MAX77601_FPS_L1_REG 		0x47
+#define MAX77601_FPS_L7_REG 		0x4D
+
+#define MAX77601_FPSSRC_NOTFPS		(0x3 << 6)
+#define MAX77601_MODE_NORMAL		(0x3 << 6)
+#define MAX77601_L1_1P2V		0x10
+#define MAX77601_L7_1P2V		0x08
+#define MAX77601_VSD3_REG		0x19
+#define MAX77601_SD0_1P25V		0x34
+#define MAX77601_SD3_2P8V		0xB0
+
+#define MAX77601_ONOFFCNFG2		0x42
+#define MAX77601_ONOFFCNFG1		0x41
+#define MAX77601_SFT_RST_WK		0x80
+#define MAX77601_SFT_RST		0x80
+
+#define MAX77601_RTCUPDATE0		0x04
+#define MAX77601_RTCUPDATE1		0x05
+#define MAX77601_RTCSECA2		0x15
+#define MAX77601_UDF			(1 << 0)
+#define MAX77601_RBUDF			(1 << 1)
+#define MAX77601_RBUDR			(1 << 4)
+#define MAX77601_RTC_RETRY_LIMIT	10
+
+void pmic_init(void)
+{
+	u8 data, KBCdata;
+	unsigned int cur_bus = i2c_get_bus_num();
+
+	/* Set i2c bus */
+	i2c_set_bus_num(0);
+
+	//Clear KBC reboot command 0x44
+	//Purpose: In case hang in WTM, KBC will take care the reset action
+	KBCdata = 0x1;
+	i2c_write(KBC_SLAVE_ADDR ,0x45, 1, &KBCdata, 1);//Notify KBC to monitor 0x44
+	KBCdata = 0;
+	i2c_write(KBC_SLAVE_ADDR ,0x44, 1, &KBCdata, 1);//Clear 0x44 to let KBC know have success boot.
+
+	/* set ame for gpio 4/5/7 */
+	data = 0xb0;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_AME_GPIO_REG, 1, &data, 1);
+
+	/* Set GPIO5 active low, VCXO_EN is low when suspend */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_CNFG_GPIO5, 1, &data, 1);
+	data &= ~0x1;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG_GPIO5, 1, &data, 1);
+
+	/* Enable 1.2V pmic_1p2v_mipi (Max77601 LDO1) at first */
+	/* not configured as part of a flexible power sequence */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_FPS_L1_REG, 1, &data, 1);
+	data |= MAX77601_FPSSRC_NOTFPS;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_FPS_L1_REG, 1, &data, 1);
+
+	data = MAX77601_MODE_NORMAL | MAX77601_L1_1P2V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG1_L1_REG, 1, &data, 1);
+
+	/* Then enable 1.2V pmic_1p2v_mipi_logic (Max77601 LDO7)  */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_FPS_L7_REG, 1, &data, 1);
+	data |= MAX77601_FPSSRC_NOTFPS;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_FPS_L7_REG, 1, &data, 1);
+
+	data = MAX77601_MODE_NORMAL | MAX77601_L7_1P2V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_CNFG1_L7_REG, 1, &data, 1);
+
+	/* Restore i2c bus num */
+	i2c_set_bus_num(cur_bus);
+	return;
+}
+
+void pmic_sdmmc_init(void)
+{
+	u8 data;
+	unsigned int cur_bus = i2c_get_bus_num();
+
+	/* Set i2c bus */
+	i2c_set_bus_num(0);
+
+	data = MAX77601_SD3_2P8V;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_VSD3_REG, 1, &data, 1);
+
+	/* Restore i2c bus num */
+	i2c_set_bus_num(cur_bus);
+	return;
+}
+
+void pmic_reset_cpu(void)
+{
+	u8 data, KBCdata;
+
+	i2c_set_bus_num(0);
+
+	//Set KBC reboot command 0x44
+	//Purpose: In case hang in WTM, KBC will take care the reset action without uboot clear 0x44
+	KBCdata = 0x1;
+	i2c_write(KBC_SLAVE_ADDR ,0x44, 1, &KBCdata, 1);
+
+	/* 1. Enable SW reset wake up */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG2, 1, &data, 1);
+	data |= MAX77601_SFT_RST_WK;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG2, 1, &data, 1);
+	/* 2. Issue SW reset */
+	i2c_read(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG1, 1, &data, 1);
+	data |= MAX77601_SFT_RST;
+	i2c_write(MAX77601_SLAVE_ADDR, MAX77601_ONOFFCNFG1, 1, &data, 1);
+
+	udelay(100*1000);
+
+}
+
+void write_recovery_reg(u8 val)
+{
+	int retry = 0;
+	u8 tmp;
+
+	i2c_set_bus_num(0);
+	tmp = val;
+	i2c_write(0x48, MAX77601_RTCSECA2, 1, &tmp, 1);
+
+	tmp = MAX77601_UDF;
+	i2c_write(0x48, MAX77601_RTCUPDATE0, 1, &tmp, 1);
+	while (retry++ < MAX77601_RTC_RETRY_LIMIT) {
+		udelay(20000);
+		i2c_read(0x48, MAX77601_RTCUPDATE1, 1, &tmp, 1);
+		if (tmp & MAX77601_UDF)
+			break;
+	}
+	if (retry >= MAX77601_RTC_RETRY_LIMIT)
+		printf("error in writing max77601-rtc reg!\n");
+}
+
+int read_recovery_reg(void)
+{
+	int retry = 0;
+	u8 tmp;
+
+	i2c_set_bus_num(0);
+	tmp = MAX77601_RBUDR;
+	i2c_write(0x48, MAX77601_RTCUPDATE0, 1, &tmp, 1);
+	while (retry++ < MAX77601_RTC_RETRY_LIMIT) {
+		udelay(20000);
+		i2c_read(0x48, MAX77601_RTCUPDATE1, 1, &tmp, 1);
+		if (tmp & MAX77601_RBUDF)
+			break;
+	}
+	if (retry >= MAX77601_RTC_RETRY_LIMIT)
+{		printf("error in reading max77601-rtc reg!\n");
+		pmic_reset_cpu();
+}
+	i2c_read(0x48, MAX77601_RTCSECA2, 1, &tmp, 1);
+
+	return tmp;
+}
+
diff --git a/board/Marvell/mk2/mk2.c b/board/Marvell/mk2/mk2.c
new file mode 100644
index 0000000000..5256c294da
--- /dev/null
+++ b/board/Marvell/mk2/mk2.c
@@ -0,0 +1,895 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+
+
+#ifdef CONFIG_MV_RECOVERY
+#include <mv_recovery.h>
+#define RECOVERY_KEY	150
+#define RTC_CLK_REG		0xd4015000
+#endif
+#include <malloc.h>
+
+#include <timestamp.h>
+
+#include "../../../../../kernel/kernel/arch/arm/mach-mmp/include/mach/wistron.h"
+
+#if defined(CONFIG_PXA168_FB)
+#include <pxa168fb.h>
+#include <video_fb.h>
+#include "../common/marvell.h"
+#endif
+
+//for mk2
+#define GPIO_V_SD_EN	 	138
+#define GPIO_V_HDMI5V_EN 	160
+#define GPIO_BACKLIGHT_EN	17
+#define GPIO_LCD_3V3		152
+#define GPIO_53_PWM3		53
+#define GPIO_64_GPIO		64
+#define GPIO_68_GPIO		68
+#define GPIO_84_GPIO		84
+#define GPIO_85_GPIO		85
+#define GPIO_19_GPIO		19
+
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MK_FB_XRES		1024
+#define MK_FB_YRES		768
+#define PWM3_BASE		0xD401A800
+#define APB_CLK_REG_BASE	0xD4015000
+
+#define APBC_PWM3_CLK_RST	(APB_CLK_REG_BASE + 0x44)
+#define PWM_CR3		(PWM3_BASE + 0x00)
+#define PWM_DCR		(PWM3_BASE + 0x04)
+#define PWM_PCR		(PWM3_BASE + 0x08)
+
+#if defined(CONFIG_PXA168_FB)
+static struct dsi_info mk2_dsi = {
+	.id = 1,
+	.lanes = 2,
+	.bpp = 24,
+	.burst_mode = DSI_BURST_MODE_SYNC_EVENT,
+	.hbp_en = 1,
+	.hfp_en = 1,
+};
+
+static struct lvds_info lvdsinfo = {
+	.src	= LVDS_SRC_PN,
+	.fmt	= LVDS_FMT_18BIT,
+};
+
+static struct fb_videomode video_modes[] = {
+	[0] = {
+		/* FIXME */
+		.pixclock = 67414,
+		.refresh = 60,
+		.xres = MK_FB_XRES,
+		.yres = MK_FB_YRES,
+		.hsync_len = 10,
+		.left_margin = 160,
+		.right_margin = 200,
+		.vsync_len = 2,
+		.upper_margin = 18,
+		.lower_margin = 18,
+		.sync = FB_SYNC_VERT_HIGH_ACT \
+				  | FB_SYNC_HOR_HIGH_ACT,
+	},
+};
+
+static struct pxa168fb_mach_info mmp_mipi_lcd_info = {
+	.index = 0,
+	.id = "GFX Layer",
+	.sclk_src = 500000000,
+	.sclk_div = 0xe0001210,
+	.num_modes = ARRAY_SIZE(video_modes),
+	.modes = video_modes,
+	.pix_fmt = PIX_FMT_RGB565,
+	.burst_len = 16,
+	/*
+	 * don't care about io_pin_allocation_mode and dumb_mode
+	 * since the panel is hard connected with lcd panel path
+	 * and dsi1 output
+	 */
+	.panel_rgb_reverse_lanes = 0,
+	.invert_composite_blank = 0,
+	.invert_pix_val_ena = 0,
+	.invert_pixclock = 0,
+	.panel_rbswap = 0,
+	.active = 1,
+	.enable_lcd = 1,
+	.spi_gpio_cs = -1,
+	.spi_gpio_reset = -1,
+	.max_fb_size = MK_FB_XRES * MK_FB_YRES * 8 + 4096,
+	.phy_type = DSI2DPI,
+	.phy_info = &mk2_dsi,
+	.twsi_id = 2,
+};
+
+static void lvds_hook(struct pxa168fb_mach_info *mi)
+{
+	mi->phy_type = LVDS;
+	mi->phy_info = (void *)&lvdsinfo;
+}
+
+#define LCD_P_GPIO17		17
+static void en_bl_power(int on)
+{
+	if (on)
+		gpio_direction_output(LCD_P_GPIO17, 1);
+	else
+		gpio_direction_output(LCD_P_GPIO17, 0);
+}
+
+#define VLCD_3V3_GPIO152	152
+static void lcd_power_en(int on)
+{
+	if (on) {
+		gpio_direction_output(VLCD_3V3_GPIO152, 1);
+		gpio_direction_output(LCD_RST_GPIO, 1);
+	} else
+		gpio_direction_output(VLCD_3V3_GPIO152, 0);
+}
+
+static void set_pwm_en(int en)
+{
+	unsigned long data;
+
+	if (en) {
+		data = __raw_readl(APBC_PWM3_CLK_RST) & ~(0x7 << 4);
+		data |= 1 << 1;
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+
+		/* delay two cycles of the solwest clock between the APB bus
+		 * clock and the functional module clock. */
+		udelay(10);
+
+		/* enable APB bus clk */
+		data |= 1;
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+
+		/* release from reset */
+		data &= ~(1 << 2);
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+	} else {
+		data = __raw_readl(APBC_PWM3_CLK_RST) & ~(0x1 << 1 | 0x7 << 4);
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+		udelay(1000);
+
+		data &= ~(1);
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+		udelay(1000);
+
+		data |= 1 << 2;
+		__raw_writel(data, APBC_PWM3_CLK_RST);
+	}
+}
+
+static void turn_off_backlight(void)
+{
+	__raw_writel(0, PWM_CR3);
+	__raw_writel(0, PWM_DCR);
+
+	/* disable pwm */
+	set_pwm_en(0);
+
+	/* disable backlight power */
+	en_bl_power(0);
+}
+
+static void turn_on_backlight(void)
+{
+	int duty_ns = 1000000, period_ns = 2000000;
+	unsigned long period_cycles, prescale, pv, dc;
+
+	/* enable pwm */
+	set_pwm_en(1);
+
+	period_cycles = 52000;
+	if (period_cycles < 1)
+		period_cycles = 1;
+
+	prescale = (period_cycles - 1) / 1024;
+	pv = period_cycles / (prescale + 1) - 1;
+
+	if (prescale > 63)
+		return;
+
+	if (duty_ns == period_ns)
+		dc = (1 << 10);
+	else
+		dc = (pv + 1) * duty_ns / period_ns;
+
+	__raw_writel(prescale, PWM_CR3);
+	__raw_writel(dc, PWM_DCR);
+	__raw_writel(pv, PWM_PCR);
+
+	/* enable backlight power */
+	en_bl_power(1);
+}
+
+static GraphicDevice ctfb;
+void *lcd_init(void)
+{
+	void *ret;
+	int lvds_en = 0;
+	int mode = 1;
+
+//	turn_off_backlight();
+//	lcd_power_en(1);
+
+	
+	gpio_direction_input(GPIO_19_GPIO);
+	mode = gpio_get_value(GPIO_19_GPIO);
+	lvds_en = !mode;
+
+	/* disable lvds interface by default */
+	if (cpu_is_bx() && lvds_en)
+		lvds_hook(&mmp_mipi_lcd_info);
+
+	ret = (void *)pxa168fb_init(&mmp_mipi_lcd_info);
+
+//	turn_on_backlight();
+	return ret;
+}
+
+void *video_hw_init(void)
+{
+	struct pxa168fb_info *fbi;
+	struct fb_var_screeninfo *var;
+	unsigned long t1, hsynch, vsynch;
+	fbi = lcd_init();
+	var = fbi->var;
+
+	ctfb.winSizeX = var->xres;
+	ctfb.winSizeY = var->yres;
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (var->left_margin + var->xres +
+	      var->right_margin + var->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= var->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (var->upper_margin + var->yres +
+	       var->lower_margin + var->vsync_len);
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(ctfb.modeIdent, "%dx%dx%d %ldkHz %ldHz", ctfb.winSizeX,
+		ctfb.winSizeY, var->bits_per_pixel, (hsynch / 1000),
+		vsynch);
+
+	ctfb.frameAdrs = (unsigned int) fbi->fb_start;
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 2;
+	ctfb.gdfIndex = GDF_16BIT_565RGB;
+
+	ctfb.isaBase = 0x9000000;
+	ctfb.pciBase = (unsigned int) fbi->fb_start;
+	ctfb.memSize = fbi->fb_size;
+
+	/* Cursor Start Address */
+	ctfb.dprBase = (unsigned int) fbi->fb_start + (ctfb.winSizeX \
+			* ctfb.winSizeY * ctfb.gdfBytesPP);
+	if ((ctfb.dprBase & 0x0fff) != 0) {
+		/* allign it */
+		ctfb.dprBase &= 0xfffff000;
+		ctfb.dprBase += 0x00001000;
+	}
+	ctfb.vprBase = (unsigned int) fbi->fb_start;
+	ctfb.cprBase = (unsigned int) fbi->fb_start;
+
+	return &ctfb;
+}
+#endif
+
+#if 0
+#if defined(CONFIG_PXA168_FB)
+static struct dsi_info abilene_dsi = {
+	.id			= 1,
+	.lanes			= 2,
+	.bpp			= 24,
+	.burst_mode		= DSI_BURST_MODE_SYNC_EVENT,
+	.hbp_en			= 1,
+	.hfp_en			= 1,
+};
+
+static struct fb_videomode video_modes[] = {
+	[0] = {
+		.pixclock	= 62500,
+		.refresh	= 60,
+		.xres		= FB_XRES,
+		.yres		= FB_YRES,
+		.hsync_len	= 2,
+
+		.left_margin	= 10,
+		.right_margin	= 116,
+		.vsync_len	= 2,
+		.upper_margin	= 10,
+		.lower_margin	= 4,
+		.sync		= FB_SYNC_VERT_HIGH_ACT \
+				  | FB_SYNC_HOR_HIGH_ACT,
+	},
+};
+
+static struct pxa168fb_mach_info mmp2_mipi_lcd_info = {
+	.id			= "GFX Layer",
+	.sclk_src		= 500000000,
+	.sclk_div		= 0xe0001210,
+	.num_modes		= ARRAY_SIZE(video_modes),
+	.modes			= video_modes,
+	.pix_fmt		= PIX_FMT_RGB565,
+	.burst_len		= 16,
+	/*
+	 * don't care about io_pin_allocation_mode and dumb_mode
+	 * since the panel is hard connected with lcd panel path
+	 * and dsi1 output
+	 */
+	.panel_rgb_reverse_lanes = 0,
+	.invert_composite_blank = 0,
+	.invert_pix_val_ena     = 0,
+	.invert_pixclock        = 0,
+	.panel_rbswap           = 0,
+	.active			= 1,
+	.enable_lcd             = 1,
+	.spi_gpio_cs            = -1,
+	.spi_gpio_reset         = -1,
+	.max_fb_size		= FB_XRES * FB_YRES * 8 + 4096,
+	.phy_type		= DSI2DPI,
+	.dsi			= &abilene_dsi,
+};
+#endif
+
+#if defined(CONFIG_PXA168_FB)
+static GraphicDevice ctfb;
+void *lcd_init(void)
+{
+	void *ret;
+
+	ret = (void *)pxa168fb_init(&mmp2_mipi_lcd_info);
+	return ret;
+}
+
+void *video_hw_init(void)
+{
+	struct pxa168fb_info *fbi;
+	struct fb_var_screeninfo *var;
+	unsigned long t1, hsynch, vsynch;
+	fbi = lcd_init();
+	var = fbi->var;
+
+	ctfb.winSizeX = var->xres;
+	ctfb.winSizeY = var->yres;
+
+	/* calculate hsynch and vsynch freq (info only) */
+	t1 = (var->left_margin + var->xres +
+	      var->right_margin + var->hsync_len) / 8;
+	t1 *= 8;
+	t1 *= var->pixclock;
+	t1 /= 1000;
+	hsynch = 1000000000L / t1;
+	t1 *= (var->upper_margin + var->yres +
+	       var->lower_margin + var->vsync_len);
+	vsynch = 1000000000L / t1;
+
+	/* fill in Graphic device struct */
+	sprintf(ctfb.modeIdent, "%dx%dx%d %ldkHz %ldHz", ctfb.winSizeX,
+		ctfb.winSizeY, var->bits_per_pixel, (hsynch / 1000),
+		vsynch);
+
+	ctfb.frameAdrs = (unsigned int) fbi->fb_start;
+	ctfb.plnSizeX = ctfb.winSizeX;
+	ctfb.plnSizeY = ctfb.winSizeY;
+
+	ctfb.gdfBytesPP = 2;
+	ctfb.gdfIndex = GDF_16BIT_565RGB;
+
+	ctfb.isaBase = 0x9000000;
+	ctfb.pciBase = (unsigned int) fbi->fb_start;
+	ctfb.memSize = fbi->fb_size;
+
+	/* Cursor Start Address */
+	ctfb.dprBase = (unsigned int) fbi->fb_start + (ctfb.winSizeX \
+			* ctfb.winSizeY * ctfb.gdfBytesPP);
+	if ((ctfb.dprBase & 0x0fff) != 0) {
+		/* allign it */
+		ctfb.dprBase &= 0xfffff000;
+		ctfb.dprBase += 0x00001000;
+	}
+	ctfb.vprBase = (unsigned int) fbi->fb_start;
+	ctfb.cprBase = (unsigned int) fbi->fb_start;
+
+	return &ctfb;
+}
+#endif
+#endif
+
+#include <mmp_freq.h>
+
+static u32 boardid;
+static u8 boardrev, boardtype;
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* Enable TWSI1 for PMIC */
+		TWSI1_SCL,
+		TWSI1_SDA,
+
+		/* Enable TWSI3 for TC35876X*/
+		TWSI3_SCL,
+		TWSI3_SDA,
+
+		/* Enable TWSI5 */
+		TWSI5_SCL,
+		TWSI5_SDA,
+
+		/* Enable TWSI6 */
+		TWSI6_SCL,
+		TWSI6_SDA,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+		MMC1_WP,
+		MMC1_GPIO138, /* GPIO_V_SD_EN */
+
+		/* Enable LCD, gpio128*/
+		LCD_RESET,
+		GPIO152_VLCD_3V3,
+
+		/* Back light PWM3, gpio53, gpio17 */
+//		BACK_LIGHT_PWM3,
+//		BL_POWER_EN,
+
+		/* MMC3 */
+		MMC3_DATA7_NDIO15,
+		MMC3_DATA6_NDIO14,
+		MMC3_DATA5_NDIO12,
+		MMC3_DATA4_NDIO10,
+		MMC3_DATA3_NDIO8,
+		MMC3_DATA2_NDIO13,
+		MMC3_DATA1_NDIO11,
+		MMC3_DATA0_NDIO9,
+		MMC3_CLK_SMNCS1,
+		MMC3_CMD_SMNCS0,
+
+		MFP_GPIO150,
+
+ 		/* HDMI 5V enable define */
+ 		GPIO_160,
+ 
+ 		/* Backlight enable*/
+ 		GPIO_17,
+		/* LVDS mode detection pin*/
+		GPIO_19, 
+ 		/*PWM3 for brightness*/
+ //		GPIO53_PWM3,
+ 		GPIO53_GPIO,
+		GPIO_147,
+		/*Modem power control pins, William Liu*/
+		GPIO93_GPIO,
+		GPIO94_GPIO,
+		GPIO95_GPIO,
+		GPIO129_GPIO,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+
+	return 0;
+}
+
+#define MACH_TYPE_MK2	3497
+#define FASTBOOT_KEY	147
+extern void pmic_init(void);
+extern void pmic_sdmmc_init(void);
+extern void pmic_reset_cpu(void);
+int board_init(void)
+{
+#if defined(CONFIG_PXA168_FB)
+	/* TC358765 reset */
+	gpio_direction_output(LCD_RST_GPIO, 0);
+	udelay(1000);
+#endif
+	/* OEM UniqueID in the NTIM
+	 * 32bit format: NN NN NN TV
+	 * NNNNNN: board name
+	 *	0x594553 (YES, YellowStone)
+	 *	0x414249 (ABI, Abilene)
+	 *	0x4f5243 (ORC, Orchid)
+	 *	0x4d4b32 (MK2, MK2)
+	 * T: type
+	 *	0x1 (Pop board)
+	 *	0x0 (Discrete board)
+	 * V: revision
+	*/
+	boardid = *(volatile unsigned int *)0xd1020010;
+	boardrev = boardid & 0xF;
+	boardtype = (boardid >> 4) & 0xF;
+	boardid = boardid >> 8;
+
+	if (boardid == 0x4d4b32)
+		gd->bd->bi_arch_number = MACH_TYPE_MK2;
+
+	pmic_init();
+
+	gpio_direction_input(FASTBOOT_KEY);
+
+
+#ifdef CONFIG_MV_RECOVERY
+	gpio_direction_input(RECOVERY_KEY);
+	/* release RTC from reset state to support recovery function */
+	__raw_writel(0x81, RTC_CLK_REG);
+	/* read magic key from WTM */
+	magic_read();
+#endif
+
+	/* for MK2, it will use GPIO_138 for the V_SD_EN */
+	gpio_direction_output(GPIO_V_SD_EN, 1);
+
+	// for MK2, use GPIO_160 for th  V_HDMI5v
+	gpio_direction_output(GPIO_V_HDMI5V_EN, 0);
+
+	gpio_direction_output(GPIO_BACKLIGHT_EN, 0);
+
+	gpio_direction_output(GPIO_53_PWM3, 0);
+
+	gpio_direction_output(GPIO_LCD_3V3, 1);
+
+/* Both GPIO129, GPIO95 and GPIO94 should be in low state
+ * BB_WAKE should keep floating (there is an external pull high). 
+ */
+	gpio_direction_output(93, 0); // BB_WAKE
+	gpio_direction_output(94, 0); // BB_ENABLE
+	gpio_direction_output(95, 0); // BB_RST
+	gpio_direction_output(129, 0); // 3.3V rail
+	printf("Start modem power on delay");
+	udelay(500000);
+	return 0;
+}
+
+#if defined(CONFIG_PXA168_FB)
+void show_logo(void)
+{
+#if 0
+	char cmd[100];
+	int wide, high;
+
+	/* Show marvell logo */
+	wide = 213;
+	high = 125;
+	sprintf(cmd, "bmp display %p %d %d", MARVELL, \
+		(FB_XRES - wide) / 2, (FB_YRES - high) / 2);
+	run_command(cmd, 0);
+#endif
+#define BASE_ADDR       0x02500000
+#define NEW_BASE_ADDR   0x02800000
+        struct mmc *mmc_0;
+        unsigned char bmp_header[54];
+        mmc_0 = find_mmc_device(0);
+        if (mmc_0) {
+                if (mmc_init(mmc_0)){
+                        printf("MMC 0 card init failed!\n");
+                        return 0;
+                }
+        }
+
+        mmc_switch_part(0, 0);
+	//mmc_0->block_dev.block_read(0, 0x2000, 0x1201, (const void *)BASE_ADDR);
+        //mmc_0->block_dev.block_read(0, 0xcc00, 0xC01, (const void *)BASE_ADDR);
+	mmc_0->block_dev.block_read(0, 0x2000, 0xC01, (const void *)BASE_ADDR);
+        memcpy(bmp_header, (const void *)BASE_ADDR, 54);
+        //memcpy((void *)DEFAULT_FB_BASE, (void const *)(BASE_ADDR + bmp_header[0xa]), 0x240000);//remove bmp header
+        memcpy((void *)DEFAULT_FB_BASE, (void const *)(BASE_ADDR + bmp_header[0xa]), 0x18000c);//remove bmp header
+
+
+}
+
+
+void show_fastlogo(void)
+{
+        char cmd[100];
+        int wide, high;
+
+        /* Show marvell logo */
+        wide = 213;
+        high = 125;
+	//printf("FB_XRES is %d\r\n", FB_XRES);
+        sprintf(cmd, "bmp display %p %d %d", MARVELL, \
+                (FB_XRES - wide) / 2, (FB_YRES - high) / 2);
+        run_command(cmd, 0);
+}
+
+void lcd_blank(void)
+{
+	memset((unsigned short *) DEFAULT_FB_BASE, 0x0, ctfb.memSize);
+}
+#endif
+
+
+
+#ifdef CONFIG_MV_WTM
+static int profile_map[] = {0x0, 0xffff, 0x3fff, 0xfff, 0x3ff, 0xff, 0x3f, 0xf, 0x3, 0x1};
+extern unsigned int mv_profile;
+#endif
+
+int misc_init_r(void)
+{
+	int i, sz;
+
+#if defined(CONFIG_PXA168_FB)
+	{
+	//printf("147 is HIGH\r\n");
+	show_logo();
+	}
+#endif
+
+	if (boardid == 0x4d4b32)
+		printf("\nBoard: MK2 (%s)\n",
+			boardtype ? "Pop" : "Discrete");
+
+	gpio_set_value(GPIO_BACKLIGHT_EN, 1);
+	gpio_set_value(GPIO_53_PWM3, 1);
+
+#ifdef CONFIG_MV_WTM
+	dcache_disable();
+	wtm_read_profile();
+	wtm_read_stepping();
+	dcache_enable();
+	wtm_dump_info();
+	for (i = 0; i < 10; i++) {
+		if (profile_map[i] == mv_profile)
+			mv_profile = i;
+	}
+	printf("Soc profile: p%d\n", mv_profile);
+#endif
+
+	gd->bd->bi_boot_params = (ulong) malloc(CONFIG_SYS_BOOTPARAMS_LEN);
+
+#if defined(CONFIG_MMP_POWER)
+	set_volt(1250);	/* set 1.25v for vcc_core */
+	setop(18); 	/* set op for 1GHz */
+#endif
+
+	/* set bootargs */
+	setenv("bootargs", CONFIG_BOOTARGS);
+	/* reserve 192M pmem if the memory is larger than 512M
+	 * reserve 96M otherwise */
+	for (i = 0, sz = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		sz += gd->bd->bi_dram[i].size;
+	if (sz > 0x20000000)
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xc000000", 0);
+	else
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xA000000", 0);
+
+	setenv("fbenv", "mmc0");
+#ifdef CONFIG_MV_RECOVERY
+	mv_recovery();
+#endif
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i;
+
+	/*
+	 * Set 2.8V power (pmic_sdmmc - max77601_SD3) for sd/mmc
+	 * The power domain is shared with other components' power
+	 * the voltage should be 2.8V on B0, will default enabled when
+	 * booting up
+	 */
+	pmic_sdmmc_init();
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+		writel(CLK_GATE_ON | CLK_GATE_CTL \
+		       | WTC(WTC_DEF) | RTC(RTC_DEF),
+		       mmc_base_address[i] + SD_FIFO_PARAM);
+		writew(WR_ENDIAN | RD_ENDIAN \
+			| DMA_SIZE(DMA_FIFO_128) | BURST_SIZE(BURST_64),
+			mmc_base_address[i] + SD_CLOCK_AND_BURST_SIZE_SETUP);
+		writel(TUNING_DLY_INC(0x1f) | SDCLK_DELAY(0x1f),
+			mmc_base_address[i] + RX_CFG_REG);
+	}
+
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+	pmic_reset_cpu();
+}
+
+#ifdef CONFIG_MV_RECOVERY
+inline int magic_key_detect_recovery(void)
+{
+	/* If Volumn down key is pressed, go recovery flow */
+	if (!gpio_get_value(RECOVERY_KEY))
+		return 1;
+	else
+		return 0;
+}
+#endif
+
+void arch_preboot_os(void)
+{
+#if defined(CONFIG_PXA168_FB)
+//	lcd_blank();
+//	turn_off_backlight();
+#endif
+}
+
+/*
+ * USB Ethernet
+ */
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count;
+
+	if (cpu_is_ax()) {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK | REFDIV_MASK),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | VDD12(1)
+			   | REFDIV(0xd) | FB_DIV(0xf0)), &file->pll_reg0);
+	} else {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK_B0 | REFDIV_MASK_B0),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | REFDIV_B0(0xd)
+		       | FB_DIV_B0(0xf0)), &file->pll_reg0);
+	}
+
+	writel(readl(&file->pll_reg1) & ~(UTMI_PLL_PU | PLL_ICP_MASK
+	       | PLL_KVCO_MASK | PLL_CALI12_MASK), &file->pll_reg1);
+	writel(readl(&file->pll_reg1) | (UTMI_PLL_PU | PLL_ICP(2)
+	       | PLL_KVCO(3) | PLL_CALI12(3)), &file->pll_reg1);
+
+
+	writel(readl(&file->tx_reg0) & ~IMPCAL_VTH_MASK, &file->tx_reg0);
+	writel(readl(&file->tx_reg0) | IMPCAL_VTH(2), &file->tx_reg0);
+
+	writel(readl(&file->tx_reg1) & ~(CK60_PHSEL_MASK | AMP_MASK
+	       | TX_VDD12_MASK), &file->tx_reg1);
+	writel(readl(&file->tx_reg1) | (CK60_PHSEL(4) | AMP(4)
+	       | TX_VDD12(3)), &file->tx_reg1);
+
+	writel(readl(&file->tx_reg2) & ~DRV_SLEWRATE(3), &file->tx_reg2);
+	writel(readl(&file->tx_reg2) | DRV_SLEWRATE(3), &file->tx_reg2);
+
+	writel(readl(&file->rx_reg0) & ~(SQ_LENGTH_MASK | SQ_THRESH_MASK),
+	       &file->rx_reg0);
+	writel(readl(&file->rx_reg0) | (SQ_LENGTH(0x2) | SQ_THRESH(0xa)),
+	       &file->rx_reg0);
+
+	writel(readl(&file->ana_reg1) | ANA_PU, &file->ana_reg1);
+
+	writel(readl(&file->otg_reg0) | PU_OTG, &file->otg_reg0);
+
+	udelay(200);
+	writel(readl(&file->pll_reg1) | VCOCAL_START, &file->pll_reg1);
+
+	udelay(200);
+	writel(readl(&file->tx_reg0) | RCAL_START, &file->tx_reg0);
+	udelay(40);
+	writel(readl(&file->tx_reg0) & ~RCAL_START, &file->tx_reg0);
+	udelay(400);
+
+	/* make sure phy is ready */
+	count = 100;
+	while (((readl(&file->pll_reg1) & PLL_READY) == 0) && count--)
+		udelay(1000);
+	if (count <= 0) {
+		printf("%s %d: calibrate timeout, UTMI_PLL %x\n",
+				__func__, __LINE__, readl(&file->pll_reg1));
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
+
+int board_late_init(void){
+
+	char kernel_parameter[512];
+
+	gpio_direction_output(GPIO_64_GPIO, 1);
+	gpio_set_value(GPIO_64_GPIO, 1);
+
+	gpio_direction_output(GPIO_68_GPIO, 1);
+	gpio_set_value(GPIO_68_GPIO, 1);
+
+	gpio_direction_output(GPIO_84_GPIO, 0);
+	gpio_set_value(GPIO_84_GPIO, 0);
+
+	gpio_direction_output(GPIO_85_GPIO, 0);
+	gpio_set_value(GPIO_85_GPIO, 0);
+
+#if 1	//Read customer serial number and pass to kernel
+	struct mmc *mmc_0;
+	char nvs_block[EMMC_BLOCK_SIZE];  
+	mmc_0 = find_mmc_device(0);
+        if (mmc_0) {
+                if (mmc_init(mmc_0)){
+                        printf("MMC 0 card init failed!\n");
+                        return 0;
+                }
+        }
+
+	mmc_switch_part(0, 0);
+	mmc_0->block_dev.block_read(0, NVS_OFFSET/EMMC_BLOCK_SIZE, 1, (struct WISTRON_NVS *)nvs_block);
+	
+	struct WISTRON_NVS *wis_nvs = nvs_block;
+
+	//empty serial number will cause problem in Android. Work around to avoid this.
+	if(strlen(wis_nvs->sn_customer) == 0)
+		strcpy(wis_nvs->sn_customer, "FZA1B");
+#endif
+	sprintf(kernel_parameter, 
+		"androidboot.console=ttyS2 console=ttyS2,115200 panic_debug reserve_pmem=0xc000000 emmc_boot fb_share \
+androidboot.bootloader=%s  androidboot.serialno=%s androidboot.baseband=%s", U_BOOT_DATE, wis_nvs->sn_customer,wis_nvs->baseband);
+	setenv("bootargs", kernel_parameter);
+}
diff --git a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
index 80fd20b7f4..4c41f3b2ef 100644
--- a/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
+++ b/board/Marvell/mv88f6281gtw_ge/mv88f6281gtw_ge.c
@@ -26,6 +26,7 @@
 
 #include <common.h>
 #include <netdev.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "mv88f6281gtw_ge.h"
diff --git a/board/Marvell/openrd/openrd.c b/board/Marvell/openrd/openrd.c
index 87939decf3..2a10e69faf 100644
--- a/board/Marvell/openrd/openrd.c
+++ b/board/Marvell/openrd/openrd.c
@@ -29,6 +29,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "openrd.h"
diff --git a/board/Marvell/orchid/Makefile b/board/Marvell/orchid/Makefile
new file mode 100644
index 0000000000..f6d8230d12
--- /dev/null
+++ b/board/Marvell/orchid/Makefile
@@ -0,0 +1,43 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= orchid.o pm800.o
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
diff --git a/board/Marvell/orchid/orchid.c b/board/Marvell/orchid/orchid.c
new file mode 100644
index 0000000000..5b3c69c8f8
--- /dev/null
+++ b/board/Marvell/orchid/orchid.c
@@ -0,0 +1,274 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+extern int pmic_init(void);
+
+/*
+ * Basic support
+ */
+static u32 boardid;
+static u8 boardrev, boardtype;
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* Enable TWSI5 */
+		TWSI5_SCL,
+		TWSI5_SDA,
+
+		/* Enable TWSI6 */
+		TWSI6_SCL,
+		TWSI6_SDA,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+
+		/* MMC3 */
+		MMC3_DATA7_NDIO15,
+		MMC3_DATA6_NDIO14,
+		MMC3_DATA5_NDIO12,
+		MMC3_DATA4_NDIO10,
+		MMC3_DATA3_NDIO8,
+		MMC3_DATA2_NDIO13,
+		MMC3_DATA1_NDIO11,
+		MMC3_DATA0_NDIO9,
+		MMC3_CLK_SMNCS1,
+		MMC3_CMD_SMNCS0,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+
+	return 0;
+}
+
+#define MACH_TYPE_ORCHID	3498
+#define FASTBOOT_KEY_IN 8
+#define FASTBOOT_KEY_OUT 9
+int board_init(void)
+{
+	/* OEM UniqueID in the NTIM
+	 * 32bit format: NN NN NN TV
+	 * NNNNNN: board name
+	 *	0x594553 (YES, YellowStone)
+	 *	0x414249 (ABI, Abilene)
+	 *	0x4f5243 (ORC, Orchid)
+	 * T: type
+	 *	0x1 (Pop board)
+	 *	0x0 (Discrete board)
+	 * V: revision
+	*/
+	boardid = *(volatile unsigned int *)0xd1020010;
+	boardrev = boardid & 0xF;
+	boardtype = (boardid >> 4) & 0xF;
+	boardid = boardid >> 8;
+
+	if (boardid == 0x4f5243)
+		gd->bd->bi_arch_number = MACH_TYPE_ORCHID;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x3c00;
+
+	/* use sw1 as fastboot key */
+	gpio_direction_input(FASTBOOT_KEY_IN);
+	gpio_direction_output(FASTBOOT_KEY_OUT, 0);
+
+	return 0;
+}
+
+int misc_init_r(void)
+{
+	int i, sz;
+
+	if (boardid == 0x4f5243)
+		printf("\nBoard: Orchid (%s)\n",
+			boardtype ? "Pop" : "Discrete");
+
+	/* init pmic: BUCKS, LDOs, watch dog... */
+	pmic_init();
+
+#if defined(CONFIG_MMP_POWER)
+	set_volt(1250);	/* set 1.25v for vcc_core */
+	setop(16); 	/* set op for 800MHz */
+#endif
+
+	/* set bootargs */
+	setenv("bootargs", CONFIG_BOOTARGS);
+	/* reserve 192M pmem if the memory is larger than 512M
+	 * reserve 96M otherwise */
+	for (i = 0, sz = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		sz += gd->bd->bi_dram[i].size;
+	if (sz > 0x20000000)
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xc000000", 0);
+	else
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xA000000", 0);
+
+	setenv("fbenv", "mmc0");
+
+	if (!gpio_get_value(FASTBOOT_KEY_IN))
+		run_command("fb", 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i;
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+		writel(DIS_PAD_SD_CLK_GATE | CLK_GATE_ON | CLK_GATE_CTL \
+		       | WTC(WTC_DEF) | RTC(RTC_DEF),
+		       mmc_base_address[i] + SD_FIFO_PARAM);
+
+		writew(SDCLK_DELAY(0x1f) | SDCLK_SEL | WR_ENDIAN | RD_ENDIAN \
+		       | DMA_SIZE(DMA_FIFO_128) | BURST_SIZE(BURST_64),
+		       mmc_base_address[i] + SD_CLOCK_AND_BURST_SIZE_SETUP);
+	}
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+	unsigned int cur_bus = i2c_get_bus_num();
+	u8 addr = 0x30, reg, data;
+
+	i2c_set_bus_num(0);
+	/* 1.Enable FAULT_WU and FAULT_WU_EN */
+	reg = 0xE7;
+	i2c_read(addr, reg, 1, &data, 1);
+	data |= ((1 << 3) | (1 << 2));
+	i2c_write(addr, reg, 1, &data, 1);
+	/* 2.Issue SW power down */
+	reg = 0x0D;
+	data = 0x20;
+	i2c_write(addr, reg, 1, &data,  1);
+	i2c_set_bus_num(cur_bus);
+}
+
+/*
+ * USB Ethernet
+ */
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count;
+
+	if (cpu_is_ax()) {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK | REFDIV_MASK),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | VDD12(1) |
+				REFDIV(0xd) | FB_DIV(0xf0)), &file->pll_reg0);
+	} else {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK_B0 | REFDIV_MASK_B0),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | REFDIV_B0(0xd)
+		       | FB_DIV_B0(0xf0)), &file->pll_reg0);
+	}
+	writel(readl(&file->pll_reg1) & ~(UTMI_PLL_PU | PLL_ICP_MASK
+	       | PLL_KVCO_MASK | PLL_CALI12_MASK), &file->pll_reg1);
+	writel(readl(&file->pll_reg1) | (UTMI_PLL_PU | PLL_ICP(2)
+	       | PLL_KVCO(3) | PLL_CALI12(3)), &file->pll_reg1);
+
+
+	writel(readl(&file->tx_reg0) & ~IMPCAL_VTH_MASK, &file->tx_reg0);
+	writel(readl(&file->tx_reg0) | IMPCAL_VTH(2), &file->tx_reg0);
+
+	writel(readl(&file->tx_reg1) & ~(CK60_PHSEL_MASK | AMP_MASK
+	       | TX_VDD12_MASK), &file->tx_reg1);
+	writel(readl(&file->tx_reg1) | (CK60_PHSEL(4) | AMP(4)
+	       | TX_VDD12(3)), &file->tx_reg1);
+
+	writel(readl(&file->tx_reg2) & ~DRV_SLEWRATE(3), &file->tx_reg2);
+	writel(readl(&file->tx_reg2) | DRV_SLEWRATE(3), &file->tx_reg2);
+
+	writel(readl(&file->rx_reg0) & ~(SQ_LENGTH_MASK | SQ_THRESH_MASK),
+	       &file->rx_reg0);
+	writel(readl(&file->rx_reg0) | (SQ_LENGTH(0x2) | SQ_THRESH(0xa)),
+	       &file->rx_reg0);
+
+	writel(readl(&file->ana_reg1) | ANA_PU, &file->ana_reg1);
+
+	writel(readl(&file->otg_reg0) | PU_OTG, &file->otg_reg0);
+
+	udelay(200);
+	writel(readl(&file->pll_reg1) | VCOCAL_START, &file->pll_reg1);
+
+	udelay(200);
+	writel(readl(&file->tx_reg0) | RCAL_START, &file->tx_reg0);
+	udelay(40);
+	writel(readl(&file->tx_reg0) & ~RCAL_START, &file->tx_reg0);
+	udelay(400);
+
+	/* make sure phy is ready */
+	count = 100;
+	while (((readl(&file->pll_reg1) & PLL_READY) == 0) && count--)
+		udelay(1000);
+	if (count <= 0) {
+		printf("%s %d: calibrate timeout, UTMI_PLL %x\n",
+				__func__, __LINE__, readl(&file->pll_reg1));
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
diff --git a/board/Marvell/orchid/pm800.c b/board/Marvell/orchid/pm800.c
new file mode 100644
index 0000000000..e3671a3c5d
--- /dev/null
+++ b/board/Marvell/orchid/pm800.c
@@ -0,0 +1,157 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* Base Page */
+#define PM800_BASE_PAGE	0x30
+
+#define PM800_CHIP_ID	0x00
+
+#define PM800_WAKEUP1	0x0D
+#define PM800_WAKEUP2	0x0E
+
+/* Power Page */
+#define PM800_POWER_PAGE	0x31
+
+#define VBUCK_EN_REG	0x50
+#define LDO_EN_REG1	0x51
+#define LDO_EN_REG2	0x52
+#define LDO_EN_REG3	0x53
+
+#define LDO13_EN (1<<4)
+#define LDO15_EN (1<<6)
+#define LDO16_EN (1<<7)
+#define LDO17_EN (1<<0)
+
+#define VBUCK1_SET_REG	0x3C
+#define VBUCK2_SET_REG	0x40
+#define VBUCK3_SET_REG	0x41
+#define VBUCK4_SET_REG	0x42
+#define VBUCK5_SET_REG	0x43
+
+#define LDO1_SET_REG	0x08
+#define LDO2_SET_REG	0x0B
+#define LDO3_SET_REG	0x0C
+#define LDO4_SET_REG	0x0D
+#define LDO5_SET_REG	0x0E
+#define LDO6_SET_REG	0x0F
+#define LDO7_SET_REG	0x10
+#define LDO8_SET_REG	0x11
+#define LDO9_SET_REG	0x12
+#define LDO10_SET_REG	0x13
+#define LDO11_SET_REG	0x14
+#define LDO12_SET_REG	0x15
+#define LDO13_SET_REG	0x16
+#define LDO14_SET_REG	0x17
+#define LDO15_SET_REG	0x18
+#define LDO16_SET_REG	0x19
+#define LDO17_SET_REG	0x1A
+#define LDO18_SET_REG	0x1B
+#define LDO19_SET_REG	0x1C
+
+/* Procida Chip ID */
+enum {
+	PM800_CHIP_A0  = 0x60,
+	PM800_CHIP_A1  = 0x61,
+	PM800_CHIP_B0  = 0x62,
+	PM800_CHIP_C0  = 0x63,
+};
+
+static inline int pm800_read_reg_power(u8 reg, u8 *val)
+{
+	return i2c_read(PM800_POWER_PAGE, reg, 1, val, 1);
+}
+
+static inline int pm800_write_reg_power(u8 reg, u8 val)
+{
+	return i2c_write(PM800_POWER_PAGE, reg, 1, &val, 1);
+}
+
+static inline int pm800_read_reg_base(u8 reg, u8 *val)
+{
+	return i2c_read(PM800_BASE_PAGE, reg, 1, val, 1);
+}
+
+static inline int pm800_write_reg_base(u8 reg, u8 val)
+{
+	return i2c_write(PM800_BASE_PAGE, reg, 1, &val, 1);
+}
+
+static int pm800_voltage_init(void)
+{
+	int ret = 0;
+	u8 val;
+
+	/* enable buck2 (1.25v) for lpddr2 */
+	val = 0x34;
+	ret |= pm800_write_reg_power(VBUCK2_SET_REG, val);
+
+	/* enable buck5 (1.25v) for wukong */
+	val = 0x34;
+	ret |= pm800_write_reg_power(VBUCK5_SET_REG, val);
+
+	/* enable ldo17 */
+	ret |= pm800_read_reg_power(LDO_EN_REG3, &val);
+	val |= LDO17_EN;
+	ret |= pm800_write_reg_power(LDO_EN_REG3, val);
+
+	/* enable ldo16 (3.3v) for wifi */
+	val = 0xff;
+	ret |= pm800_write_reg_power(LDO16_SET_REG, val);
+
+	/* enable ldo13, ldo15, ldo16 */
+	ret |= pm800_read_reg_power(LDO_EN_REG2, &val);
+	val |= LDO13_EN | LDO15_EN | LDO16_EN;
+	ret |= pm800_write_reg_power(LDO_EN_REG2, val);
+
+	return ret;
+}
+
+static int pm800_disable_watch_dog(void)
+{
+	int ret = 0;
+
+	/* Set WD_TIMER_COUNT to 0 */
+	ret |= pm800_write_reg_base(PM800_WAKEUP2, 0x0);
+	/* Reset watch dog timer */
+	ret |= pm800_write_reg_base(PM800_WAKEUP1, 0x10);
+	return ret;
+}
+
+int pmic_init(void)
+{
+	int ret = 0;
+	unsigned int cur_bus = i2c_get_bus_num();
+	u8 val;
+	/* Set i2c bus */
+	i2c_set_bus_num(0);
+	ret |= pm800_read_reg_base(PM800_CHIP_ID, &val);
+	printf("Procida Chip ID: 0x%x\n", val);
+	/* Disable Watch Dog */
+	if (val < PM800_CHIP_C0)
+		ret |= pm800_disable_watch_dog();
+	/* Voltage init */
+	ret |= pm800_voltage_init();
+	/* Restore i2c bus num */
+	i2c_set_bus_num(cur_bus);
+	return ret;
+}
diff --git a/board/Marvell/rd6281a/rd6281a.c b/board/Marvell/rd6281a/rd6281a.c
index ecdea82d90..9c768bf595 100644
--- a/board/Marvell/rd6281a/rd6281a.c
+++ b/board/Marvell/rd6281a/rd6281a.c
@@ -25,6 +25,7 @@
 #include <common.h>
 #include <miiphy.h>
 #include <netdev.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "rd6281a.h"
diff --git a/board/Marvell/sheevaplug/sheevaplug.c b/board/Marvell/sheevaplug/sheevaplug.c
index d7dc80c1ba..71e6793098 100644
--- a/board/Marvell/sheevaplug/sheevaplug.c
+++ b/board/Marvell/sheevaplug/sheevaplug.c
@@ -24,6 +24,7 @@
 
 #include <common.h>
 #include <miiphy.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 #include "sheevaplug.h"
diff --git a/board/Marvell/yellowstone/Makefile b/board/Marvell/yellowstone/Makefile
new file mode 100644
index 0000000000..84676cbf72
--- /dev/null
+++ b/board/Marvell/yellowstone/Makefile
@@ -0,0 +1,45 @@
+#
+# (C) Copyright 2008
+# Marvell Inc.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).o
+
+COBJS	:= yellowstone.o pm800.o
+
+OBJS	:= $(addprefix $(obj),$(COBJS))
+
+$(LIB):	$(obj).depend $(OBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/Marvell/yellowstone/pm800.c b/board/Marvell/yellowstone/pm800.c
new file mode 100644
index 0000000000..03eb27a2e4
--- /dev/null
+++ b/board/Marvell/yellowstone/pm800.c
@@ -0,0 +1,130 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <i2c.h>
+
+/* Base Page */
+#define PM800_BASE_PAGE	0x30
+
+#define PM800_WAKEUP1	0x0D
+#define PM800_WAKEUP2	0x0E
+
+/* Power Page */
+#define PM800_POWER_PAGE	0x31
+
+#define VBUCK_EN_REG	0x50
+#define LDO_EN_REG1	0x51
+#define LDO_EN_REG2	0x52
+#define LDO_EN_REG3	0x53
+
+#define VBUCK1_SET_REG	0x3C
+#define VBUCK2_SET_REG	0x40
+#define VBUCK3_SET_REG	0x41
+#define VBUCK4_SET_REG	0x42
+#define VBUCK5_SET_REG	0x43
+
+#define LDO1_SET_REG	0x08
+#define LDO2_SET_REG	0x0B
+#define LDO3_SET_REG	0x0C
+#define LDO4_SET_REG	0x0D
+#define LDO5_SET_REG	0x0E
+#define LDO6_SET_REG	0x0F
+#define LDO7_SET_REG	0x10
+#define LDO8_SET_REG	0x11
+#define LDO9_SET_REG	0x12
+#define LDO10_SET_REG	0x13
+#define LDO11_SET_REG	0x14
+#define LDO12_SET_REG	0x15
+#define LDO13_SET_REG	0x16
+#define LDO14_SET_REG	0x17
+#define LDO15_SET_REG	0x18
+#define LDO16_SET_REG	0x19
+#define LDO17_SET_REG	0x1A
+#define LDO18_SET_REG	0x1B
+#define LDO19_SET_REG	0x1C
+
+static inline int pm800_write_reg_power(u8 reg, u8 val)
+{
+	return i2c_write(PM800_POWER_PAGE, reg, 1, &val, 1);
+}
+
+static inline int pm800_write_reg_base(u8 reg, u8 val)
+{
+	return i2c_write(PM800_BASE_PAGE, reg, 1, &val, 1);
+}
+
+static int pm800_voltage_init(void)
+{
+	int ret = 0;
+	/* Disable VBUCK5 */
+	ret |= pm800_write_reg_power(VBUCK_EN_REG, 0x0F);
+	/* Disable LDO1 & LDO4 */
+	ret |= pm800_write_reg_power(LDO_EN_REG1, 0xF6);
+	/* Disable LDO12 & LDO14 & LDO15 */
+	ret |= pm800_write_reg_power(LDO_EN_REG2, 0x97);
+	/* BUCKs votage setting */
+	ret |= pm800_write_reg_power(VBUCK1_SET_REG, 0x28);	/* 1100mv */
+	ret |= pm800_write_reg_power(VBUCK2_SET_REG, 0x3c);	/* 1350mv */
+	ret |= pm800_write_reg_power(VBUCK3_SET_REG, 0x30);	/* 1200mv */
+	ret |= pm800_write_reg_power(VBUCK4_SET_REG, 0x54);	/* 1800mv */
+	/* LDOs voltage settting */
+	ret |= pm800_write_reg_power(LDO2_SET_REG, 0xFF);	/* 1500mv */
+	ret |= pm800_write_reg_power(LDO3_SET_REG, 0x00);	/* 1200mv */
+	ret |= pm800_write_reg_power(LDO5_SET_REG, 0xFF);	/* 3300mv */
+	ret |= pm800_write_reg_power(LDO6_SET_REG, 0x33);	/* 1800mv */
+	ret |= pm800_write_reg_power(LDO7_SET_REG, 0xAA);	/* 2800mv */
+	ret |= pm800_write_reg_power(LDO8_SET_REG, 0x00);	/* 1200mv */
+	ret |= pm800_write_reg_power(LDO9_SET_REG, 0x33);	/* 1800mv */
+	ret |= pm800_write_reg_power(LDO10_SET_REG, 0xAA);	/* 2800mv */
+	ret |= pm800_write_reg_power(LDO11_SET_REG, 0x00);	/* 1200mv */
+	ret |= pm800_write_reg_power(LDO13_SET_REG, 0xDD);	/* 3000mv */
+	ret |= pm800_write_reg_power(LDO14_SET_REG, 0xAA);	/* 2800mv */
+	ret |= pm800_write_reg_power(LDO16_SET_REG, 0xDD);	/* 3000mv */
+	ret |= pm800_write_reg_power(LDO17_SET_REG, 0xDD);	/* 3000mv */
+	ret |= pm800_write_reg_power(LDO18_SET_REG, 0x44);	/* 2800mv */
+	ret |= pm800_write_reg_power(LDO19_SET_REG, 0x11);	/* 1800mv */
+	return ret;
+}
+
+static int pm800_disable_watch_dog(void)
+{
+	int ret = 0;
+	/* Set WD_TIMER_COUNT to 0 */
+	ret |= pm800_write_reg_base(PM800_WAKEUP2, 0x0);
+	/* Reset watch dog timer */
+	ret |= pm800_write_reg_base(PM800_WAKEUP1, 0x10);
+	return ret;
+}
+
+int pmic_init(void)
+{
+	int ret = 0;
+	unsigned int cur_bus = i2c_get_bus_num();
+	/* Set i2c bus */
+	i2c_set_bus_num(0);
+	/* Disable Watch Dog */
+	ret |= pm800_disable_watch_dog();
+	/* Voltage init */
+	ret |= pm800_voltage_init();
+	/* Restore i2c bus num */
+	i2c_set_bus_num(cur_bus);
+	return ret;
+}
diff --git a/board/Marvell/yellowstone/yellowstone.c b/board/Marvell/yellowstone/yellowstone.c
new file mode 100644
index 0000000000..bba4d910e2
--- /dev/null
+++ b/board/Marvell/yellowstone/yellowstone.c
@@ -0,0 +1,275 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductors Ltd. <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <mvmfp.h>
+#include <i2c.h>
+#include <asm/arch/mfp.h>
+#include <asm/arch/cpu.h>
+#include <asm/gpio.h>
+#ifdef CONFIG_USB_ETHER
+#include <asm/arch/usb.h>
+#endif
+#ifdef CONFIG_GENERIC_MMC
+#include <sdhci.h>
+#endif
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * Basic support
+ */
+static u32 boardid;
+static u8 boardrev, boardtype;
+int board_early_init_f(void)
+{
+	u32 mfp_cfg[] = {
+		/* Enable Console on UART3 */
+		UART3_RXD,
+		UART3_TXD,
+
+		/* Enable TWSI5 */
+		TWSI5_SCL,
+		TWSI5_SDA,
+
+		/* Enable TWSI6 */
+		TWSI6_SCL,
+		TWSI6_SDA,
+
+		/* MMC1 */
+		MMC1_DATA3,
+		MMC1_DATA2,
+		MMC1_DATA1,
+		MMC1_DATA0,
+		MMC1_CLK,
+		MMC1_CMD,
+		MMC1_CD,
+		MMC1_WP,
+
+		/* MMC3 */
+		MMC3_DATA7_NDIO15,
+		MMC3_DATA6_NDIO14,
+		MMC3_DATA5_NDIO12,
+		MMC3_DATA4_NDIO10,
+		MMC3_DATA3_NDIO8,
+		MMC3_DATA2_NDIO13,
+		MMC3_DATA1_NDIO11,
+		MMC3_DATA0_NDIO9,
+		MMC3_CLK_SMNCS1,
+		MMC3_CMD_SMNCS0,
+
+		MFP_EOC		/*End of configureation*/
+	};
+	/* configure MFP's */
+	mfp_config(mfp_cfg);
+
+	return 0;
+}
+
+#define MACH_TYPE_YELLOWSTONE	3495
+#define FASTBOOT_KEY	20
+int board_init(void)
+{
+	/* OEM UniqueID in the NTIM
+	 * 32bit format: NN NN NN TV
+	 * NNNNNN: board name
+	 *	0x594553 (YES, YellowStone)
+	 *	0x414249 (ABI, Abilene)
+	 * T: type
+	 *	0x1 (Pop board)
+	 *	0x0 (Discrete board)
+	 * V: revision
+	*/
+	boardid = *(volatile unsigned int *)0xd1020010;
+	boardrev = boardid & 0xF;
+	boardtype = (boardid >> 4) & 0xF;
+	boardid = boardid >> 8;
+
+	if (boardid == 0x594553)
+		gd->bd->bi_arch_number = MACH_TYPE_YELLOWSTONE;
+
+	gd->bd->bi_boot_params = CONFIG_SYS_TEXT_BASE + 0x3c00;
+
+	gpio_direction_input(FASTBOOT_KEY);
+
+	return 0;
+}
+
+extern int pmic_init(void);
+int misc_init_r(void)
+{
+	int i, sz;
+
+	if (boardid == 0x594553)
+		printf("\nBoard: YellowStone (%s)\n",
+			boardtype ? "Pop" : "Discrete");
+
+#if defined(CONFIG_MMP_POWER)
+	set_volt(1230);	/* set 1.23v for vcc_core */
+	setop(6); 	/* set op for 800MHz */
+#endif
+
+	setenv("fbenv", "mmc0");
+
+	/* init pmic: BUCKS, LDOs, watch dog... */
+	pmic_init();
+
+	/* set bootargs */
+	setenv("bootargs", CONFIG_BOOTARGS);
+	/* reserve 192M pmem if the memory is larger than 512M
+	 * reserve 96M otherwise */
+	for (i = 0, sz = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+		sz += gd->bd->bi_dram[i].size;
+	if (sz > 0x20000000)
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xc000000", 0);
+	else
+		run_command("setenv bootargs ${bootargs} reserve_pmem=0xA000000", 0);
+
+	/* If Volumn up key is pressed, launch fastboot */
+	if (!gpio_get_value(FASTBOOT_KEY))
+		run_command("fb", 0);
+
+	return 0;
+}
+
+#ifdef CONFIG_GENERIC_MMC
+int board_mmc_init(bd_t *bd)
+{
+	ulong mmc_base_address[CONFIG_SYS_MMC_NUM] = CONFIG_SYS_MMC_BASE;
+	u8 i;
+
+	for (i = 0; i < CONFIG_SYS_MMC_NUM; i++) {
+		if (mv_sdh_init(mmc_base_address[i], 0, 0,
+				SDHCI_QUIRK_32BIT_DMA_ADDR))
+			return 1;
+		writel(DIS_PAD_SD_CLK_GATE | CLK_GATE_ON | CLK_GATE_CTL \
+		       | WTC(WTC_DEF) | RTC(RTC_DEF),
+		       mmc_base_address[i] + SD_FIFO_PARAM);
+
+		writew(SDCLK_DELAY(0x1f) | SDCLK_SEL | WR_ENDIAN | RD_ENDIAN \
+		       | DMA_SIZE(DMA_FIFO_128) | BURST_SIZE(BURST_64),
+		       mmc_base_address[i] + SD_CLOCK_AND_BURST_SIZE_SETUP);
+	}
+	return 0;
+}
+#endif
+
+void reset_cpu(ulong ignored)
+{
+	unsigned int cur_bus = i2c_get_bus_num();
+	u8 addr = 0x30, reg, data;
+
+	i2c_set_bus_num(0);
+	/* 1.Enable FAULT_WU and FAULT_WU_EN */
+	reg = 0xE7;
+	i2c_read(addr, reg, 1, &data, 1);
+	data |= ((1 << 3) | (1 << 2));
+	i2c_write(addr, reg, 1, &data, 1);
+	/* 2.Issue SW power down */
+	reg = 0x0D;
+	data = 0x20;
+	i2c_write(addr, reg, 1, &data,  1);
+	i2c_set_bus_num(cur_bus);
+}
+
+/*
+ * USB Ethernet
+ */
+#ifdef CONFIG_USB_ETHER
+int usb_lowlevel_init(void)
+{
+	struct usb_file *file = (struct usb_file *)CONFIG_USB_PHY_BASE;
+	int count;
+
+	if (cpu_is_ax()) {
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK | REFDIV_MASK),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | VDD12(1) | REFDIV(0xd)
+		       | FB_DIV(0xf0)), &file->pll_reg0);
+	} else if (cpu_is_bx()){
+		writel(readl(&file->pll_reg0) & ~(FB_DIV_MASK_B0 | REFDIV_MASK_B0),
+		       &file->pll_reg0);
+		writel(readl(&file->pll_reg0) | (VDD18(1) | REFDIV_B0(0xd)
+		       | FB_DIV_B0(0xf0)), &file->pll_reg0);
+	} else {
+		printf("%s: Unknown CPU type.\n", __func__);
+		return -1;
+	}
+	writel(readl(&file->pll_reg1) & ~(UTMI_PLL_PU | PLL_ICP_MASK
+	       | PLL_KVCO_MASK | PLL_CALI12_MASK), &file->pll_reg1);
+	writel(readl(&file->pll_reg1) | (UTMI_PLL_PU | PLL_ICP(2)
+	       | PLL_KVCO(3) | PLL_CALI12(3)), &file->pll_reg1);
+
+
+	writel(readl(&file->tx_reg0) & ~IMPCAL_VTH_MASK, &file->tx_reg0);
+	writel(readl(&file->tx_reg0) | IMPCAL_VTH(2), &file->tx_reg0);
+
+	writel(readl(&file->tx_reg1) & ~(CK60_PHSEL_MASK | AMP_MASK
+	       | TX_VDD12_MASK), &file->tx_reg1);
+	writel(readl(&file->tx_reg1) | (CK60_PHSEL(4) | AMP(4)
+	       | TX_VDD12(3)), &file->tx_reg1);
+
+	writel(readl(&file->tx_reg2) & ~DRV_SLEWRATE(3), &file->tx_reg2);
+	writel(readl(&file->tx_reg2) | DRV_SLEWRATE(3), &file->tx_reg2);
+
+	writel(readl(&file->rx_reg0) & ~(SQ_LENGTH_MASK | SQ_THRESH_MASK),
+	       &file->rx_reg0);
+	writel(readl(&file->rx_reg0) | (SQ_LENGTH(0x2) | SQ_THRESH(0xa)),
+	       &file->rx_reg0);
+
+	writel(readl(&file->ana_reg1) | ANA_PU, &file->ana_reg1);
+
+	writel(readl(&file->otg_reg0) | PU_OTG, &file->otg_reg0);
+
+	udelay(200);
+	writel(readl(&file->pll_reg1) | VCOCAL_START, &file->pll_reg1);
+
+	udelay(200);
+	writel(readl(&file->tx_reg0) | RCAL_START, &file->tx_reg0);
+	udelay(40);
+	writel(readl(&file->tx_reg0) & ~RCAL_START, &file->tx_reg0);
+	udelay(400);
+
+	/* make sure phy is ready */
+	count = 100;
+	while(((readl(&file->pll_reg1) & PLL_READY)==0) && count--)
+		udelay(1000);
+	if (count <= 0) {
+		printf("%s %d: calibrate timeout, UTMI_PLL %x\n",
+				__func__, __LINE__, readl(&file->pll_reg1));
+		return -1;
+	}
+
+	return 0;
+}
+#endif
+
+#ifdef CONFIG_CMD_NET
+int board_eth_init(bd_t *bis)
+{
+	int res = -1;
+
+#if defined(CONFIG_MV_UDC)
+	if (usb_eth_initialize(bis) >= 0)
+		res = 0;
+#endif
+	return res;
+}
+#endif
+
diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c
index a8f2b2317a..35dca5f97c 100644
--- a/board/keymile/km_arm/km_arm.c
+++ b/board/keymile/km_arm/km_arm.c
@@ -34,6 +34,7 @@
 #include <netdev.h>
 #include <miiphy.h>
 #include <asm/io.h>
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/mpp.h>
 
diff --git a/boards.cfg b/boards.cfg
index d32ff7e15f..09d93581b0 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -155,6 +155,16 @@ dkb			     arm         arm926ejs   -                   Marvell        pantheon
 integratorap_cm946es         arm         arm946es    integrator          armltd         -               integratorap
 integratorcp_cm946es         arm         arm946es    integrator          armltd         -               integratorcp
 ca9x4_ct_vxp                 arm         armv7       vexpress            armltd
+abilene                      arm         armv7       abilene             Marvell        armada620	abilene
+abilene_cm                   arm         armv7       abilene             Marvell        armada620	abilene:TZ_HYPERVISOR
+mmp2_brownstone              arm         armv7       brownstone          Marvell        armada610
+mmp2_g50                     arm         armv7       g50                 Marvell        armada610
+mmp_yellowstone              arm         armv7       yellowstone         Marvell        armada620	yellowstone
+mmp_yellowstone_cm           arm         armv7       yellowstone         Marvell        armada620	yellowstone:TZ_HYPERVISOR
+mmp_orchid                   arm         armv7       orchid              Marvell        armada620       orchid
+mmp_orchid_cm                arm         armv7       orchid              Marvell        armada620       orchid:TZ_HYPERVISOR
+mmp_mk2                      arm         armv7       mk2                 Marvell        armada620       mk2
+mmp_mk2_cm                   arm         armv7       mk2                 Marvell        armada620       mk2:TZ_HYPERVISOR
 efikamx                      arm         armv7       efikamx             -              mx5		efikamx:IMX_CONFIG=board/efikamx/imximage.cfg
 mx51evk                      arm         armv7       mx51evk             freescale      mx5		mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg
 mx53ard                      arm         armv7       mx53ard             freescale      mx5		mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg
diff --git a/common/Makefile b/common/Makefile
index 2edbd71474..76f0923397 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -25,6 +25,14 @@ include $(TOPDIR)/config.mk
 
 LIB	= $(obj)libcommon.o
 
+ifneq ($(TARGET_BUILD_VARIANT), user)
+CFLAGS  += -DNONUSERBUILD
+else
+ifeq ($(TARGET_BUILD_DEVMODE), enable)
+CFLAGS  += -DNONUSERBUILD
+endif
+endif
+
 # core
 ifndef CONFIG_SPL_BUILD
 COBJS-y += main.o
@@ -88,6 +96,7 @@ COBJS-$(CONFIG_CMD_EEPROM) += cmd_eeprom.o
 COBJS-$(CONFIG_CMD_ELF) += cmd_elf.o
 COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_exit.o
 COBJS-$(CONFIG_CMD_EXT2) += cmd_ext2.o
+COBJS-$(CONFIG_CMD_FASTBOOT) += cmd_fastboot.o
 COBJS-$(CONFIG_CMD_FAT) += cmd_fat.o
 COBJS-$(CONFIG_CMD_FDC)$(CONFIG_CMD_FDOS) += cmd_fdc.o
 COBJS-$(CONFIG_OF_LIBFDT) += cmd_fdt.o fdt_support.o
@@ -151,6 +160,7 @@ COBJS-$(CONFIG_SYS_HUSH_PARSER) += cmd_test.o
 COBJS-$(CONFIG_CMD_TSI148) += cmd_tsi148.o
 COBJS-$(CONFIG_CMD_UBI) += cmd_ubi.o
 COBJS-$(CONFIG_CMD_UBIFS) += cmd_ubifs.o
+COBJS-$(CONFIG_CMD_UNSPARSE) += cmd_unsparse.o
 COBJS-$(CONFIG_CMD_UNIVERSE) += cmd_universe.o
 COBJS-$(CONFIG_CMD_UNZIP) += cmd_unzip.o
 ifdef CONFIG_CMD_USB
@@ -160,6 +170,7 @@ COBJS-$(CONFIG_USB_STORAGE) += usb_storage.o
 endif
 COBJS-$(CONFIG_CMD_XIMG) += cmd_ximg.o
 COBJS-$(CONFIG_YAFFS2) += cmd_yaffs2.o
+COBJS-$(CONFIG_HDMI) += cmd_hdmi.o
 
 # others
 COBJS-$(CONFIG_DDR_SPD) += ddr_spd.o
@@ -173,6 +184,8 @@ COBJS-$(CONFIG_LYNXKDI) += lynxkdi.o
 COBJS-$(CONFIG_MODEM_SUPPORT) += modem.o
 COBJS-$(CONFIG_UPDATE_TFTP) += update.o
 COBJS-$(CONFIG_USB_KEYBOARD) += usb_kbd.o
+COBJS-$(CONFIG_MV_WTM) += mv_wtm.o
+COBJS-$(CONFIG_MV_RECOVERY) += mv_recovery.o
 endif
 
 COBJS-y += console.o
diff --git a/common/cmd_fastboot.c b/common/cmd_fastboot.c
new file mode 100644
index 0000000000..a53522b483
--- /dev/null
+++ b/common/cmd_fastboot.c
@@ -0,0 +1,834 @@
+/*
+ * Copyright (C) 2008 The Android Open Source Project
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
+ * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+/*
+ * Copyright (c) 2010 Marvell Inc.
+ * Modified by Lei Wen <leiwen@marvell.com>
+ */
+#include <common.h>
+#include <fastboot.h>
+#include <sparse_format.h>
+#include <jffs2/load_kernel.h>
+#include <linux/mtd/mtd.h>
+#include <mmc.h>
+#include <malloc.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#define SECTOR_SIZE 512
+enum fb_dev {
+	FB_INVALID = 0,
+	FB_NOR = MTD_DEV_TYPE_NOR,
+	FB_NAND = MTD_DEV_TYPE_NAND,
+	FB_ONENAND = MTD_DEV_TYPE_ONENAND,
+	FB_MMC,
+	FB_MAX,
+};
+
+#ifndef CONFIG_FB_RESV
+#define CONFIG_FB_RESV	64
+#endif
+
+#define MAX_NAME_NUM	36
+#define UDC_OUT_PACKET_SIZE 0x200
+block_dev_desc_t *mmc_dev;
+static char commands[CONFIG_SYS_CBSIZE];
+/* For each part has four attributes:
+ * device type, device num, start address, size
+ */
+struct fb_part {
+	char name[MAX_NAME_NUM];
+#define PART_ATTR_YAFFS	1
+#define PART_NUM_MASK	0xE0000000
+#define PART_NUM(x)	(((x) & PART_NUM_MASK) >> 29)
+	unsigned int attr;
+	unsigned long long start;
+	unsigned long long size;
+};
+
+struct fb_parts {
+	enum fb_dev dev;
+	int dev_num;
+	int part_num;
+	int align_len;
+	struct fb_part *part;
+};
+
+static struct fb_parts *parts;
+#ifdef CONFIG_MTD_DEVICE
+#ifdef CONFIG_SYS_FB_YAFFS
+static char *part_yaffs[] = CONFIG_SYS_FB_YAFFS;
+#else
+static char *part_yaffs[] = {NULL};
+#endif
+#endif
+
+static char *rcv_buf;
+static unsigned fb_mem, ramdisk_addr, ramdisk_size, kernel_addr, kernel_size;
+static int keep_running, is_yaffs, part_num, onfly, bootsp, first_rcv, need_unsparse;
+
+#define BOOT_MAGIC "ANDROID!"
+#define BOOT_MAGIC_SIZE 8
+#define BOOT_NAME_SIZE 16
+#define BOOT_ARGS_SIZE 512
+
+struct boot_img_hdr {
+	unsigned char magic[BOOT_MAGIC_SIZE];
+
+	unsigned kernel_size;  /* size in bytes */
+	unsigned kernel_addr;  /* physical load addr */
+
+	unsigned ramdisk_size; /* size in bytes */
+	unsigned ramdisk_addr; /* physical load addr */
+
+	unsigned second_size;  /* size in bytes */
+	unsigned second_addr;  /* physical load addr */
+
+	unsigned tags_addr;    /* physical addr for kernel tags */
+	unsigned page_size;    /* flash page size we assume */
+	unsigned unused[2];    /* future expansion: should be 0 */
+
+	unsigned char name[BOOT_NAME_SIZE]; /* asciiz product name */
+
+	unsigned char cmdline[BOOT_ARGS_SIZE];
+
+	unsigned id[8]; /* timestamp / checksum / sha1 / etc */
+};
+
+static unsigned rx_addr;
+static unsigned rx_length;
+static unsigned long long flash_start;
+static unsigned long long flash_len;
+
+static int init_boot_linux(void)
+{
+	struct boot_img_hdr *hdr = (void *) fb_mem;
+	unsigned page_mask = 2047;
+	unsigned kernel_actual;
+	unsigned ramdisk_actual;
+	unsigned second_actual;
+
+	if ((kernel_size < 2048)
+			|| memcmp(hdr->magic, BOOT_MAGIC, BOOT_MAGIC_SIZE)) {
+		printf("bootimg: bad header\n");
+		return -1;
+	}
+
+	if (hdr->page_size != 2048) {
+		printf("bootimg: invalid page size\n");
+		return -1;
+	}
+
+	kernel_actual = (hdr->kernel_size + page_mask) & (~page_mask);
+	ramdisk_actual = (hdr->ramdisk_size + page_mask) & (~page_mask);
+	second_actual = (hdr->second_size + page_mask) & (~page_mask);
+
+	if (kernel_size !=
+		(kernel_actual + ramdisk_actual + second_actual + 2048)) {
+		printf("bootimg: invalid image size");
+		return -1;
+	}
+
+	/* XXX process commandline here */
+	if (hdr->cmdline[0]) {
+		hdr->cmdline[BOOT_ARGS_SIZE - 1] = 0;
+		printf("cmdline is: %s\n", hdr->cmdline);
+		setenv("bootargs", (char *)hdr->cmdline);
+	}
+
+	/* XXX how to validate addresses? */
+	kernel_addr = (unsigned)hdr + 2048;
+	kernel_size = hdr->kernel_size;
+	ramdisk_size = hdr->ramdisk_size;
+	if (ramdisk_size > 0)
+		ramdisk_addr = (kernel_addr + 2048 + kernel_size) & (~page_mask);
+	else
+		ramdisk_addr = 0;
+
+	printf("bootimg: kernel addr=%x size=%x\n",
+			kernel_addr, kernel_size);
+	printf("bootimg: ramdisk addr=%x size=%x\n",
+			ramdisk_addr, ramdisk_size);
+
+	return 0;
+}
+
+static int composite_command(int is_write)
+{
+	char tmp[CONFIG_SYS_CBSIZE];
+	ulong start, len;
+
+	if (need_unsparse) {
+		need_unsparse = 0;
+		sprintf(commands, "mmc dev %d 0; unsparse mmc %d 0x%x 0x%llx 0x%llx",
+			parts->dev_num, parts->dev_num,
+			fb_mem, flash_start, parts->part[part_num].size);
+		goto DIRECT_BURN;
+	}
+
+	start = (parts->dev == FB_MMC)
+		? flash_start / SECTOR_SIZE : flash_start;
+	len = (parts->dev == FB_MMC) ? flash_len / SECTOR_SIZE : flash_len;
+	if (is_write) {
+		if (is_yaffs)
+			sprintf(tmp, "write.yaffs 0x%x 0x%lx 0x%lx",
+					fb_mem, start, len);
+		else
+			sprintf(tmp, "write 0x%x 0x%lx 0x%lx",
+					fb_mem, start, len);
+	} else
+		sprintf(tmp, "erase 0x%lx 0x%lx", start, len);
+
+	switch (parts->dev) {
+	case FB_NOR:
+		sprintf(commands, "sf %s", tmp); break;
+	case FB_NAND:
+		sprintf(commands, "nand device %d; nand %s",
+				parts->dev_num, tmp); break;
+	case FB_ONENAND:
+		sprintf(commands, "onenand %s", tmp); break;
+	case FB_MMC:
+		sprintf(commands, "mmc dev %d %d; mmc %s; mmc dev %d 0",
+			parts->dev_num, PART_NUM(parts->part[part_num].attr),
+			tmp, parts->dev_num);
+		break;
+	default:
+		printf("Err dev!!\n");
+		return 0;
+	}
+
+DIRECT_BURN:
+	printf("command::%s\n", commands);
+	run_command(commands, 0);
+	return 0;
+}
+
+static void burn_image(int force_burn)
+{
+	int len = rx_addr - fb_mem;
+	int checklen = (is_yaffs) ? ((CONFIG_SYS_FASTBOOT_ONFLY_SZ/32)*33)
+			: CONFIG_SYS_FASTBOOT_ONFLY_SZ;
+	if (len == checklen || force_burn) {
+		if (!is_yaffs) {
+			flash_len = len & ~(parts->align_len - 1);
+			if (flash_len != len) {
+				flash_len += parts->align_len;
+				memset((char *)rx_addr, 0xff, flash_len - len);
+			}
+		} else
+			flash_len = len;
+		composite_command(1);
+		flash_start += CONFIG_SYS_FASTBOOT_ONFLY_SZ;
+		fb_set_buf((void *)fb_mem);
+		rx_addr = fb_mem;
+	}
+}
+
+static int check_part(char *name)
+{
+	int i;
+	for (i = 0; i < parts->part_num; i++) {
+		if (strncmp(name, parts->part[i].name,
+					strlen(name)) == 0)
+			break;
+	}
+	if (i == parts->part_num) {
+		printf("There is no such part!\n");
+		fb_tx_status("FAILno such part");
+		return -1;
+	}
+
+	return i;
+}
+
+static int find_devnum(const char *p)
+{
+	int devnum;
+	if (*p == '\0') {
+		printf("no partition number specified\n");
+		return -1;
+	}
+	devnum = simple_strtoul(p, (char **)&p, 0);
+	if (*p != '\0') {
+		printf("unexpected trailing character '%c'\n", *p);
+		return -1;
+	}
+	return devnum;
+}
+
+static int init_partitions(void)
+{
+	struct mmc *mmc;
+	int i, pnum = 0;
+	disk_partition_t info;
+	const char *p;
+
+	mmc_dev = NULL;
+	p = getenv("fbenv");
+	if (0 == strncmp(p, "mmc", 3)) {
+#ifdef CONFIG_MMC
+		parts = malloc(sizeof(struct fb_parts));
+		if (!parts) {
+			printf("Out of memory %s:%d\n", __func__, __LINE__);
+			return 1;
+		}
+		i = find_devnum(p + 3);
+		if (i == -1)
+			return 1;
+		mmc = find_mmc_device(i);
+		if (!mmc)
+			return 1;
+		mmc_init(mmc);
+		parts->part_num = 0;
+		parts->part = 0;
+		parts->align_len = SECTOR_SIZE;
+		parts->dev = FB_MMC;
+		parts->dev_num = i;
+		mmc_dev = mmc_get_dev(i);
+		pnum = get_partition_num(mmc_dev);
+		if (pnum) {
+			parts->part = malloc(sizeof(struct fb_part)*pnum);
+			if (!parts->part) {
+				printf("Out of memory %s:%d\n",
+						__func__, __LINE__);
+				return 1;
+			}
+		} else
+			parts->part = NULL;
+		parts->part_num = pnum;
+		if (mmc_dev != NULL && mmc_dev->type != DEV_TYPE_UNKNOWN) {
+			for (i = 1; i <= pnum; i++) {
+				int len;
+				if (get_partition_info(mmc_dev, i, &info))
+					break;
+				len = strlen((char *)info.name);
+				len = (len < MAX_NAME_NUM)
+					? len : MAX_NAME_NUM - 1;
+				memcpy(parts->part[i - 1].name, info.name, len);
+				parts->part[i - 1].name[len] = 0;
+				parts->part[i - 1].start =
+				  (unsigned long long)info.start * info.blksz;
+				parts->part[i - 1].size =
+				  (unsigned long long)info.size * info.blksz;
+				parts->part[i - 1].attr = 0;
+			}
+		}
+#else
+		printf("CONFIG_MMC not be defined!!\n");
+		return 1;
+#endif
+	} else {
+#ifdef CONFIG_MTD_DEVICE
+		enum fb_dev type;
+		struct mtd_device *dev;
+		struct part_info *part;
+		int j, align;
+		if (mtdparts_init()) {
+			printf("mtd part init fail!\n");
+			return 1;
+		}
+		if (0 == strncmp(p, "nand", 4)) {
+			p += 4;
+			type = FB_NAND;
+			align = CONFIG_SYS_FASTBOOT_ONFLY_SZ;
+		} else if (0 == strncmp(p, "onenand", 4)) {
+			p += 7;
+			type = FB_ONENAND;
+			align = CONFIG_SYS_FASTBOOT_ONFLY_SZ;
+		} else if (0 == strncmp(p, "nor", 3)) {
+			p += 3;
+			type = FB_NOR;
+			align = 1;
+		} else {
+			printf("fbenv must de defined!!");
+			return 1;
+		}
+
+		i = find_devnum(p);
+		if (i == -1)
+			return 1;
+
+		dev = device_find(type, i);
+		if (dev == NULL) {
+			printf("There is no device as %s\n", getenv("fbenv"));
+			return 1;
+		}
+		if (!dev->num_parts)
+			return 1;
+		parts = malloc(sizeof(struct fb_parts));
+		if (!parts) {
+			printf("Out of memory %s:%d\n", __func__, __LINE__);
+			return 1;
+		}
+		parts->part = malloc(sizeof(struct fb_part)*dev->num_parts);
+		if (!parts->part) {
+			printf("Out of memory %s:%d\n", __func__, __LINE__);
+			return 1;
+		}
+		parts->dev = type;
+		parts->dev_num = i;
+		parts->part_num = dev->num_parts;
+		parts->align_len = align;
+		pnum = dev->num_parts;
+		for (i = 0; i < dev->num_parts; i++) {
+			part = mtd_part_info(dev, i);
+			if (part) {
+				int len;
+				len = strlen((char *)part->name);
+				len = (len < MAX_NAME_NUM)
+					? len : MAX_NAME_NUM - 1;
+				memcpy(parts->part[i].name, part->name, len);
+				parts->part[i].name[len] = 0;
+				parts->part[i].start = part->offset;
+				parts->part[i].size = part->size;
+				parts->part[i].attr = 0;
+				for (j = 0; j < ARRAY_SIZE(part_yaffs); j++)
+					if (!memcmp(part_yaffs[j], part->name,
+						    strlen(part->name))) {
+						parts->part[i].attr =
+							PART_ATTR_YAFFS;
+						break;
+					}
+			} else {
+				printf("fail to find the part:%s\n",
+						part->name);
+				return 1;
+			}
+		}
+#else
+		printf("CONFIG_MTD_DEVICE not be defined!!\n");
+		return 1;
+#endif
+	}
+
+	switch (parts->dev) {
+	case FB_NOR:
+		printf("nor\n"); break;
+	case FB_NAND:
+		printf("nand\n"); break;
+	case FB_ONENAND:
+		printf("onenand\n"); break;
+	case FB_MMC:
+		printf("mmc\n"); break;
+	default:
+		printf("error!!!\n"); break;
+	}
+	for (i = 0; i < pnum; i++)
+		printf("part %3d::attr %x::%12s\t"
+			"start 0x%08llx, size 0x%08llx\n",
+			i, parts->part[i].attr, parts->part[i].name,
+			parts->part[i].start, parts->part[i].size);
+	return 0;
+}
+
+static int modify_part(char *name, unsigned long long x[3])
+{
+	int len = strlen(name);
+	parts->part = realloc(parts->part,
+			sizeof(struct fb_part)*(parts->part_num + 1));
+	if (!parts->part)  {
+		printf("Out of memory %s:%d\n", __func__, __LINE__);
+		return 1;
+	}
+	len = (len < MAX_NAME_NUM) ? len : MAX_NAME_NUM - 1;
+	memcpy(parts->part[parts->part_num].name, name, len);
+	parts->part[parts->part_num].name[len] = 0;
+	parts->part[parts->part_num].attr = (unsigned int)x[0];
+	parts->part[parts->part_num].start = x[1];
+	parts->part[parts->part_num].size = x[2];
+	parts->part_num++;
+
+	return 0;
+}
+
+#define MAX_RESP_SZ	64
+void rcv_cmd(void)
+{
+	char status[MAX_RESP_SZ];
+	int len;
+	static char *cmdbuf;
+
+	len = fb_get_rcv_len();
+	cmdbuf = (char *)fb_get_buf();
+
+	if (rx_length) {
+		rx_length -= len;
+		rx_addr += len;
+		fb_set_buf(cmdbuf + len);
+		/* Here we do some check for the downloaded image header */
+#ifdef CONFIG_CMD_UNSPARSE
+		if (first_rcv) {
+			sparse_header_t *header;
+
+			first_rcv = 0;
+			header = (sparse_header_t *)fb_mem;
+			if (header->magic == SPARSE_HEADER_MAGIC) {
+				if (parts->dev == FB_MMC) {
+					if (onfly)
+						onfly = 0;
+					need_unsparse = 1;
+				} else
+					printf("Only mmc support sparsed"
+						" Image now!\n");
+			}
+		}
+#endif
+		if (!rx_length) {
+			if (onfly)
+				burn_image(1);
+			fb_tx_status("OKAY");
+			fb_set_buf (rcv_buf);
+			onfly = 0;
+		} else {
+			if (onfly)
+				burn_image(0);
+		}
+
+		return;
+	}
+	if (len >= UDC_OUT_PACKET_SIZE)
+		len = UDC_OUT_PACKET_SIZE - 1;
+	cmdbuf[len] = 0;
+
+	printf("\n> %s\n", cmdbuf);
+
+	if (memcmp(cmdbuf, "download:", 9) == 0) {
+		rx_addr = fb_mem;
+		first_rcv = 1;
+		fb_set_buf((void *)rx_addr);
+		rx_length = simple_strtoul(cmdbuf + 9, NULL, 16);
+		if ((onfly && (rx_length > flash_len)) ||
+		       (!onfly && (rx_length > (CONFIG_FB_RESV*1024*1024)))) {
+			fb_tx_status("FAILdata too large");
+			rx_length = 0;
+			return;
+		}
+		kernel_size = rx_length;
+		printf("recv data addr=%x size=%x\n", rx_addr, rx_length);
+		strcpy(status, "DATA");
+		sprintf(status + 4, "%08x", rx_length);
+		fb_tx_status(status);
+		return;
+	}
+
+	if (memcmp(cmdbuf, "boot", 4) == 0) {
+		if (init_boot_linux())
+			fb_tx_status("FAILinvalid boot image");
+		else {
+			printf("booting linux...\n");
+			fb_tx_status("OKAY");
+#if 0
+			if (!bootsp) {
+				if (ramdisk_size > 0)
+					sprintf(status, "bootm 0x%x 0x%x 0x%x",
+						kernel_addr, ramdisk_addr,
+						ramdisk_size);
+				else
+					sprintf(status, "bootm 0x%x",
+							kernel_addr);
+			} else
+				sprintf(status, "go 0x%x", kernel_addr);
+#else
+			#define MK2_RAMDISK_ADDR 0x02100000
+			#define MK2_RAMDISK_SIZE 0x200
+			//sprintf(status, "mmc rescan; mmc dev 0 0; mmc read 0x02100000 0x8c00 0x200;setenv  bootm 0x%x 0x01100000 0x%x", kernel_addr, 0x200);
+			sprintf(status, "setenv ramdisk_addr 0x%x; setenv ramdisk_size 0x%x; \
+					 mmc rescan; mmc dev 0 0; mmc read 0x%x 0x8c00 0x%x; \
+					 bootm 0x%x 0x%X 0x%x",
+					 MK2_RAMDISK_ADDR, MK2_RAMDISK_SIZE,
+					 MK2_RAMDISK_ADDR, MK2_RAMDISK_SIZE,
+					 kernel_addr, MK2_RAMDISK_ADDR, MK2_RAMDISK_SIZE);
+#endif
+			printf("cmd:%s\n", status);
+			run_command(status, 0);
+			fb_tx_status("FAILNot zImage, use bootsp oem cmd"
+				       " to boot special app");
+		}
+		return;
+	}
+	onfly = 0;
+	bootsp = 0;
+	if (memcmp(cmdbuf, "flash", 5) == 0) {
+		int ret = 0;
+		if (rx_addr > fb_mem) {
+			if (strncmp(cmdbuf + 6, "trust", strlen("trust")) == 0){
+
+				struct mmc *mmc;
+				int mmc_dev_id = 0;
+				
+				mmc = find_mmc_device(mmc_dev_id);
+				if (!mmc)
+					return 1;
+
+				mmc_init(mmc);
+				mmc_switch_part(mmc_dev_id, 1);
+				mmc->block_dev.block_write(mmc_dev_id, 0x0, 2048, (volatile unsigned *)fb_mem);
+
+				mmc_switch_part(mmc_dev_id, 2);
+				mmc->block_dev.block_write(mmc_dev_id, 0x0, 2048, (volatile unsigned *)(fb_mem + 0x00100000));
+
+				mmc_switch_part(mmc_dev_id, 0);
+				mmc->block_dev.block_write(mmc_dev_id, 0x0, (rx_addr - fb_mem - 0x00100000 - 0x00100000)/512, (volatile unsigned *)(fb_mem + 0x00200000));
+
+				fb_tx_status("OKAY");
+				return;	
+			}
+			else if (strncmp(cmdbuf + 6, "secondary_GPT", strlen("secondary_GPT")) == 0) {
+				struct mmc *mmc;
+				int mmc_dev_id = 0;
+				
+				mmc = find_mmc_device(mmc_dev_id);
+				if (!mmc)
+					return 1;
+
+				mmc_init(mmc);
+				mmc_switch_part(mmc_dev_id, 0);
+				mmc->block_dev.block_write(mmc_dev_id, 0x1DA9FDF, 33, (volatile unsigned *)fb_mem);
+
+				fb_tx_status("OKAY");
+				return;	
+			}
+			else{
+				part_num = check_part(cmdbuf + 6);
+				if (part_num < 0)
+					return;
+				is_yaffs = parts->part[part_num].attr & PART_ATTR_YAFFS;
+				flash_start = parts->part[part_num].start;
+				flash_len = parts->part[part_num].size;
+				if ((rx_addr - fb_mem) > flash_len) {
+					fb_tx_status("FAILdata too large");
+					return;
+				}
+				burn_image(1);
+			}
+			is_yaffs = 0;
+			if (!ret)
+				fb_tx_status("OKAY");
+		}
+		return;
+	}
+
+	if (memcmp(cmdbuf, "senddata", 8) == 0) {
+		int i, ret;
+		char *p;
+
+		ret = sprintf(status, "OKAY");
+		p = status + ret;
+		for(i=0; i<CONFIG_NR_DRAM_BANKS; i++) {
+			if (!gd->bd->bi_dram[i].size)
+				continue;
+
+			ret = sprintf(p, "%lx:%lx:",
+			   gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size);
+			p += ret;
+		}
+
+		fb_tx_status(status);
+		return;
+	}
+
+	if (memcmp(cmdbuf, "upload", 6) == 0) {
+		char *s = cmdbuf + 7, *p;
+		unsigned long upload_start, upload_sz;
+
+		p = strchr(s, ':');
+		if (!p) {
+			fb_tx_status("FAILno valid start pos");
+			return;
+		}
+		*p = 0;
+		upload_start = simple_strtoul(s, (char **)&s, 16);
+		s = p + 1;
+		p = strchr(s, ':');
+		if (!p) {
+			fb_tx_status("FAILno valid start pos");
+			return;
+		}
+		*p = 0;
+		upload_sz = simple_strtoul(s, (char **)&s, 16);
+		if (!upload_sz) {
+			fb_tx_status("FAILno valid upload sz");
+			return;
+		}
+
+		fb_tx_data((void *)upload_start, upload_sz);
+		return;
+	}
+
+	if (memcmp(cmdbuf, "erase", 5) == 0) {
+		part_num = check_part(cmdbuf + 6);
+		if (part_num < 0)
+			return;
+		flash_start = parts->part[part_num].start;
+		flash_len = parts->part[part_num].size;
+		composite_command(0);
+		fb_tx_status("OKAY");
+		return;
+	}
+
+	if (memcmp(cmdbuf, "oem", 3) == 0) {
+		if (memcmp(cmdbuf + 4, "onfly", 5) == 0) {
+			onfly = 0;
+			part_num = check_part(cmdbuf + 10);
+			if (part_num < 0)
+				return;
+			is_yaffs = parts->part[part_num].attr & PART_ATTR_YAFFS;
+			flash_start = parts->part[part_num].start;
+			flash_len = parts->part[part_num].size;
+			onfly = 1;
+			fb_tx_status("OKAY");
+			return;
+		}
+		if (memcmp(cmdbuf + 4, "bootsp", 6) == 0) {
+			bootsp = 1;
+			fb_tx_status("OKAY");
+			return;
+		}
+		if (memcmp(cmdbuf + 4, "setno", 5) == 0) {
+			char *s = cmdbuf + 4, *p;
+			p = strchr(s, ':');
+			s = p + 1;
+			if (!p || !s) {
+				fb_tx_status("FAILno valid serial no");
+				return;
+			}
+			setenv("fb_serial", s);
+			fb_tx_status("OKAY");
+			fb_init();
+			return;
+		}
+		if (memcmp(cmdbuf + 4, "part", 4) == 0) {
+			unsigned int i;
+			unsigned long long x[3];
+			char *s = cmdbuf + 8, *p, *name;
+			p = strchr(s, ':');
+			if (p) {
+				s = p + 1;
+				p = strchr(s, ':');
+				*p = 0;
+				name = s;
+				if (!name) {
+					fb_tx_status("FAILno name specified");
+					return;
+				}
+				s = p + 1;
+				for (i = 0; i < 3 && s; i++) {
+					p = strchr(s, ':');
+					if (p)
+						*p = 0;
+					x[i] = simple_strtoull(s,
+							(char **)&s, 0);
+					if (p)
+						s = p + 1;
+					else
+						break;
+				}
+				if (i == 2) {
+					if (modify_part(name, x)) {
+						fb_tx_status("FAILadd part"
+							       " error");
+						return;
+					} else {
+						fb_tx_status("OKAY");
+						return;
+					}
+				}
+			}
+
+			i = 0;
+			init_partitions();
+			sprintf(status, "INFO::there %s %d partition",
+				(parts->part_num == 1) ? "is" : "are",
+				parts->part_num);
+			fb_tx_status(status);
+			do {
+				strcpy(status, "INFO");
+				status[4] = '\0';
+				for (; i < parts->part_num; i++) {
+					strcat(status, parts->part[i].name);
+					strcat(status, ",");
+					if ((i == (parts->part_num - 1))
+					    || (strlen(status) +
+					    strlen(parts->part[i + 1].name) >=
+					    (MAX_RESP_SZ - 1))) {
+						i++;
+						fb_tx_status(status);
+						break;
+					}
+				}
+			} while (i < parts->part_num);
+			fb_tx_status("OKAY");
+			return;
+		}
+		fb_tx_status("FAILbad oem command");
+		return;
+	}
+	if (memcmp(cmdbuf, "reboot", 6) == 0) {
+		fb_tx_status("OKAY");
+		if (strncmp(cmdbuf + 6, "-bootloader", 11) == 0)
+			keep_running = 0;
+		else
+			reset_cpu(0);
+		return;
+	}
+
+	fb_tx_status("FAILinvalid command");
+}
+
+int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ALLOC_CACHE_ALIGN_BUFFER(char, cmd_pool, 512);
+	rx_length = 0;
+	part_num = -1;
+	onfly = 0;
+	bootsp = 0;
+	first_rcv = 0;
+	fb_mem = USB_LOADADDR - 2048;
+	ramdisk_size = 0;
+	kernel_addr = 0;
+	kernel_size = 0;
+	keep_running = 1;
+	is_yaffs = 0;
+	need_unsparse = 0;
+
+	init_partitions();
+
+	rcv_buf = cmd_pool;
+	fb_init();
+	fb_set_buf((void *)rcv_buf);
+	while (keep_running)
+		fb_run();
+	keep_running = 1;
+	fb_halt();
+	return 0;
+}
+
+U_BOOT_CMD(
+		fb,	1,	1,	do_fastboot,
+		"android fastboot client application",
+		""
+	  );
diff --git a/common/cmd_hdmi.c b/common/cmd_hdmi.c
new file mode 100644
index 0000000000..6492ab0627
--- /dev/null
+++ b/common/cmd_hdmi.c
@@ -0,0 +1,141 @@
+/*
+ * Control GPIO pins on the fly
+ *
+ * Copyright (c) 2008-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+
+#include <hdmi.h>
+
+#ifndef name_to_hdmi
+#define name_to_hdmi(name) simple_strtoul(name, NULL, 10)
+#endif
+
+extern unsigned *hdmi_base;
+
+static void dump_hdmi(void)
+{
+	int i;
+
+	printf("************direct register*******************\n");
+	for (i = 0x8; i <= 0x30; i += 4)
+		printf("direct offset 0x%x is 0x%x\n", i, hdmi_direct_read(hdmi_base, i));
+	printf("************indirect register*******************\n");
+	for (i = 0; i < 0x13e; i++)
+		printf("offset 0x%x is 0x%x\n", i, hdmi_read(hdmi_base, i));
+	printf("************HDCP indirect register*******************\n");
+	for (i = 0x1350; i < 0x1352; i++)
+		printf("offset 0x%x is 0x%x\n", i, hdmi_read(hdmi_base, i));
+	for (i = 0x1384; i < 0x1386; i++)
+		printf("offset 0x%x is 0x%x\n", i, hdmi_read(hdmi_base, i));
+
+}
+
+static int do_hdmi(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int hdmi;
+	ulong addr, value;
+	const char *str_cmd;
+
+	str_cmd = argv[1];
+	if ((argc == 2 && *str_cmd == 'D') ||
+	argc == 3 || argc == 4) {
+		addr = simple_strtoul(argv[2], NULL, 16);
+		value = simple_strtoul(argv[3], NULL, 16);
+	} else {
+		goto show_usage;
+	}
+
+	/* parse the behavior */
+	switch (*str_cmd) {
+		case 'm':
+			pxa168fb_hdmi_set_mode(addr, value);
+			break;
+		case 'r':
+			printf("0x%x: 0x%x\n", addr, hdmi_read(hdmi_base, addr));
+			break;
+		case 'w':
+			printf("change 0x%x from 0x%x to 0x%x\n",
+					addr, hdmi_read(hdmi_base, addr), value);
+			hdmi_write(hdmi_base, addr, value);
+			break;
+		case 'R':
+			printf("0x%x: 0x%x\n", addr, hdmi_direct_read(hdmi_base, addr));
+			break;
+		case 'W':
+			printf("change 0x%x from 0x%x to 0x%x\n",
+					addr, hdmi_direct_read(hdmi_base, addr, value), value);
+			hdmi_direct_write(hdmi_base, addr, value);
+			break;
+		case 'D':
+			dump_hdmi();
+			break;
+		default:  goto show_usage;
+	}
+	return 0;
+
+show_usage:
+		return cmd_usage(cmdtp);
+}
+
+static int do_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong addr, value;
+	const char *str_cmd;
+
+	if (argc != 3 && argc != 4)
+ show_usage:
+		return cmd_usage(cmdtp);
+	str_cmd = argv[1];
+	addr = simple_strtoul(argv[2], NULL, 16);
+	value = simple_strtoul(argv[3], NULL, 16);
+
+	/* parse the behavior */
+	switch (*str_cmd) {
+		case 'r':
+			printf("0x%x: 0x%x\n", addr, lcd_read(addr));
+			break;
+		case 'w':
+			lcd_write(addr, value);
+			break;
+		default:  goto show_usage;
+	}
+	return 0;
+}
+
+static int do_vid(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	u32 enable, xres, yres;
+	//const char *str_cmd;
+
+	if (!strcmp(argv[1], "sync")) {
+		return 0;
+	}
+
+	if (argc != 4)
+		return cmd_usage(cmdtp);
+
+	enable = simple_strtoul(argv[1], NULL, 16);
+	xres = simple_strtoul(argv[2], NULL, 16);
+	yres = simple_strtoul(argv[3], NULL, 16);
+	pxa168fb_vid(enable, xres, yres);
+
+	return 0;
+}
+
+U_BOOT_CMD(hdmi, 4, 0, do_hdmi,
+	"read/write hdmi register",
+	"r/w for indirect and R/W for direct, m for cea_mode_id\n"
+	"4: 720p60 20:1080p24 (id is in hex format)\n");
+U_BOOT_CMD(lcd, 4, 0, do_lcd,
+	"read/write lcd register",
+	"lcd r <addr> or lcd w <addr> <value>\n");
+U_BOOT_CMD(video, 4, 0, do_vid,
+	"video layer size config or 3d sync",
+	"video <enable> <xres> <yres>\n"
+	"video sync\n"
+	"Hex format input is required\n");
diff --git a/common/cmd_unsparse.c b/common/cmd_unsparse.c
new file mode 100644
index 0000000000..5c1641ecc5
--- /dev/null
+++ b/common/cmd_unsparse.c
@@ -0,0 +1,207 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+#include <common.h>
+
+#include <command.h>
+#include <environment.h>
+#include <sparse_format.h>
+#include <linux/stddef.h>
+#include <malloc.h>//Add for malloc a buf space (nand to RAM)
+#include <linux/string.h>//Add for cmp ram buf1 and nand_out_buf2
+
+#define SPARSE_HEADER_MAJOR_VER 1
+#define SECTOR_SIZE	512
+#define READ_BUF_ADDR 0x20000000
+#define RETRY_COUNT 20
+#define UPDATE_FLAG_ADDR 0x30000000
+
+int *update_flag= 0x30000000;       //flag to show if update fail 
+//*update_flag = 0;
+
+int unsparse(block_dev_desc_t *dev, uint64_t from, uint64_t to, uint64_t sz)
+{
+	sparse_header_t *header = (sparse_header_t *)from;
+	u32 i;
+    uint64_t outlen = 0;
+        
+
+	if ((header->total_blks * header->blk_sz) > sz) {
+		printf("sparse: section size %d MB limit: exceeded\n",
+				sz / (1024*1024));
+		return 1;
+	}
+
+	if (header->magic != SPARSE_HEADER_MAGIC) {
+		printf("sparse: bad magic\n");
+		return 1;
+	}
+
+	if ((header->major_version != SPARSE_HEADER_MAJOR_VER) ||
+			(header->file_hdr_sz != sizeof(sparse_header_t)) ||
+			(header->chunk_hdr_sz != sizeof(chunk_header_t))) {
+		printf("sparse: incompatible format\n");
+		return 1;
+	}
+	/* todo: ensure image will fit */
+
+	/* Skip the header now */
+	from += header->file_hdr_sz;
+
+	for (i=0; i < header->total_chunks; i++) {
+		unsigned int len = 0;
+		int r;
+		int rd;//Add by Ares (flag to show if read from nandflash successfully)
+		int read_buf = READ_BUF_ADDR;
+		int ret;
+		int retry_count = RETRY_COUNT;//Add by Ares retry_time
+		chunk_header_t *chunk = (void*) from;
+
+		printf(".");
+
+		/* move to next chunk */
+		from += sizeof(chunk_header_t);
+
+		switch (chunk->chunk_type) {
+		case CHUNK_TYPE_RAW:
+			len = chunk->chunk_sz * header->blk_sz;
+
+			if (chunk->total_sz != (len + sizeof(chunk_header_t))) {
+				printf("sparse: bad chunk size for chunk %d, type Raw\n", i);
+				return 1;
+			}
+
+			outlen += len;
+			if (outlen > sz) {
+				printf("sparse: section size %d MB limit: "
+					"exceeded\n", sz /(1024*1024));
+				return 1;
+			}
+#ifdef DEBUG
+			printf("sparse: RAW blk=%d bsz=%d: write(sector=%d,len=%d)\n",
+					chunk->chunk_sz, header->blk_sz, from, len);
+#endif
+			r = dev->block_write(dev->dev, to / SECTOR_SIZE,
+				len / SECTOR_SIZE, (const void *)from);
+				
+			//++Add by Ares@Jul14:read and check,if not the same ,do retry
+			rd = dev->block_read(dev->dev, to / SECTOR_SIZE,len / SECTOR_SIZE, read_buf);
+				
+			ret = memcmp(from,read_buf,len);
+			while(ret&&retry_count!=0)
+			{
+				printf("chunk need rewrite...\n");
+				r = dev->block_write(dev->dev, to / SECTOR_SIZE,len / SECTOR_SIZE, (const void *)from);
+				rd = dev->block_read(dev->dev, to / SECTOR_SIZE,len / SECTOR_SIZE, read_buf);
+				ret = memcmp(from,read_buf,len);
+				retry_count--;
+			}
+			if(ret!=0)
+			{
+				printf("update and retry fail.ooo\n");
+				return 1;
+			}
+			//--Add by Ares    
+				
+				
+			if (r < 0) {
+				printf("sparse: mmc write failed\n");
+				return 1;
+			}
+			
+			to += len;
+			from += len;
+			break;
+
+		case CHUNK_TYPE_DONT_CARE:
+			if (chunk->total_sz != sizeof(chunk_header_t)) {
+				printf("sparse: bogus DONT CARE chunk\n");
+				return 1;
+			}
+			len = chunk->chunk_sz * header->blk_sz;
+#ifdef DEBUG
+			printf("sparse: DONT_CARE blk=%d bsz=%d: skip(sector=%d,len=%d)\n",
+					chunk->chunk_sz, header->blk_sz, to, len);
+#endif
+
+			outlen += len;
+			if (outlen > sz) {
+				printf("sparse: section size %d MB limit: "
+						"exceeded\n", sz/(1024*1024));
+				return 1;
+			}
+			to += len;
+			break;
+
+		default:
+			printf("sparse: unknown chunk ID %04x\n", chunk->chunk_type);
+			return 1;
+		}
+	}
+
+	printf("\nsparse: out-length-0x%lld MB\n", outlen/(1024*1024));
+	return 0;
+}
+
+static int do_unsparse(cmd_tbl_t *cmdtp, int flag,
+               int argc, char * const argv[])
+{
+       uint64_t size;
+       uint64_t addr;
+       uint64_t offset;
+       block_dev_desc_t *dev_desc = NULL;
+       int dev = 0;
+       char *ep;
+	   *update_flag = 0;
+	   int ret = 0;
+
+       if (argc < 5) {
+               printf("usage: unsparse <interface> <dev> "
+                       "<ram addr> <block offset> <size>\n");
+               *update_flag = 1;
+               return 1;
+       }
+
+       dev = (int)simple_strtoul(argv[2], &ep, 16);
+       dev_desc = get_dev(argv[1], dev);
+       if (dev_desc == NULL) {
+               puts("\n** Invalid boot device **\n");
+               *update_flag = 1;
+               return 1;
+       }
+       addr = simple_strtoull(argv[3], NULL, 16);
+       offset = simple_strtoull(argv[4], NULL, 16);
+       size = simple_strtoull(argv[5], NULL, 16);
+
+       ret = unsparse(dev_desc, addr, offset, size);
+       *update_flag = ret;
+       return ret;
+}
+
+U_BOOT_CMD(
+       unsparse,       6,      0,      do_unsparse,
+       "write sparsed file into block device",
+       "<interface> <dev> <ram addr> <block offset> <size>\n"
+       "    - unsparse sparsed image from the address 'addr' in RAM\n"
+       "      to 'dev' on 'interface'"
+);
diff --git a/common/env_common.c b/common/env_common.c
index 19149b513d..777fc2e120 100644
--- a/common/env_common.c
+++ b/common/env_common.c
@@ -47,6 +47,13 @@ static uchar env_get_char_init (int index);
 #define XMK_STR(x)	#x
 #define MK_STR(x)	XMK_STR(x)
 
+#ifndef NONUSERBUILD
+#define CONFIG_BOOTCOMMAND		"mmc dev 0 0; " \
+					"mmc read 0x7fc0 0x4c00 0x3000; " \
+					"mmc read 0x2100000 0x8c00 0x200; " \
+					"bootm 0x7fc0 0x2100000\0"
+#endif
+
 const uchar default_environment[] = {
 #ifdef	CONFIG_BOOTARGS
 	"bootargs="	CONFIG_BOOTARGS			"\0"
diff --git a/common/main.c b/common/main.c
index 3324d9d6e4..756ecf0c73 100644
--- a/common/main.c
+++ b/common/main.c
@@ -1267,6 +1267,9 @@ int run_command (const char *cmd, int flag)
 	int argc, inquotes;
 	int repeatable = 1;
 	int rc = 0;
+#ifndef CONFIG_REPEAT_COMMNAD
+	repeatable = 0;
+#endif
 
 #ifdef DEBUG_PARSER
 	printf ("[RUN_COMMAND] cmd[%p]=\"", cmd);
diff --git a/common/mv_recovery.c b/common/mv_recovery.c
new file mode 100644
index 0000000000..e75b0aed3b
--- /dev/null
+++ b/common/mv_recovery.c
@@ -0,0 +1,415 @@
+/*
+ * (C) Copyright 2000-2003
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <mmc.h>
+#include <mv_recovery.h>
+
+#define MAGIC_NUM_ADDR		(0xD1020100)
+#define MAGIC_VALIDATION_ADDR	(0xD1020104)
+#define MAGIC_RESIDUE_ADDR	(0xD1020108)
+#define MISC_HEAD_BLK_ADDR	(0x14C00)
+#if defined(CONFIG_MACH_MK2)
+#define MISC_END_BLK_ADDR	(MISC_HEAD_BLK_ADDR + 0x1FFFF)	/* 64M */
+#else
+#define MISC_END_BLK_ADDR	(MISC_HEAD_BLK_ADDR + 0x9FFF)	/* 20M */
+#endif
+#define MISC_MAX_IMAGE_SIZE	(8 * 1024 * 1024)		/* 8M */
+
+//#define RECOVERY_DEBUG
+#undef RECOVERY_DEBUG
+
+#define RTC_BRN0		(0xD4010014)
+
+
+#ifndef NONUSERBUILD
+
+//Support for recovery kernel command
+#define CONFIG_GO_RKERNEL_CMD		"mmc dev 0 0; mmc read 0x7fc0 " \
+					"0xcc00 0x3000; mmc read 0x2100000 0x10c00 0x1000; bootm 0x7fc0 0x2100000"
+#endif
+
+inline void __write_recovery_reg(u8 val) {
+	__raw_writel(val, RTC_BRN0);
+}
+void write_recovery_reg(u8 val) __attribute__((weak, alias("__write_recovery_reg")));
+inline int __read_recovery_reg(void) {
+	return __raw_readl(RTC_BRN0);
+}
+int read_recovery_reg(void) __attribute__((weak, alias("__read_recovery_reg")));
+
+enum rtc_stat {
+	DEFAULT = 0,
+	KERNEL_RECOVERY,
+	UBOOT_RECOVERY
+};
+
+static enum uboot_stat_class {
+	GO_N_KERNEL = 0,
+	GO_R_UBOOT,
+	GO_R_KERNEL,
+	GO_UPDATE_RECOVERY,
+	GO_DEAD_LOOP,
+} uboot_stat;
+
+/* magic number : default value 0x54525354 */
+/* magic number indicates the validation flag and the residue flag
+ * are correct. Wrong magic number indicates that the 2 flags are not
+ * trusted by themselves. */
+
+/* validation flag */
+/* validation flag indicates whether the images are trustable.
+ * bit[0]: ramdisk	bit[1]: r_ramdisk
+ * bit[2]: kernel	bit[3]: r_kernel
+ * bit[4]: uboot	bit[5]: r_uboot
+ * bit[6]: dtim		bit[7]: r_dtim
+ * 0: image is trusted	1: image is not trusted
+ */
+
+/* residue flag */
+/* residue flag indicates whether the images are right in DDR.
+ * bit[0]: ramdisk	bit[1]: r_ramdisk
+ * bit[2]: kernel	bit[3]: r_kernel
+ * bit[4]: uboot	bit[5]: r_uboot
+ * 0: not in DDR	1: in DDR
+ */
+static struct mv_magic{
+	unsigned int magic;		/* magic number */
+	unsigned int validation;	/* validation flag */
+	unsigned int residue;		/* residue flag */
+} magic_blk;
+
+struct update_unit {
+	unsigned int	idx;
+	unsigned int	src_partition;
+	unsigned int	src_blk_addr;
+	unsigned int	des_partition;
+	unsigned int	des_blk_addr;
+	unsigned int	blk_size;
+};
+
+#if defined(CONFIG_MACH_ABILENE) || defined(CONFIG_MACH_MK2)
+static struct update_unit update_table[] = {
+	{
+		/* r_dtim */
+		.idx = (1 << 0),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x403,
+		.des_partition = 0,
+		.des_blk_addr = 0x4400,
+		.blk_size = 0x800,	/* 1M */
+	},
+	{
+		/* r_uboot */
+		.idx = (1 << 1),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0xC03,
+		.des_partition = 2,
+		.des_blk_addr = 0x400,
+		.blk_size = 0x400,	/* 512K */
+	},
+	{
+		/* r_zImage */
+		.idx = (1 << 2),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x1003,
+		.des_partition = 0,
+		.des_blk_addr = 0xCC00,
+		.blk_size = 0x4000,	/* 8M */
+	},
+	{
+		/* r_ramdisk */
+		.idx = (1 << 3),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x5003,
+		.des_partition = 0,
+		.des_blk_addr = 0x10C00,
+		.blk_size = 0x1000,	/* 8M */
+	},
+};
+#elif defined (CONFIG_MACH_BROWNSTONE)
+static struct update_unit update_table[] = {
+	{
+		/* r_uboot */
+		.idx = (1 << 0),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x283,
+		.des_partition = 1,
+		.des_blk_addr = 0x580,
+		.blk_size = 0x280,	/* 320K */
+	},
+	{
+		/* r_zImage */
+		.idx = (1 << 1),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x503,
+		.des_partition = 0,
+		.des_blk_addr = 0xCC00,
+		.blk_size = 0x4000,	/* 8M */
+	},
+	{
+		/* r_ramdisk */
+		.idx = (1 << 2),
+		.src_partition = 0,
+		.src_blk_addr = MISC_HEAD_BLK_ADDR + 0x4503,
+		.des_partition = 0,
+		.des_blk_addr = 0x10C00,
+		.blk_size = 0x1000,	/* 8M */
+	},
+};
+#else
+static struct update_unit update_table[] = {};
+#endif
+
+/* magic block should be read as soon as uboot boot up in case that
+ * this memory may be over-written by other program */
+inline void magic_read(void)
+{
+#ifdef CONFIG_TRUST_BOOT
+	magic_blk.magic = __raw_readl(MAGIC_NUM_ADDR);
+	if (magic_blk.magic != CONFIG_TRUST_BOOT_MAGIC) {
+		magic_blk.validation = 0;
+		magic_blk.residue = 0;
+	} else {
+		magic_blk.validation = __raw_readl(MAGIC_VALIDATION_ADDR);
+		magic_blk.residue = __raw_readl(MAGIC_RESIDUE_ADDR);
+	}
+#else
+	magic_blk.magic = CONFIG_TRUST_BOOT_MAGIC;
+	magic_blk.validation = 0;
+	magic_blk.residue = 0;
+#endif
+}
+
+static inline void magic_write(void)
+{
+	__raw_writel(magic_blk.magic, MAGIC_NUM_ADDR);
+	__raw_writel(magic_blk.validation, MAGIC_VALIDATION_ADDR);
+	__raw_writel(magic_blk.residue, MAGIC_RESIDUE_ADDR);
+}
+
+/* function to detect validation flag for normal flow */
+static inline int normal_flow_is_trusted(void)
+{
+	return !(magic_blk.validation & 0x55);
+}
+
+/* function to detect validation flag for recovery flow */
+static inline int recovery_flow_is_trusted(void)
+{
+	return !(magic_blk.validation & 0xaa);
+}
+
+static inline int normal_kernel_is_residue(void)
+{
+	return (magic_blk.residue & 0x04);
+}
+
+static inline int recovery_kernel_is_residue(void)
+{
+	return (magic_blk.residue & 0x08);
+}
+
+/* function to detect recovery command in misc partition */
+static int misc_detect_recovery(int blk_addr, char *cmd)
+{
+	int ret = 0;
+#ifdef CONFIG_GENERIC_MMC
+	struct mmc *mmc;
+	char buffer[512];
+
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		printf("ERR: mmc not found\n");
+		return ret;
+	}
+
+	mmc_init(mmc);
+	mmc_switch_part(0, 0);
+	mmc->block_dev.block_read(0, blk_addr, 1, buffer);
+#ifdef RECOVERY_DEBUG
+	printf("Misc command: %s\n", buffer);
+#endif
+	if (strcmp(buffer, cmd) == 0)
+		ret = 1;
+#endif
+	return ret;
+}
+
+static void clear_recovery_flag(int end_clear)
+{
+#ifdef CONFIG_GENERIC_MMC
+	struct mmc *mmc;
+	char buffer[512];
+
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		printf("ERR: mmc not found\n");
+		write_recovery_reg(DEFAULT);
+		return;
+	}
+
+	mmc_init(mmc);
+	memset(buffer, 0, sizeof(buffer));
+	strcpy(buffer, "reserved");
+	mmc_switch_part(0, 0);
+	mmc->block_dev.block_write(0, MISC_HEAD_BLK_ADDR, 1, buffer);
+	if (end_clear)
+		mmc->block_dev.block_write(0, MISC_END_BLK_ADDR, 1, buffer);
+#endif
+	write_recovery_reg(DEFAULT);
+}
+
+static void recovery_flow_update(void)
+{
+#ifdef CONFIG_GENERIC_MMC
+	struct misc_end {
+		char		cmd[32];
+		unsigned int	idx;
+		char 		reserved[476];		/* 512 bytes align */
+	} me;
+	struct mmc *mmc;
+	char buffer[MISC_MAX_IMAGE_SIZE];
+	int i;
+
+	mmc = find_mmc_device(0);
+	if (!mmc) {
+		printf("ERR: mmc not found\n");
+		return;
+	}
+
+	mmc_init(mmc);
+	mmc_switch_part(0, 0);
+	mmc->block_dev.block_read(0, MISC_END_BLK_ADDR, 1, &me);
+	for (i = 0; i < ARRAY_SIZE(update_table); i++) {
+		if (update_table[i].idx == (me.idx & (1 << i))) {
+			mmc_switch_part(0, update_table[i].src_partition);
+			mmc->block_dev.block_read(0, update_table[i].src_blk_addr,
+						update_table[i].blk_size, buffer);
+			mmc_switch_part(0, update_table[i].des_partition);
+			mmc->block_dev.block_write(0, update_table[i].des_blk_addr,
+						update_table[i].blk_size, buffer);
+		}
+	}
+	clear_recovery_flag(1);
+#endif
+	return;
+}
+
+void mv_recovery(void)
+{
+		/* check uboot mode: normal uboot or recovery uboot */
+		/* recovery_reg == UBOOT_RECOVERY means this uboot is recovery uboot */
+		/* !normal_flow_is_trusted() means this r_uboot is loaded by OBM direrctly */
+	if (read_recovery_reg() == UBOOT_RECOVERY || !normal_flow_is_trusted())
+		uboot_stat = GO_R_KERNEL;
+
+		/* the first way used by OS to go to recovery flow */
+		/* set 1 to a RTC register to transfer this command */
+		/* it is mainly used in normal kernel */
+	else if (read_recovery_reg() == KERNEL_RECOVERY)
+		uboot_stat = GO_R_UBOOT;
+
+		/* the way used by OS to update recovery flow */
+		/* go normal flow after updating done */
+	else if (misc_detect_recovery(MISC_END_BLK_ADDR, "update_recovery"))
+		uboot_stat = GO_UPDATE_RECOVERY;
+
+		/* the second way used by OS to go to recovery flow */
+		/* write special char string to misc header to transfer the command */
+		/* it is mainly used in recovery kernel */
+	else if (misc_detect_recovery(MISC_HEAD_BLK_ADDR, "boot-recovery"))
+		uboot_stat = GO_R_UBOOT;
+
+		/* the way used by user to go to recovery flow */
+		/* go to recovery flow by pressing specific keys */
+	else if (magic_key_detect_recovery())
+		uboot_stat = GO_R_UBOOT;
+
+		/* default: go to normal flow */
+	else
+		uboot_stat = GO_N_KERNEL;
+
+	/* trust flag confirmation */
+	switch (uboot_stat) {
+	case GO_R_KERNEL:
+		if (!recovery_flow_is_trusted())
+			uboot_stat = GO_DEAD_LOOP;
+		break;
+	case GO_R_UBOOT:
+		if (!recovery_flow_is_trusted()) {
+			clear_recovery_flag(0);
+			if (!normal_flow_is_trusted())
+				uboot_stat = GO_DEAD_LOOP;
+			else
+				//uboot_stat = GO_N_KERNEL;
+				uboot_stat = GO_R_KERNEL;
+		}
+		break;
+	case GO_N_KERNEL:
+	case GO_UPDATE_RECOVERY:
+#ifdef CONFIG_MACH_BROWNSTONE
+		/* both block head and block end flags indicate that it failed
+		 * in the last power cycle when doing dtim upgrade */
+		if (misc_detect_recovery(MISC_HEAD_BLK_ADDR, "boot-recovery")) {
+			uboot_stat = GO_R_KERNEL;
+			break;
+		}
+#endif
+		if (!normal_flow_is_trusted())
+			uboot_stat = GO_DEAD_LOOP;
+		break;
+	default:
+		break;
+	}
+
+	switch (uboot_stat) {
+	case GO_N_KERNEL:
+		if (normal_kernel_is_residue())
+		;//Do nothing	setenv("bootcmd", CONFIG_RESIDUE_CMD);
+		printf("Normal uboot: boot normal kernel.\n");
+		break;
+	case GO_R_UBOOT:
+		write_recovery_reg(UBOOT_RECOVERY);
+		/* pass down magic blk param */
+		magic_write();
+		setenv("bootcmd", CONFIG_GO_RUBOOT_CMD);
+		printf("Normal uboot: boot recovery uboot.\n");
+		break;
+	case GO_R_KERNEL:
+		if (recovery_kernel_is_residue())
+		{	printf("tampered\n");	
+/*	setenv("bootcmd", CONFIG_RESIDUE_CMD); */ 
+			setenv("bootcmd", CONFIG_GO_RKERNEL_CMD); 
+		}
+		else
+		{	printf("magickey\n");		
+			setenv("bootcmd", CONFIG_GO_RKERNEL_CMD); 
+		}
+		printf("Recovery uboot: boot recovery kernel.\n");
+		break;
+	case GO_UPDATE_RECOVERY:
+		printf("Update recovery flow:\n");
+		printf("=========================================\n");
+		recovery_flow_update();
+		printf("=========================================\n");
+		break;
+	case GO_DEAD_LOOP:
+		printf("DEAD LOOP: Images are not trusted!\n");
+		while(1);
+		break;
+	}
+}
+
diff --git a/common/mv_wtm.c b/common/mv_wtm.c
new file mode 100644
index 0000000000..9638e8992c
--- /dev/null
+++ b/common/mv_wtm.c
@@ -0,0 +1,222 @@
+/*
+ * (C) Copyright 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <mv_wtm.h>
+struct wtm_cmd {
+    unsigned int prim_cmd_parm0;          // 0x0
+    unsigned int prim_cmd_parm1;          // 0x4
+    unsigned int prim_cmd_parm2;          // 0x8
+    unsigned int prim_cmd_parm3;          // 0xc
+    unsigned int prim_cmd_parm4;          // 0x10
+    unsigned int prim_cmd_parm5;          // 0x14
+    unsigned int prim_cmd_parm6;          // 0x18
+    unsigned int prim_cmd_parm7;          // 0x1c
+    unsigned int prim_cmd_parm8;          // 0x20
+    unsigned int prim_cmd_parm9;          // 0x24
+    unsigned int prim_cmd_parm10;         // 0x28
+    unsigned int prim_cmd_parm11;         // 0x2c
+    unsigned int prim_cmd_parm12;         // 0x30
+    unsigned int prim_cmd_parm13;         // 0x34
+    unsigned int prim_cmd_parm14;         // 0x38
+    unsigned int prim_cmd_parm15;         // 0x3c
+    unsigned int secure_processor_cmd;    // 0x40
+};
+
+/*
++ * WTM register file for host communication
++ */
+struct wtm_mail_box {
+	unsigned int prim_cmd_parm0;          // 0x0
+	unsigned int prim_cmd_parm1;          // 0x4
+	unsigned int prim_cmd_parm2;          // 0x8
+	unsigned int prim_cmd_parm3;          // 0xc
+	unsigned int prim_cmd_parm4;          // 0x10
+	unsigned int prim_cmd_parm5;          // 0x14
+	unsigned int prim_cmd_parm6;          // 0x18
+	unsigned int prim_cmd_parm7;          // 0x1c
+	unsigned int prim_cmd_parm8;          // 0x20
+	unsigned int prim_cmd_parm9;          // 0x24
+	unsigned int prim_cmd_parm10;         // 0x28
+	unsigned int prim_cmd_parm11;         // 0x2c
+	unsigned int prim_cmd_parm12;         // 0x30
+	unsigned int prim_cmd_parm13;         // 0x34
+	unsigned int prim_cmd_parm14;         // 0x38
+	unsigned int prim_cmd_parm15;         // 0x3c
+	unsigned int secure_processor_cmd;    // 0x40
+	unsigned char reserved_0x44[60];
+	unsigned int cmd_return_status;       // 0x80
+	unsigned int cmd_status_0;            // 0x84
+	unsigned int cmd_status_1;            // 0x88
+	unsigned int cmd_status_2;            // 0x8c
+	unsigned int cmd_status_3;            // 0x90
+	unsigned int cmd_status_4;            // 0x94
+	unsigned int cmd_status_5;            // 0x98
+	unsigned int cmd_status_6;            // 0x9c
+	unsigned int cmd_status_7;            // 0xa0
+	unsigned int cmd_status_8;            // 0xa4
+	unsigned int cmd_status_9;            // 0xa8
+	unsigned int cmd_status_10;           // 0xac
+	unsigned int cmd_status_11;           // 0xb0
+	unsigned int cmd_status_12;           // 0xb4
+	unsigned int cmd_status_13;           // 0xb8
+	unsigned int cmd_status_14;           // 0xbc
+	unsigned int cmd_status_15;           // 0xc0
+	unsigned int cmd_fifo_status;         // 0xc4
+	unsigned int host_interrupt_register; // 0xc8
+	unsigned int host_interrupt_mask;     // 0xcc
+	unsigned int host_exception_address;  // 0xd0
+	unsigned int sp_trust_register;       // 0xd4
+	unsigned int wtm_identification;      // 0xd8
+	unsigned int wtm_revision;            // 0xdc
+};
+
+
+#define WTM_BASE			0xD4290000
+#define WTM_GET_SOC_STEPPING		0x1007
+#define WTM_PRIM_CMD_COMPLETE_MASK	(1 << 0)
+#define WTM_GET_SOC_POWER_POINT		0x1006
+unsigned int mv_ack_from_wtm   = 0x0;
+unsigned int mv_profile_adjust = 0x0;
+unsigned int mv_profile	 = 0x0;
+unsigned int mv_max_freq	 = 0x0;
+unsigned int mv_ts_calibration = 0x0;
+
+unsigned int mv_stepping	 = 0x0;
+unsigned int mv_soc_stepping	 = 0x0;
+
+static volatile struct wtm_mail_box *wtm_mb =
+	(volatile struct wtm_mail_box *)(WTM_BASE);
+
+static int wtm_exe_cmd(struct wtm_cmd *cmd)
+{
+	int i;
+
+	unsigned int *pcmd = &cmd->prim_cmd_parm0;
+	volatile unsigned int *phi = &wtm_mb->prim_cmd_parm0;
+
+	for (i = 0; i <= 16; i++) {
+		*phi++ = *pcmd++;
+	}
+
+	/* try 1000 times */
+	for (i = 0; i < 10000; i++) {
+		if (wtm_mb->host_interrupt_register &
+		    WTM_PRIM_CMD_COMPLETE_MASK) {
+			/* clean interrupt */
+			wtm_mb->host_interrupt_register = 0xFFFFFFFF;
+			return wtm_mb->cmd_return_status;
+		}
+	}
+
+	/* read fail */
+	return -1;
+}
+
+
+int wtm_read_profile(void)
+{
+	struct wtm_cmd cmd;
+	int status;
+
+	memset(&cmd, 0, sizeof(cmd));
+
+	/* valid request */
+	cmd.prim_cmd_parm0 = 0;
+	cmd.secure_processor_cmd = WTM_GET_SOC_POWER_POINT;
+	status = wtm_exe_cmd(&cmd);
+	if (status < 0) {
+		mv_ack_from_wtm = 0;
+		goto out;
+	}
+
+	mv_ack_from_wtm   = 1;
+	mv_profile_adjust = wtm_mb->cmd_status_0;
+	mv_profile	    = wtm_mb->cmd_status_1;
+	mv_max_freq	    = wtm_mb->cmd_status_2;
+	mv_ts_calibration = wtm_mb->cmd_status_3;
+
+out:
+	return status;
+}
+
+static char *mv_stepping_string;
+void wtm_read_stepping(void)
+{
+	struct wtm_cmd cmd;
+	int status;
+
+	unsigned int chip_id;
+	unsigned int id;
+	unsigned int soc_stepping;
+
+	memset(&cmd, 0, sizeof(cmd));
+
+	/* valid request */
+	cmd.prim_cmd_parm0 = 0;
+	cmd.secure_processor_cmd = WTM_GET_SOC_STEPPING;
+	status = wtm_exe_cmd(&cmd);
+	if (status < 0) {
+		printf("wtm read steppping error: %d\n", status);
+	}
+
+	soc_stepping = wtm_mb->cmd_status_0;
+	chip_id      = __raw_readl(0xd4282c00);
+	mv_soc_stepping = soc_stepping;
+	if ((chip_id & 0x00ff0000) == 0x00a00000) {
+
+		if (soc_stepping == 0x4130) {
+			mv_stepping = 0xa0;
+			mv_stepping_string = "A0";
+		}
+		else if (soc_stepping == 0x4131) {
+			mv_stepping = 0xa1;
+			mv_stepping_string = "A1";
+		}
+		else if (soc_stepping == 0x4132) {
+			mv_stepping = 0xa2;
+			mv_stepping_string = "A2";
+		}
+	} else if ((chip_id & 0x00ff0000) == 0x00b00000) {
+		if (soc_stepping == 0x4230) {
+			mv_stepping = 0xb0;
+			mv_stepping_string = "B0";
+		} else if (soc_stepping == 0x423050) {
+			mv_stepping_string = "B0P";
+		} else
+			printf("Unknow cpu stepping!\n");
+	} else
+		printf("Unknow cpu stepping! ");
+}
+
+void wtm_dump_info(void)
+{
+	printf("----- wtm info -----\n");
+
+	if (!mv_ack_from_wtm)
+		printf("wtm has NO ack.\n");
+	else
+		printf("get ack from wtm.\n");
+
+	printf("profile_adjust = 0x%08x\n", mv_profile_adjust);
+	printf("profile        = 0x%08x\n", mv_profile);
+	printf("max_freq       = 0x%08x\n", mv_max_freq);
+	printf("ts_calibration = 0x%08x\n", mv_ts_calibration);
+	printf("stepping       = %s\n", mv_stepping_string);
+
+	printf("-----   end    -----\n\n");
+
+	return;
+}
diff --git a/disk/part.c b/disk/part.c
index f07a17feb8..3d00670236 100644
--- a/disk/part.c
+++ b/disk/part.c
@@ -77,7 +77,7 @@ DECLARE_GLOBAL_DATA_PTR;
 block_dev_desc_t *get_dev(char* ifname, int dev)
 {
 	const struct block_drvr *drvr = block_drvr;
-	block_dev_desc_t* (*reloc_get_dev)(int dev);
+	block_dev_desc_t* (*reloc_get_dev)(int dev), *dev_desc;
 	char *name;
 
 	name = drvr->name;
@@ -91,8 +91,13 @@ block_dev_desc_t *get_dev(char* ifname, int dev)
 		name += gd->reloc_off;
 		reloc_get_dev += gd->reloc_off;
 #endif
-		if (strncmp(ifname, name, strlen(name)) == 0)
-			return reloc_get_dev(dev);
+		if (strncmp(ifname, name, strlen(name)) == 0) {
+			dev_desc = reloc_get_dev(dev);
+			if (dev_desc && dev_desc->dev_init(dev_desc->dev))
+				dev_desc = NULL;
+
+			return dev_desc;
+		}
 		drvr++;
 	}
 	return NULL;
@@ -293,6 +298,20 @@ void init_part (block_dev_desc_t * dev_desc)
 #endif
 }
 
+int get_partition_num (block_dev_desc_t *dev_desc)
+{
+	switch (dev_desc->part_type) {
+#ifdef CONFIG_EFI_PARTITION
+	case PART_TYPE_EFI:
+		return get_partition_num_efi(dev_desc);
+#endif
+#ifdef CONFIG_DOS_PARTITION
+	case PART_TYPE_DOS:
+		return get_partition_num_dos(dev_desc);
+#endif
+	}
+	return 0;
+}
 
 int get_partition_info (block_dev_desc_t *dev_desc, int part
 					, disk_partition_t *info)
diff --git a/disk/part_dos.c b/disk/part_dos.c
index b5bcb3735c..dce0729785 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -258,5 +258,32 @@ int get_partition_info_dos (block_dev_desc_t *dev_desc, int part, disk_partition
 	return get_partition_info_extended (dev_desc, 0, 0, 1, part, info);
 }
 
+int get_partition_num_dos (block_dev_desc_t *dev_desc)
+{
+	unsigned char buffer[dev_desc->blksz];
+	dos_partition_t *pt;
+	int i, num;
+
+	if (dev_desc->block_read(dev_desc->dev, 0, 1, (ulong *) buffer) != 1) {
+		printf ("** Can't read partition table on %d **\n",
+				dev_desc->dev);
+		return -1;
+	}
+	if (buffer[DOS_PART_MAGIC_OFFSET] != 0x55 ||
+			buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa) {
+		printf ("bad MBR sector signature 0x%02x%02x\n",
+				buffer[DOS_PART_MAGIC_OFFSET],
+				buffer[DOS_PART_MAGIC_OFFSET + 1]);
+		return -1;
+	}
 
+	/* Print all primary/logical partitions */
+	pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET);
+	for (i = 0, num = 0; i < 4; i++, pt++) {
+		if (le32_to_int (pt->size4))
+			num++;
+	}
+
+	return num;
+}
 #endif
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 1b04c27cea..0d57efd722 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -35,6 +35,7 @@
 #include <ide.h>
 #include <malloc.h>
 #include "part_efi.h"
+#include <linux/ctype.h>
 
 #if defined(CONFIG_CMD_IDE) || \
     defined(CONFIG_CMD_MG_DISK) || \
@@ -99,6 +100,20 @@ static gpt_entry *alloc_read_gpt_entries(block_dev_desc_t * dev_desc,
 
 static int is_pte_valid(gpt_entry * pte);
 
+static char *print_efiname(gpt_entry *pte)
+{
+	static char name[PARTNAME_SZ + 1];
+	int i;
+	for (i = 0; i < PARTNAME_SZ; i++) {
+		u8 c;
+		c = pte->partition_name[i] & 0xff;
+		c = (c && !isprint(c)) ? '.' : c;
+		name[i] = c;
+	}
+	name[PARTNAME_SZ] = 0;
+	return name;
+}
+
 /*
  * Public Functions (include/part.h)
  */
@@ -106,7 +121,7 @@ static int is_pte_valid(gpt_entry * pte);
 void print_part_efi(block_dev_desc_t * dev_desc)
 {
 	gpt_header gpt_head;
-	gpt_entry **pgpt_pte = NULL;
+	gpt_entry *gpt_pte = NULL;
 	int i = 0;
 
 	if (!dev_desc) {
@@ -115,39 +130,59 @@ void print_part_efi(block_dev_desc_t * dev_desc)
 	}
 	/* This function validates AND fills in the GPT header and PTE */
 	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			 &(gpt_head), pgpt_pte) != 1) {
+			 &(gpt_head), &gpt_pte) != 1) {
 		printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
 		return;
 	}
 
-	debug("%s: gpt-entry at 0x%08X\n", __FUNCTION__, (unsigned int)*pgpt_pte);
+	debug("%s: gpt-entry at 0x%08X\n", __FUNCTION__, (unsigned int)gpt_pte);
 
-	printf("Part  Start LBA  End LBA\n");
+	printf("Part\tName\t\t\tStart LBA\tEnd LBA\n");
 	for (i = 0; i < le32_to_int(gpt_head.num_partition_entries); i++) {
 
-		if (is_pte_valid(&(*pgpt_pte)[i])) {
-			printf("%s%d  0x%llX    0x%llX\n", GPT_ENTRY_NAME,
-				(i + 1),
-				le64_to_int((*pgpt_pte)[i].starting_lba),
-				le64_to_int((*pgpt_pte)[i].ending_lba));
+		if (is_pte_valid(&gpt_pte[i])) {
+			printf("%3d\t%-18s\t0x%08llX\t0x%08llX\n", (i + 1),
+				print_efiname(&gpt_pte[i]),
+				le64_to_int(gpt_pte[i].starting_lba),
+				le64_to_int(gpt_pte[i].ending_lba));
 		} else {
 			break;	/* Stop at the first non valid PTE */
 		}
 	}
 
 	/* Remember to free pte */
-	if (*pgpt_pte != NULL) {
-		debug("%s: Freeing pgpt_pte\n", __FUNCTION__);
-		free(*pgpt_pte);
-	}
+	free(gpt_pte);
 	return;
 }
 
+int get_partition_num_efi(block_dev_desc_t * dev_desc)
+{
+	gpt_header gpt_head;
+	gpt_entry *gpt_pte = NULL;
+	int i;
+
+	if (!dev_desc) {
+		printf("%s: Invalid Argument(s)\n", __FUNCTION__);
+		return 0;
+	}
+	/* This function validates AND fills in the GPT header and PTE */
+	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
+				&(gpt_head), &gpt_pte) != 1) {
+		printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
+		return 0;
+	}
+
+	for (i = 0; i < le32_to_int(gpt_head.num_partition_entries); i++)
+		if (!is_pte_valid(&gpt_pte[i]))
+			break;
+	return i;
+}
+
 int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 				disk_partition_t * info)
 {
 	gpt_header gpt_head;
-	gpt_entry **pgpt_pte = NULL;
+	gpt_entry *gpt_pte = NULL;
 
 	/* "part" argument must be at least 1 */
 	if (!dev_desc || !info || part < 1) {
@@ -157,29 +192,27 @@ int get_partition_info_efi(block_dev_desc_t * dev_desc, int part,
 
 	/* This function validates AND fills in the GPT header and PTE */
 	if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
-			&(gpt_head), pgpt_pte) != 1) {
+			&(gpt_head), &gpt_pte) != 1) {
 		printf("%s: *** ERROR: Invalid GPT ***\n", __FUNCTION__);
 		return -1;
 	}
 
 	/* The ulong casting limits the maximum disk size to 2 TB */
-	info->start = (ulong) le64_to_int((*pgpt_pte)[part - 1].starting_lba);
+	info->start = (ulong) le64_to_int(gpt_pte[part - 1].starting_lba);
 	/* The ending LBA is inclusive, to calculate size, add 1 to it */
-	info->size = ((ulong)le64_to_int((*pgpt_pte)[part - 1].ending_lba) + 1)
+	info->size = ((ulong)le64_to_int(gpt_pte[part - 1].ending_lba) + 1)
 		     - info->start;
 	info->blksz = GPT_BLOCK_SIZE;
 
-	sprintf((char *)info->name, "%s%d", GPT_ENTRY_NAME, part);
+	sprintf((char *)info->name, "%s",
+			print_efiname(&gpt_pte[part - 1]));
 	sprintf((char *)info->type, "U-Boot");
 
 	debug("%s: start 0x%lX, size 0x%lX, name %s", __FUNCTION__,
 		info->start, info->size, info->name);
 
 	/* Remember to free pte */
-	if (*pgpt_pte != NULL) {
-		debug("%s: Freeing pgpt_pte\n", __FUNCTION__);
-		free(*pgpt_pte);
-	}
+	free(gpt_pte);
 	return 0;
 }
 
@@ -333,9 +366,7 @@ static int is_gpt_valid(block_dev_desc_t * dev_desc, unsigned long long lba,
 			le32_to_int(pgpt_head->partition_entry_array_crc32),
 			calc_crc32);
 
-		if (*pgpt_pte != NULL) {
-			free(*pgpt_pte);
-		}
+		free(*pgpt_pte);
 		return 0;
 	}
 
diff --git a/disk/part_efi.h b/disk/part_efi.h
index 6bbb06bde9..5903e7c812 100644
--- a/disk/part_efi.h
+++ b/disk/part_efi.h
@@ -117,13 +117,14 @@ typedef struct _gpt_entry_attributes {
 	unsigned long long type_guid_specific:16;
 } __attribute__ ((packed)) gpt_entry_attributes;
 
+#define PARTNAME_SZ	(72 / sizeof(efi_char16_t))
 typedef struct _gpt_entry {
 	efi_guid_t partition_type_guid;
 	efi_guid_t unique_partition_guid;
 	unsigned char starting_lba[8];
 	unsigned char ending_lba[8];
 	gpt_entry_attributes attributes;
-	efi_char16_t partition_name[72 / sizeof(efi_char16_t)];
+	efi_char16_t partition_name[PARTNAME_SZ];
 }
 __attribute__ ((packed)) gpt_entry;
 
diff --git a/doc/README.arm-caches b/doc/README.arm-caches
index cd2b4587c2..f6a52e3e38 100644
--- a/doc/README.arm-caches
+++ b/doc/README.arm-caches
@@ -40,6 +40,8 @@ Buffer Requirements:
 - If the buffer is not cache-line aligned invalidation will be restricted
   to the aligned part. That is, one cache-line at the respective boundary
   may be left out while doing invalidation.
+- A suitable buffer can be alloced on the stack using the
+  ALLOC_CACHE_ALIGN_BUFFER macro.
 
 Cleanup Before Linux:
 - cleanup_before_linux() should flush the D-cache, invalidate I-cache, and
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 62ec97dfdd..beca1da2a2 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -27,6 +27,7 @@ LIB 	:= $(obj)libgpio.o
 
 COBJS-$(CONFIG_AT91_GPIO)	+= at91_gpio.o
 COBJS-$(CONFIG_KIRKWOOD_GPIO)	+= kw_gpio.o
+COBJS-$(CONFIG_MARVELL_GPIO)	+= mvgpio.o
 COBJS-$(CONFIG_MARVELL_MFP)	+= mvmfp.o
 COBJS-$(CONFIG_MXC_GPIO)	+= mxc_gpio.o
 COBJS-$(CONFIG_PCA953X)		+= pca953x.o
diff --git a/drivers/gpio/kw_gpio.c b/drivers/gpio/kw_gpio.c
index 56383c2875..c86c28fa3c 100644
--- a/drivers/gpio/kw_gpio.c
+++ b/drivers/gpio/kw_gpio.c
@@ -31,6 +31,7 @@
 
 #include <common.h>
 #include <asm/bitops.h>
+#include <asm/io.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/gpio.h>
 
diff --git a/drivers/gpio/mvgpio.c b/drivers/gpio/mvgpio.c
new file mode 100644
index 0000000000..0cc8ed7446
--- /dev/null
+++ b/drivers/gpio/mvgpio.c
@@ -0,0 +1,114 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/errno.h>
+#include <asm/gpio.h>
+
+#ifndef MV_MAX_GPIO
+#define MV_MAX_GPIO	128
+#endif
+
+int gpio_request(int gp, const char *label)
+{
+	if (gp >= MV_MAX_GPIO) {
+		printf("%s: Invalid GPIO requested %d\n", __func__, gp);
+		return -EINVAL;
+	}
+	return 0;
+}
+
+void gpio_free(int gp)
+{
+}
+
+void gpio_toggle_value(int gp)
+{
+	gpio_set_value(gp, !gpio_get_value(gp));
+}
+
+int gpio_direction_input(int gp)
+{
+	struct gpio_reg *gpio_reg_bank;
+
+	if (gp >= MV_MAX_GPIO) {
+		printf("%s: Invalid GPIO %d\n", __func__, gp);
+		return -EINVAL;
+	}
+
+	gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+	writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gcdr);
+	return 0;
+}
+
+int gpio_direction_output(int gp, int value)
+{
+	struct gpio_reg *gpio_reg_bank;
+
+	if (gp >= MV_MAX_GPIO) {
+		printf("%s: Invalid GPIO %d\n", __func__, gp);
+		return -EINVAL;
+	}
+
+	gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+	writel(GPIO_TO_BIT(gp), &gpio_reg_bank->gsdr);
+	gpio_set_value(gp, value);
+	return 0;
+}
+
+int gpio_get_value(int gp)
+{
+	struct gpio_reg *gpio_reg_bank;
+	u32 gp_val;
+
+	if (gp >= MV_MAX_GPIO) {
+		printf("%s: Invalid GPIO %d\n", __func__, gp);
+		return -EINVAL;
+	}
+
+	gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+	gp_val = readl(&gpio_reg_bank->gplr);
+
+	return GPIO_VAL(gp, gp_val);
+}
+
+void gpio_set_value(int gp, int value)
+{
+	struct gpio_reg *gpio_reg_bank;
+
+	if (gp >= MV_MAX_GPIO) {
+		printf("%s: Invalid GPIO %d\n", __func__, gp);
+		return;
+	}
+
+	gpio_reg_bank = get_gpio_base(GPIO_TO_REG(gp));
+	if (value)
+		writel(GPIO_TO_BIT(gp),	&gpio_reg_bank->gpsr);
+	else
+		writel(GPIO_TO_BIT(gp),	&gpio_reg_bank->gpcr);
+}
diff --git a/drivers/gpio/mvmfp.c b/drivers/gpio/mvmfp.c
index e7830c6906..f56c037603 100644
--- a/drivers/gpio/mvmfp.c
+++ b/drivers/gpio/mvmfp.c
@@ -26,13 +26,6 @@
 #include <asm/io.h>
 #include <mvmfp.h>
 #include <asm/arch/mfp.h>
-#ifdef CONFIG_ARMADA100
-#include <asm/arch/armada100.h>
-#elif defined(CONFIG_PANTHEON)
-#include <asm/arch/pantheon.h>
-#else
-#error Unsupported SoC...
-#endif
 
 /*
  * mfp_config
diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c
index dcbe1aefad..2faf0f5bb9 100644
--- a/drivers/i2c/mv_i2c.c
+++ b/drivers/i2c/mv_i2c.c
@@ -67,6 +67,27 @@ struct mv_i2c {
 };
 
 static struct mv_i2c *base;
+static void i2c_board_init(struct mv_i2c * base)
+{
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
+	u32 icr;
+	/*
+	 * call board specific i2c bus reset routine before accessing the
+	 * environment, which might be in a chip on that bus. For details
+	 * about this problem see doc/I2C_Edge_Conditions.
+	 *
+	 * disable I2C controller first, otherwhise it thinks we want to
+	 * talk to the slave port...
+	 */
+	icr = readl(&base->icr);
+	writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
+
+	i2c_init_board();
+
+	writel(icr, &base->icr);
+#endif
+}
+
 #ifdef CONFIG_I2C_MULTI_BUS
 static u32 i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG;
 static unsigned int bus_initialized[CONFIG_MV_I2C_NUM];
@@ -83,7 +104,7 @@ int i2c_set_bus_num(unsigned int bus)
 	current_bus = bus;
 
 	if (!bus_initialized[current_bus]) {
-		i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+		i2c_board_init(base);
 		bus_initialized[current_bus] = 1;
 	}
 
@@ -253,7 +274,7 @@ transfer_error_bus_busy:
 		ret = -6; goto i2c_transfer_finish;
 
 i2c_transfer_finish:
-		PRINTD(("i2c_transfer: ISR: 0x%04x\n", ISR));
+		PRINTD(("i2c_transfer: ISR: 0x%04x\n", readl(&base->isr)));
 		i2c_reset();
 		return ret;
 }
@@ -264,28 +285,13 @@ i2c_transfer_finish:
 void i2c_init(int speed, int slaveaddr)
 {
 #ifdef CONFIG_I2C_MULTI_BUS
+	current_bus = 0;
 	base = (struct mv_i2c *)i2c_regs[current_bus];
 #else
 	base = (struct mv_i2c *)CONFIG_MV_I2C_REG;
 #endif
 
-#ifdef CONFIG_SYS_I2C_INIT_BOARD
-	u32 icr;
-	/*
-	 * call board specific i2c bus reset routine before accessing the
-	 * environment, which might be in a chip on that bus. For details
-	 * about this problem see doc/I2C_Edge_Conditions.
-	 *
-	 * disable I2C controller first, otherwhise it thinks we want to
-	 * talk to the slave port...
-	 */
-	icr = readl(&base->icr);
-	writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr);
-
-	i2c_init_board();
-
-	writel(icr, &base->icr);
-#endif
+	i2c_board_init(base);
 }
 
 /*
@@ -296,25 +302,10 @@ void i2c_init(int speed, int slaveaddr)
  */
 int i2c_probe(uchar chip)
 {
-	struct i2c_msg msg;
+	uchar buf[1];
 
 	i2c_reset();
-
-	msg.condition = I2C_COND_START;
-	msg.acknack   = I2C_ACKNAK_WAITACK;
-	msg.direction = I2C_WRITE;
-	msg.data      = (chip << 1) + 1;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	msg.condition = I2C_COND_STOP;
-	msg.acknack   = I2C_ACKNAK_SENDNAK;
-	msg.direction = I2C_READ;
-	msg.data      = 0x00;
-	if (i2c_transfer(&msg))
-		return -1;
-
-	return 0;
+	return i2c_read(chip, 0, 1, buf, 1);
 }
 
 /*
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 391bc2bafa..f9bf9b2057 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -631,8 +631,6 @@ int mmc_change_freq(struct mmc *mmc)
 	if (mmc->version < MMC_VERSION_4)
 		return 0;
 
-	mmc->card_caps |= MMC_MODE_4BIT;
-
 	err = mmc_send_ext_csd(mmc, ext_csd);
 
 	if (err)
@@ -856,11 +854,11 @@ void mmc_set_bus_width(struct mmc *mmc, uint width)
 
 int mmc_startup(struct mmc *mmc)
 {
-	int err;
+	int err, width;
 	uint mult, freq;
 	u64 cmult, csize, capacity;
 	struct mmc_cmd cmd;
-	char ext_csd[512];
+	char ext_csd[512], test_csd[512];
 	int timeout = 1000;
 
 #ifdef CONFIG_MMC_SPI_CRC_ON
@@ -1072,42 +1070,82 @@ int mmc_startup(struct mmc *mmc)
 			mmc_set_bus_width(mmc, 4);
 		}
 
-		if (mmc->card_caps & MMC_MODE_HS)
-			mmc_set_clock(mmc, 50000000);
-		else
+//		if (mmc->card_caps & MMC_MODE_HS)
+//		{
+//			mmc_set_clock(mmc, 50000000);
+//			printf("A 50M\r\n"); 
+//		}
+//		else
+		{
 			mmc_set_clock(mmc, 25000000);
+			printf("A 25M\r\n");
+		}
 	} else {
-		if (mmc->card_caps & MMC_MODE_4BIT) {
+		for (width = EXT_CSD_BUS_WIDTH_8; width >= 0; width --) {
 			/* Set the card to use 4 bit*/
 			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-					EXT_CSD_BUS_WIDTH,
-					EXT_CSD_BUS_WIDTH_4);
-
-			if (err)
-				return err;
-
-			mmc_set_bus_width(mmc, 4);
-		} else if (mmc->card_caps & MMC_MODE_8BIT) {
-			/* Set the card to use 8 bit*/
-			err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
-					EXT_CSD_BUS_WIDTH,
-					EXT_CSD_BUS_WIDTH_8);
+					EXT_CSD_BUS_WIDTH, width);
 
 			if (err)
-				return err;
+				continue;
 
-			mmc_set_bus_width(mmc, 8);
+			if (!width) {
+				mmc_set_bus_width(mmc, 1);
+				break;
+			} else
+				mmc_set_bus_width(mmc, 4 * width);
+
+			err = mmc_send_ext_csd(mmc, test_csd);
+			if (!err && ext_csd[160] == test_csd[160]
+			    && ext_csd[175] == test_csd[175]
+			    && ext_csd[192] == test_csd[192]
+			    && ext_csd[224] == test_csd[224]
+			    && memcmp(&ext_csd[212], &test_csd[212], 4) == 0) {
+				mmc->card_caps |= width;
+				break;
+			}
 		}
 
 		if (mmc->card_caps & MMC_MODE_HS) {
 			if (mmc->card_caps & MMC_MODE_HS_52MHz)
+			{
 				mmc_set_clock(mmc, 52000000);
+				printf("B 52M \r\n");
+			}
 			else
+			{
 				mmc_set_clock(mmc, 26000000);
+				printf("B 26M \r\n");
+			}
 		} else
+			{
 			mmc_set_clock(mmc, 20000000);
+				printf("B 20M\r\n");
+			}
 	}
 
+	/*
+	 * some card may respond to several commands very slowly just after
+	 * increasing the clock (100khz -> 50mhz with 1G/2G/4G sd card).
+	 * This leads to command timerout error (SD_ERROR_INT_STATUS[0] = 0b1,
+	 * which means no response withine 64 SDCLK)
+	 * so add cmd13 here to avoid send command failure impact.
+	 */
+	cmd.cmdidx = MMC_CMD_SEND_STATUS;
+	cmd.resp_type = MMC_RSP_R1;
+	if (!mmc_host_is_spi(mmc))
+		cmd.cmdarg = mmc->rca << 16;
+	else
+		cmd.cmdarg = 0;
+	cmd.flags = 0;
+	do {
+		err = mmc_send_cmd(mmc, &cmd, NULL);
+		if (!err)
+			break;
+	} while (timeout--);
+	if (!timeout)
+		return err;
+
 	/* fill in device description */
 	mmc->block_dev.lun = 0;
 	mmc->block_dev.type = 0;
@@ -1149,6 +1187,7 @@ int mmc_send_if_cond(struct mmc *mmc)
 	return 0;
 }
 
+static int mmc_dev_init(int dev_num);
 int mmc_register(struct mmc *mmc)
 {
 	/* Setup the universal parts of the block interface just once */
@@ -1158,6 +1197,7 @@ int mmc_register(struct mmc *mmc)
 	mmc->block_dev.block_read = mmc_bread;
 	mmc->block_dev.block_write = mmc_bwrite;
 	mmc->block_dev.block_erase = mmc_berase;
+	mmc->block_dev.dev_init = mmc_dev_init;
 	if (!mmc->b_max)
 		mmc->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
 
@@ -1225,6 +1265,15 @@ int mmc_init(struct mmc *mmc)
 	return err;
 }
 
+static int mmc_dev_init(int dev_num)
+{
+	struct mmc *mmc = find_mmc_device(dev_num);
+	if (!mmc)
+		return -1;
+
+	return mmc_init(mmc);
+}
+
 /*
  * CPU and board-specific MMC initializations.  Aliased function
  * signals caller to move on
diff --git a/drivers/mmc/mv_sdhci.c b/drivers/mmc/mv_sdhci.c
index 9e5995103c..f92caeb8fd 100644
--- a/drivers/mmc/mv_sdhci.c
+++ b/drivers/mmc/mv_sdhci.c
@@ -2,6 +2,33 @@
 #include <malloc.h>
 #include <sdhci.h>
 
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+static struct sdhci_ops mv_ops;
+
+#if defined(CONFIG_SHEEVA_88SV331xV5)
+#define SD_CE_ATA_2	0xEA
+#define  MMC_CARD	0x1000
+#define  MMC_WIDTH	0x0100
+static inline void mv_sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
+{
+	struct mmc *mmc = host->mmc;
+	u32 ata = (u32)host->ioaddr + SD_CE_ATA_2;
+
+	if (!IS_SD(mmc) && reg == SDHCI_HOST_CONTROL) {
+		if (mmc->bus_width == 8)
+			writew(readw(ata) | (MMC_CARD | MMC_WIDTH), ata);
+		else
+			writew(readw(ata) & ~(MMC_CARD | MMC_WIDTH), ata);
+	}
+
+	writeb(val, host->ioaddr + reg);
+}
+
+#else
+#define mv_sdhci_writeb	NULL
+#endif /* CONFIG_SHEEVA_88SV331xV5 */
+#endif /* CONFIG_MMC_SDHCI_IO_ACCESSORS */
+
 static char *MVSDH_NAME = "mv_sdh";
 int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
 {
@@ -15,6 +42,12 @@ int mv_sdh_init(u32 regbase, u32 max_clk, u32 min_clk, u32 quirks)
 	host->name = MVSDH_NAME;
 	host->ioaddr = (void *)regbase;
 	host->quirks = quirks;
+#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
+	memset(&mv_ops, 0, sizeof(struct sdhci_ops));
+	if (mv_sdhci_writeb != NULL)
+		mv_ops.write_b = mv_sdhci_writeb;
+	host->ops = &mv_ops;
+#endif
 	host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
 	add_sdhci(host, max_clk, min_clk);
 	return 0;
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 9ebd33d90e..994d47dabe 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -81,8 +81,9 @@ static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
 static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 				unsigned int start_addr)
 {
-	unsigned int stat, rdy, mask, block = 0;
+	unsigned int stat, rdy, mask, timeout, block = 0;
 
+	timeout = 100000;
 	rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
 	mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
 	do {
@@ -103,11 +104,17 @@ static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data,
 #ifdef CONFIG_MMC_SDMA
 		if (stat & SDHCI_INT_DMA_END) {
 			sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
-			start_addr &= SDHCI_DEFAULT_BOUNDARY_SIZE - 1;
+			start_addr &= ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
 			start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
 			sdhci_writel(host, start_addr, SDHCI_DMA_ADDRESS);
 		}
 #endif
+		if (timeout-- > 0)
+			udelay(10);
+		else {
+			printf("Transfer data timeout\n");
+			return -1;
+		}
 	} while (!(stat & SDHCI_INT_DATA_END));
 	return 0;
 }
@@ -196,7 +203,7 @@ int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
 
 	sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
 #ifdef CONFIG_MMC_SDMA
-	flush_cache(0, ~0);
+	flush_cache(start_addr, trans_bytes);
 #endif
 	sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
 	do {
@@ -377,6 +384,7 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 	}
 
 	mmc->priv = host;
+	host->mmc = mmc;
 
 	sprintf(mmc->name, "%s", host->name);
 	mmc->send_cmd = sdhci_send_command;
@@ -422,7 +430,8 @@ int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk)
 		mmc->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
 	if (caps & SDHCI_CAN_VDD_180)
 		mmc->voltages |= MMC_VDD_165_195;
-	mmc->host_caps = MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
+	mmc->host_caps =
+		MMC_MODE_HC | MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
 	if (caps & SDHCI_CAN_DO_8BIT)
 		mmc->host_caps |= MMC_MODE_8BIT;
 
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 819b197673..34b432217e 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -28,6 +28,7 @@ LIB	:= $(obj)libnet.o
 COBJS-$(CONFIG_DRIVER_3C589) += 3c589.o
 COBJS-$(CONFIG_PPC4xx_EMAC) += 4xx_enet.o
 COBJS-$(CONFIG_ALTERA_TSE) += altera_tse.o
+COBJS-$(CONFIG_ARMADA100_FEC) += armada100_fec.o
 COBJS-$(CONFIG_DRIVER_AT91EMAC) += at91_emac.o
 COBJS-$(CONFIG_DRIVER_AX88180) += ax88180.o
 COBJS-$(CONFIG_BCM570x) += bcm570x.o
diff --git a/drivers/net/armada100_fec.c b/drivers/net/armada100_fec.c
new file mode 100644
index 0000000000..7584e87af2
--- /dev/null
+++ b/drivers/net/armada100_fec.c
@@ -0,0 +1,773 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <common.h>
+#include <net.h>
+#include <malloc.h>
+#include <miiphy.h>
+#include <netdev.h>
+#include <asm/types.h>
+#include <asm/byteorder.h>
+#include <linux/err.h>
+#include <linux/mii.h>
+#include <asm/io.h>
+#include "armada100_fec.h"
+
+#define  MMP3_A0
+#define  PHY_ADR_REQ     0xFF	/* Magic number to read/write PHY address */
+
+#ifdef DEBUG
+static int eth_dump_regs(struct eth_device *dev)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	unsigned int i = 0;
+
+	printf("\noffset: phy_adr, value: 0x%x\n", readl(&regs->phyadr));
+	printf("offset: smi, value: 0x%x\n", readl(&regs->smi));
+	for (i = 0x400; i <= 0x4e4; i += 4)
+		printf("offset: 0x%x, value: 0x%x\n",
+			i, readl((void *)regs + i));
+	return 0;
+}
+#endif
+
+static int armdfec_phy_timeout(u32 *reg, u32 flag, int cond)
+{
+	u32 timeout = PHY_WAIT_ITERATIONS;
+	u32 reg_val;
+
+	while (--timeout) {
+		reg_val = readl(reg);
+		if (cond && (reg_val & flag))
+			break;
+		else if (!cond && !(reg_val & flag))
+			break;
+		udelay(PHY_WAIT_MICRO_SECONDS);
+	}
+	return !timeout;
+}
+
+static int smi_reg_read(const char *devname, u8 phy_addr, u8 phy_reg,
+			u16 *value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	u32 val;
+
+	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+		val = readl(&regs->phyadr);
+		*value = val & 0x1f;
+		return 0;
+	}
+
+	/* check parameters */
+	if (phy_addr > PHY_MASK) {
+		printf("ARMD100 FEC: (%s) Invalid phy address: 0x%X\n",
+				__func__, phy_addr);
+		return -EINVAL;
+	}
+	if (phy_reg > PHY_MASK) {
+		printf("ARMD100 FEC: (%s) Invalid register offset: 0x%X\n",
+				__func__, phy_reg);
+		return -EINVAL;
+	}
+
+	/* wait for the SMI register to become available */
+	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
+		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
+		return -1;
+	}
+
+	writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_R, &regs->smi);
+
+	/* now wait for the data to be valid */
+	if (armdfec_phy_timeout(&regs->smi, SMI_R_VALID, TRUE)) {
+		val = readl(&regs->smi);
+		printf("ARMD100 FEC: (%s) PHY Read timeout, val=0x%x\n",
+				__func__, val);
+		return -1;
+	}
+	val = readl(&regs->smi);
+	*value = val & 0xffff;
+
+	return 0;
+}
+
+static int smi_reg_write(const char *devname,
+	 u8 phy_addr, u8 phy_reg, u16 value)
+{
+	struct eth_device *dev = eth_get_dev_by_name(devname);
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+
+	if (phy_addr == PHY_ADR_REQ && phy_reg == PHY_ADR_REQ) {
+		clrsetbits_le32(&regs->phyadr, 0x1f, value & 0x1f);
+		return 0;
+	}
+
+	/* check parameters */
+	if (phy_addr > PHY_MASK) {
+		printf("ARMD100 FEC: (%s) Invalid phy address\n", __func__);
+		return -EINVAL;
+	}
+	if (phy_reg > PHY_MASK) {
+		printf("ARMD100 FEC: (%s) Invalid register offset\n", __func__);
+		return -EINVAL;
+	}
+
+	/* wait for the SMI register to become available */
+	if (armdfec_phy_timeout(&regs->smi, SMI_BUSY, FALSE)) {
+		printf("ARMD100 FEC: (%s) PHY busy timeout\n",	__func__);
+		return -1;
+	}
+
+	writel((phy_addr << 16) | (phy_reg << 21) | SMI_OP_W | (value & 0xffff),
+			&regs->smi);
+	return 0;
+}
+
+/*
+ * Abort any transmit and receive operations and put DMA
+ * in idle state. AT and AR bits are cleared upon entering
+ * in IDLE state. So poll those bits to verify operation.
+ */
+static void abortdma(struct eth_device *dev)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	int delay;
+	int maxretries = 40;
+	u32 tmp;
+
+	while (--maxretries) {
+		writel(SDMA_CMD_AR | SDMA_CMD_AT, &regs->sdma_cmd);
+		udelay(100);
+
+		delay = 10;
+		while (--delay) {
+			tmp = readl(&regs->sdma_cmd);
+			if (!(tmp & (SDMA_CMD_AR | SDMA_CMD_AT)))
+				break;
+			udelay(10);
+		}
+		if (delay)
+			break;
+	}
+
+	if (!maxretries)
+		printf("ARMD100 FEC: (%s) DMA Stuck\n", __func__);
+}
+
+static inline u32 nibble_swapping_32_bit(u32 x)
+{
+	return ((x & 0xf0f0f0f0) >> 4) | ((x & 0x0f0f0f0f) << 4);
+}
+
+static inline u32 nibble_swapping_16_bit(u32 x)
+{
+	return ((x & 0x0000f0f0) >> 4) | ((x & 0x00000f0f) << 4);
+}
+
+static inline u32 flip_4_bits(u32 x)
+{
+	return ((x & 0x01) << 3) | ((x & 0x002) << 1)
+		| ((x & 0x04) >> 1) | ((x & 0x008) >> 3);
+}
+
+/*
+ * This function will calculate the hash function of the address.
+ * depends on the hash mode and hash size.
+ * Inputs
+ * mach             - the 2 most significant bytes of the MAC address.
+ * macl             - the 4 least significant bytes of the MAC address.
+ * Outputs
+ * return the calculated entry.
+ */
+static u32 hash_function(u32 mach, u32 macl)
+{
+	u32 hashresult;
+	u32 addrh;
+	u32 addrl;
+	u32 addr0;
+	u32 addr1;
+	u32 addr2;
+	u32 addr3;
+	u32 addrhswapped;
+	u32 addrlswapped;
+
+	addrh = nibble_swapping_16_bit(mach);
+	addrl = nibble_swapping_32_bit(macl);
+
+	addrhswapped = flip_4_bits(addrh & 0xf)
+		+ ((flip_4_bits((addrh >> 4) & 0xf)) << 4)
+		+ ((flip_4_bits((addrh >> 8) & 0xf)) << 8)
+		+ ((flip_4_bits((addrh >> 12) & 0xf)) << 12);
+
+	addrlswapped = flip_4_bits(addrl & 0xf)
+		+ ((flip_4_bits((addrl >> 4) & 0xf)) << 4)
+		+ ((flip_4_bits((addrl >> 8) & 0xf)) << 8)
+		+ ((flip_4_bits((addrl >> 12) & 0xf)) << 12)
+		+ ((flip_4_bits((addrl >> 16) & 0xf)) << 16)
+		+ ((flip_4_bits((addrl >> 20) & 0xf)) << 20)
+		+ ((flip_4_bits((addrl >> 24) & 0xf)) << 24)
+		+ ((flip_4_bits((addrl >> 28) & 0xf)) << 28);
+
+	addrh = addrhswapped;
+	addrl = addrlswapped;
+
+	addr0 = (addrl >> 2) & 0x03f;
+	addr1 = (addrl & 0x003) | (((addrl >> 8) & 0x7f) << 2);
+	addr2 = (addrl >> 15) & 0x1ff;
+	addr3 = ((addrl >> 24) & 0x0ff) | ((addrh & 1) << 8);
+
+	hashresult = (addr0 << 9) | (addr1 ^ addr2 ^ addr3);
+	hashresult = hashresult & 0x07ff;
+	return hashresult;
+}
+
+/*
+ * This function will add an entry to the address table.
+ * depends on the hash mode and hash size that was initialized.
+ * Inputs
+ * mach - the 2 most significant bytes of the MAC address.
+ * macl - the 4 least significant bytes of the MAC address.
+ * skip - if 1, skip this address.
+ * rd   - the RD field in the address table.
+ * Outputs
+ * address table entry is added.
+ * 0 if success.
+ * -ENOSPC if table full
+ */
+static int add_del_hash_entry(struct armdfec_device *darmdfec, u32 mach,
+			      u32 macl, u32 rd, u32 skip, int del)
+{
+	struct addr_table_entry_t *entry, *start;
+	u32 newhi;
+	u32 newlo;
+	u32 i;
+
+	newlo = (((mach >> 4) & 0xf) << 15)
+		| (((mach >> 0) & 0xf) << 11)
+		| (((mach >> 12) & 0xf) << 7)
+		| (((mach >> 8) & 0xf) << 3)
+		| (((macl >> 20) & 0x1) << 31)
+		| (((macl >> 16) & 0xf) << 27)
+		| (((macl >> 28) & 0xf) << 23)
+		| (((macl >> 24) & 0xf) << 19)
+		| (skip << HTESKIP) | (rd << HTERDBIT)
+		| HTEVALID;
+
+	newhi = (((macl >> 4) & 0xf) << 15)
+		| (((macl >> 0) & 0xf) << 11)
+		| (((macl >> 12) & 0xf) << 7)
+		| (((macl >> 8) & 0xf) << 3)
+		| (((macl >> 21) & 0x7) << 0);
+
+	/*
+	 * Pick the appropriate table, start scanning for free/reusable
+	 * entries at the index obtained by hashing the specified MAC address
+	 */
+	start = (struct addr_table_entry_t *)(darmdfec->htpr);
+	entry = start + hash_function(mach, macl);
+	for (i = 0; i < HOP_NUMBER; i++) {
+		if (!(entry->lo & HTEVALID)) {
+			break;
+		} else {
+			/* if same address put in same position */
+			if (((entry->lo & 0xfffffff8) == (newlo & 0xfffffff8))
+					&& (entry->hi == newhi))
+				break;
+		}
+		if (entry == start + 0x7ff)
+			entry = start;
+		else
+			entry++;
+	}
+
+	if (((entry->lo & 0xfffffff8) != (newlo & 0xfffffff8)) &&
+		(entry->hi != newhi) && del)
+		return 0;
+
+	if (i == HOP_NUMBER) {
+		if (!del) {
+			printf("ARMD100 FEC: (%s) table section is full\n",
+					__func__);
+			return -ENOSPC;
+		} else {
+			return 0;
+		}
+	}
+
+	/*
+	 * Update the selected entry
+	 */
+	if (del) {
+		entry->hi = 0;
+		entry->lo = 0;
+	} else {
+		entry->hi = newhi;
+		entry->lo = newlo;
+	}
+
+	return 0;
+}
+
+/*
+ *  Create an addressTable entry from MAC address info
+ *  found in the specifed net_device struct
+ *
+ *  Input : pointer to ethernet interface network device structure
+ *  Output : N/A
+ */
+static void update_hash_table_mac_address(struct armdfec_device *darmdfec,
+					  u8 *oaddr, u8 *addr)
+{
+	u32 mach;
+	u32 macl;
+
+	/* Delete old entry */
+	if (oaddr) {
+		mach = (oaddr[0] << 8) | oaddr[1];
+		macl = (oaddr[2] << 24) | (oaddr[3] << 16) |
+			(oaddr[4] << 8) | oaddr[5];
+		add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_DELETE);
+	}
+
+	/* Add new entry */
+	mach = (addr[0] << 8) | addr[1];
+	macl = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
+	add_del_hash_entry(darmdfec, mach, macl, 1, 0, HASH_ADD);
+}
+
+/* Address Table Initialization */
+static void init_hashtable(struct eth_device *dev)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	memset(darmdfec->htpr, 0, HASH_ADDR_TABLE_SIZE);
+	writel((u32)darmdfec->htpr, &regs->htpr);
+}
+
+/*
+ * This detects PHY chip from address 0-31 by reading PHY status
+ * registers. PHY chip can be connected at any of this address.
+ */
+static int ethernet_phy_detect(struct eth_device *dev)
+{
+	u32 val;
+	u16 tmp, mii_status;
+	u8 addr;
+
+	for (addr = 0; addr < 32; addr++) {
+		if (miiphy_read(dev->name, addr, MII_BMSR, &mii_status)	!= 0)
+			/* try next phy */
+			continue;
+
+		/* invalid MII status. More validation required here... */
+		if (mii_status == 0 || mii_status == 0xffff)
+			/* try next phy */
+			continue;
+
+		if (miiphy_read(dev->name, addr, MII_PHYSID1, &tmp) != 0)
+			/* try next phy */
+			continue;
+
+		val = tmp << 16;
+		if (miiphy_read(dev->name, addr, MII_PHYSID2, &tmp) != 0)
+			/* try next phy */
+			continue;
+
+		val |= tmp;
+
+		if ((val & 0xfffffff0) != 0)
+			return addr;
+	}
+	return -1;
+}
+
+static void armdfec_init_rx_desc_ring(struct armdfec_device *darmdfec)
+{
+	struct rx_desc *p_rx_desc;
+	int i;
+
+	/* initialize the Rx descriptors ring */
+	p_rx_desc = darmdfec->p_rxdesc;
+	for (i = 0; i < RINGSZ; i++) {
+		p_rx_desc->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
+		p_rx_desc->buf_size = PKTSIZE_ALIGN;
+		p_rx_desc->byte_cnt = 0;
+		p_rx_desc->buf_ptr = darmdfec->p_rxbuf + i * PKTSIZE_ALIGN;
+		if (i == (RINGSZ - 1)) {
+			p_rx_desc->nxtdesc_p = darmdfec->p_rxdesc;
+		} else {
+			p_rx_desc->nxtdesc_p = (struct rx_desc *)
+			    ((u32)p_rx_desc + ARMDFEC_RXQ_DESC_ALIGNED_SIZE);
+			p_rx_desc = p_rx_desc->nxtdesc_p;
+		}
+	}
+	darmdfec->p_rxdesc_curr = darmdfec->p_rxdesc;
+}
+
+static int armdfec_init(struct eth_device *dev, bd_t *bd)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	int phy_adr;
+
+	armdfec_init_rx_desc_ring(darmdfec);
+
+	/* Disable interrupts */
+	writel(0, &regs->im);
+	writel(0, &regs->ic);
+	/* Write to ICR to clear interrupts. */
+	writel(0, &regs->iwc);
+
+	/*
+	 * Abort any transmit and receive operations and put DMA
+	 * in idle state.
+	 */
+	abortdma(dev);
+
+	/* Initialize address hash table */
+	init_hashtable(dev);
+
+	/* SDMA configuration */
+	writel(SDCR_BSZ8 |	/* Burst size = 32 bytes */
+		SDCR_RIFB |	/* Rx interrupt on frame */
+		SDCR_BLMT |	/* Little endian transmit */
+		SDCR_BLMR |	/* Little endian receive */
+		SDCR_RC_MAX_RETRANS,	/* Max retransmit count */
+		&regs->sdma_conf);
+	/* Port Configuration */
+	writel(PCR_HS, &regs->pconf);	/* Hash size is 1/2kb */
+
+	/* Set extended port configuration */
+	writel(PCXR_2BSM |		/* Two byte suffix aligns IP hdr */
+		PCXR_DSCP_EN |		/* Enable DSCP in IP */
+		PCXR_MFL_1536 |		/* Set MTU = 1536 */
+		PCXR_FLP |		/* do not force link pass */
+		PCXR_TX_HIGH_PRI,	/* Transmit - high priority queue */
+		&regs->pconf_ext);
+
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
+
+#if defined(CONFIG_PHY_BASE_ADR)
+        miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, CONFIG_PHY_BASE_ADR);
+#else
+        /* Search phy address from range 0-31 */
+        phy_adr = ethernet_phy_detect(dev);
+        if (phy_adr < 0) {
+                printf("ARMD100 FEC: PHY not detected at address range 0-31\n");
+                return -1;
+        } else {
+                debug("ARMD100 FEC: PHY detected at addr %d\n", phy_adr);
+                miiphy_write(dev->name, PHY_ADR_REQ, PHY_ADR_REQ, phy_adr);
+        }
+#endif
+#endif
+
+	/* reset the PHY and wait it out of reset state */
+        miiphy_reset(dev->name, phy_adr);
+#if defined(MMP3_A0)
+	fe_phy_regs_set(dev->name, phy_adr);
+#endif
+
+        u32 advert, bmcr;
+        /*
+	 * set the advertisement control register to autonegotiate about
+	 * speed, work mode(full/half duplex) etc.
+	 */
+        advert = ADVERTISE_CSMA | ADVERTISE_10HALF | ADVERTISE_10FULL |
+                 ADVERTISE_100HALF | ADVERTISE_100FULL | ADVERTISE_PAUSE_CAP;
+        if (miiphy_write(dev->name, phy_adr, MII_ADVERTISE, advert) != 0)
+                printf("write advertisement control register failed\n");
+        /* turn on autonegotiation and force a renegotiate */
+        bmcr = BMCR_ANENABLE | BMCR_FULLDPLX | BMCR_ANRESTART;
+        if (miiphy_write(dev->name, phy_adr, MII_BMCR, bmcr) != 0)
+                printf("write basic mode control register failed\n");
+
+	update_hash_table_mac_address(darmdfec, NULL, dev->enetaddr);
+
+	/* Update TX and RX queue descriptor register */
+	writel((u32)darmdfec->p_txdesc, &regs->txcdp[TXQ]);
+	writel((u32)darmdfec->p_rxdesc, &regs->rxfdp[RXQ]);
+	writel((u32)darmdfec->p_rxdesc_curr, &regs->rxcdp[RXQ]);
+
+	/* Enable Interrupts */
+	writel(ALL_INTS, &regs->im);
+
+	/* Enable Ethernet Port */
+	setbits_le32(&regs->pconf, PCR_EN);
+
+	flush_cache((unsigned long)darmdfec->htpr, HASH_ADDR_TABLE_SIZE);
+	flush_cache((unsigned long)darmdfec->p_rxdesc, (RINGSZ + 1) * PKTALIGN);
+	flush_cache((unsigned long)darmdfec->p_rxbuf,
+		(RINGSZ * PKTSIZE_ALIGN / PKTALIGN + 1) * PKTALIGN);
+	/* Enable RX DMA engine */
+	setbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
+
+#ifdef DEBUG
+	eth_dump_regs(dev);
+#endif
+
+#if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
+
+#if defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
+	/* Wait up to 5s for the link status */
+	int i;
+	for (i = 0; i < 5; i++) {
+		u16 phy_adr;
+
+		miiphy_read(dev->name, 0xFF, 0xFF, &phy_adr);
+		/* Return if we get link up */
+		if (miiphy_link(dev->name, phy_adr))
+			return 0;
+		udelay(1000000);
+	}
+
+	printf("ARMD100 FEC: No link on %s\n", dev->name);
+	return -1;
+#endif
+#endif
+	return 0;
+}
+
+static void armdfec_halt(struct eth_device *dev)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+
+	/* Stop RX DMA */
+	clrbits_le32(&regs->sdma_cmd, SDMA_CMD_ERD);
+
+	/*
+	 * Abort any transmit and receive operations and put DMA
+	 * in idle state.
+	 */
+	abortdma(dev);
+
+	/* Disable interrupts */
+	writel(0, &regs->im);
+	writel(0, &regs->ic);
+	writel(0, &regs->iwc);
+
+	/* Disable Port */
+	clrbits_le32(&regs->pconf, PCR_EN);
+}
+
+static int armdfec_send(struct eth_device *dev, volatile void *dataptr,
+		    int datasize)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct armdfec_reg *regs = darmdfec->regs;
+	struct tx_desc *p_txdesc = darmdfec->p_txdesc;
+	void *p = (void *)dataptr;
+	int retry = PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS;
+	u32 cmd_sts;
+
+	/* Copy buffer if it's misaligned */
+	if ((u32)dataptr & 0x07) {
+		if (datasize > PKTSIZE_ALIGN) {
+			printf("ARMD100 FEC: Non-aligned data too large (%d)\n",
+					datasize);
+			return -1;
+		}
+		memcpy(darmdfec->p_aligned_txbuf, p, datasize);
+		p = darmdfec->p_aligned_txbuf;
+	}
+
+	p_txdesc->cmd_sts = TX_ZERO_PADDING | TX_GEN_CRC;
+	p_txdesc->cmd_sts |= TX_FIRST_DESC | TX_LAST_DESC;
+	p_txdesc->cmd_sts |= BUF_OWNED_BY_DMA;
+	p_txdesc->cmd_sts |= TX_EN_INT;
+	p_txdesc->buf_ptr = p;
+	p_txdesc->byte_cnt = datasize;
+
+	/* Apply send command using high priority TX queue */
+	writel((u32)p_txdesc, &regs->txcdp[TXQ]);
+	flush_cache((unsigned long)p, datasize);
+	flush_cache((unsigned long)p_txdesc, PKTALIGN);
+	writel(SDMA_CMD_TXDL | SDMA_CMD_TXDH | SDMA_CMD_ERD, &regs->sdma_cmd);
+
+	/*
+	 * wait for packet xmit completion
+	 */
+	cmd_sts = readl(&p_txdesc->cmd_sts);
+	while (cmd_sts & BUF_OWNED_BY_DMA) {
+		/* return fail if error is detected */
+		if ((cmd_sts & (TX_ERROR | TX_LAST_DESC)) ==
+			(TX_ERROR | TX_LAST_DESC)) {
+			printf("ARMD100 FEC: (%s) in xmit packet\n", __func__);
+			return -1;
+		}
+		invalidate_dcache_range((unsigned long)p_txdesc,
+			(unsigned long)((void *)p_txdesc + PKTALIGN));
+		cmd_sts = readl(&p_txdesc->cmd_sts);
+		if (!(retry--)) {
+			printf("ARMD100 FEC: (%s) xmit packet timeout!\n",
+					__func__);
+			return -1;
+		}
+	}
+
+	return 0;
+}
+
+static int armdfec_recv(struct eth_device *dev)
+{
+	struct armdfec_device *darmdfec = to_darmdfec(dev);
+	struct rx_desc *p_rxdesc_curr = darmdfec->p_rxdesc_curr;
+	u32 cmd_sts;
+	u32 timeout = 0;
+
+	/* wait untill rx packet available or timeout */
+	do {
+		invalidate_dcache_range((unsigned long)p_rxdesc_curr,
+			(unsigned long)((void *)p_rxdesc_curr + PKTALIGN));
+		if (timeout < PHY_WAIT_ITERATIONS * PHY_WAIT_MICRO_SECONDS) {
+			timeout++;
+		} else {
+			debug("ARMD100 FEC: %s time out...\n", __func__);
+			return -1;
+		}
+	} while (readl(&p_rxdesc_curr->cmd_sts) & BUF_OWNED_BY_DMA);
+
+	if (p_rxdesc_curr->byte_cnt != 0) {
+		debug("ARMD100 FEC: %s: Received %d byte Packet @ 0x%x"
+				"(cmd_sts= %08x)\n", __func__,
+				(u32)p_rxdesc_curr->byte_cnt,
+				(u32)p_rxdesc_curr->buf_ptr,
+				(u32)p_rxdesc_curr->cmd_sts);
+	}
+
+	/*
+	 * In case received a packet without first/last bits on
+	 * OR the error summary bit is on,
+	 * the packets needs to be dropeed.
+	 */
+	cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
+
+	if ((cmd_sts & (RX_FIRST_DESC | RX_LAST_DESC)) !=
+			(RX_FIRST_DESC | RX_LAST_DESC)) {
+		printf("ARMD100 FEC: (%s) Dropping packet spread on"
+			" multiple descriptors\n", __func__);
+	} else if (cmd_sts & RX_ERROR) {
+		printf("ARMD100 FEC: (%s) Dropping packet with errors\n",
+				__func__);
+	} else {
+		/* !!! call higher layer processing */
+		debug("ARMD100 FEC: (%s) Sending Received packet to"
+			" upper layer (NetReceive)\n", __func__);
+
+		/*
+		 * let the upper layer handle the packet, subtract offset
+		 * as two dummy bytes are added in received buffer see
+		 * PORT_CONFIG_EXT register bit TWO_Byte_Stuff_Mode bit.
+		 */
+		NetReceive((p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET),
+			   (int)(p_rxdesc_curr->byte_cnt - RX_BUF_OFFSET));
+		invalidate_dcache_range((unsigned long)p_rxdesc_curr->buf_ptr,
+			(unsigned long)(p_rxdesc_curr->buf_ptr + PKTSIZE_ALIGN));
+	}
+	/*
+	 * free these descriptors and point next in the ring
+	 */
+	p_rxdesc_curr->cmd_sts = BUF_OWNED_BY_DMA | RX_EN_INT;
+	p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
+	p_rxdesc_curr->byte_cnt = 0;
+	flush_cache((unsigned long)p_rxdesc_curr, PKTALIGN);
+
+	writel((u32)p_rxdesc_curr->nxtdesc_p, (u32)&darmdfec->p_rxdesc_curr);
+
+	return 0;
+}
+
+int armada100_fec_register(unsigned long base_addr)
+{
+	struct armdfec_device *darmdfec;
+	struct eth_device *dev;
+
+	darmdfec = malloc(sizeof(struct armdfec_device));
+	if (!darmdfec)
+		goto error;
+
+	memset(darmdfec, 0, sizeof(struct armdfec_device));
+
+	darmdfec->htpr = memalign(8, HASH_ADDR_TABLE_SIZE);
+	if (!darmdfec->htpr)
+		goto error1;
+
+	darmdfec->p_rxdesc = memalign(PKTALIGN,
+			ARMDFEC_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
+
+	if (!darmdfec->p_rxdesc)
+		goto error1;
+
+	darmdfec->p_rxbuf = memalign(PKTALIGN, RINGSZ * PKTSIZE_ALIGN + 1);
+	if (!darmdfec->p_rxbuf)
+		goto error1;
+
+	darmdfec->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
+	if (!darmdfec->p_aligned_txbuf)
+		goto error1;
+
+	darmdfec->p_txdesc = memalign(PKTALIGN, sizeof(struct tx_desc) + 1);
+	if (!darmdfec->p_txdesc)
+		goto error1;
+
+	dev = &darmdfec->dev;
+	/* Assign ARMADA100 Fast Ethernet Controller Base Address */
+	darmdfec->regs = (void *)base_addr;
+
+	/* must be less than NAMESIZE (16) */
+	strcpy(dev->name, "armd-fec0");
+
+	dev->init = armdfec_init;
+	dev->halt = armdfec_halt;
+	dev->send = armdfec_send;
+	dev->recv = armdfec_recv;
+
+	eth_register(dev);
+
+#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
+	miiphy_register(dev->name, smi_reg_read, smi_reg_write);
+#endif
+	return 0;
+
+error1:
+	free(darmdfec->p_aligned_txbuf);
+	free(darmdfec->p_rxbuf);
+	free(darmdfec->p_rxdesc);
+	free(darmdfec->htpr);
+error:
+	free(darmdfec);
+	printf("AMD100 FEC: (%s) Failed to allocate memory\n", __func__);
+	return -1;
+}
diff --git a/drivers/net/armada100_fec.h b/drivers/net/armada100_fec.h
new file mode 100644
index 0000000000..e2df4fcb87
--- /dev/null
+++ b/drivers/net/armada100_fec.h
@@ -0,0 +1,232 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ * Contributor: Mahavir Jain <mjain@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __ARMADA100_FEC_H__
+#define __ARMADA100_FEC_H__
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#define PORT_NUM		0x0
+
+/* RX & TX descriptor command */
+#define BUF_OWNED_BY_DMA        (1<<31)
+
+/* RX descriptor status */
+#define RX_EN_INT               (1<<23)
+#define RX_FIRST_DESC           (1<<17)
+#define RX_LAST_DESC            (1<<16)
+#define RX_ERROR                (1<<15)
+
+/* TX descriptor command */
+#define TX_EN_INT               (1<<23)
+#define TX_GEN_CRC              (1<<22)
+#define TX_ZERO_PADDING         (1<<18)
+#define TX_FIRST_DESC           (1<<17)
+#define TX_LAST_DESC            (1<<16)
+#define TX_ERROR                (1<<15)
+
+/* smi register */
+#define SMI_BUSY                (1<<28)	/* 0 - Write, 1 - Read  */
+#define SMI_R_VALID             (1<<27)	/* 0 - Write, 1 - Read  */
+#define SMI_OP_W                (0<<26)	/* Write operation      */
+#define SMI_OP_R                (1<<26)	/* Read operation */
+
+#define HASH_ADD                0
+#define HASH_DELETE             1
+#define HASH_ADDR_TABLE_SIZE    0x4000	/* 16K (1/2K address - PCR_HS == 1) */
+#define HOP_NUMBER              12
+
+#define PHY_WAIT_ITERATIONS     1000	/* 1000 iterations * 10uS = 10mS max */
+#define PHY_WAIT_MICRO_SECONDS  10
+
+#define ETH_HW_IP_ALIGN         2	/* hw aligns IP header */
+#define ETH_EXTRA_HEADER        (6+6+2+4)
+					/* dest+src addr+protocol id+crc */
+#define MAX_PKT_SIZE            1536
+
+
+/* Bit definitions of the SDMA Config Reg */
+#define SDCR_BSZ_OFF            12
+#define SDCR_BSZ8               (3<<SDCR_BSZ_OFF)
+#define SDCR_BSZ4               (2<<SDCR_BSZ_OFF)
+#define SDCR_BSZ2               (1<<SDCR_BSZ_OFF)
+#define SDCR_BSZ1               (0<<SDCR_BSZ_OFF)
+#define SDCR_BLMR               (1<<6)
+#define SDCR_BLMT               (1<<7)
+#define SDCR_RIFB               (1<<9)
+#define SDCR_RC_OFF             2
+#define SDCR_RC_MAX_RETRANS     (0xf << SDCR_RC_OFF)
+
+/* SDMA_CMD */
+#define SDMA_CMD_AT             (1<<31)
+#define SDMA_CMD_TXDL           (1<<24)
+#define SDMA_CMD_TXDH           (1<<23)
+#define SDMA_CMD_AR             (1<<15)
+#define SDMA_CMD_ERD            (1<<7)
+
+
+/* Bit definitions of the Port Config Reg */
+#define PCR_HS                  (1<<12)
+#define PCR_EN                  (1<<7)
+#define PCR_PM                  (1<<0)
+
+/* Bit definitions of the Port Config Extend Reg */
+#define PCXR_2BSM               (1<<28)
+#define PCXR_DSCP_EN            (1<<21)
+#define PCXR_MFL_1518           (0<<14)
+#define PCXR_MFL_1536           (1<<14)
+#define PCXR_MFL_2048           (2<<14)
+#define PCXR_MFL_64K            (3<<14)
+#define PCXR_FLP                (1<<11)
+#define PCXR_PRIO_TX_OFF        3
+#define PCXR_TX_HIGH_PRI        (7<<PCXR_PRIO_TX_OFF)
+
+/*
+ *  * Bit definitions of the Interrupt Cause Reg
+ *   * and Interrupt MASK Reg is the same
+ *    */
+#define ICR_RXBUF               (1<<0)
+#define ICR_TXBUF_H             (1<<2)
+#define ICR_TXBUF_L             (1<<3)
+#define ICR_TXEND_H             (1<<6)
+#define ICR_TXEND_L             (1<<7)
+#define ICR_RXERR               (1<<8)
+#define ICR_TXERR_H             (1<<10)
+#define ICR_TXERR_L             (1<<11)
+#define ICR_TX_UDR              (1<<13)
+#define ICR_MII_CH              (1<<28)
+
+#define ALL_INTS (ICR_TXBUF_H  | ICR_TXBUF_L  | ICR_TX_UDR |\
+				ICR_TXERR_H  | ICR_TXERR_L |\
+				ICR_TXEND_H  | ICR_TXEND_L |\
+				ICR_RXBUF | ICR_RXERR  | ICR_MII_CH)
+
+#define PHY_MASK               0x0000001f
+
+#define to_darmdfec(_kd) container_of(_kd, struct armdfec_device, dev)
+/* Size of a Tx/Rx descriptor used in chain list data structure */
+#define ARMDFEC_RXQ_DESC_ALIGNED_SIZE \
+	(((sizeof(struct rx_desc) / PKTALIGN) + 1) * PKTALIGN)
+
+#define RX_BUF_OFFSET		0x2
+#define RXQ			0x0	/* RX Queue 0 */
+#define TXQ			0x1	/* TX Queue 1 */
+
+struct addr_table_entry_t {
+	u32 lo;
+	u32 hi;
+};
+
+/* Bit fields of a Hash Table Entry */
+enum hash_table_entry {
+	HTEVALID = 1,
+	HTESKIP = 2,
+	HTERD = 4,
+	HTERDBIT = 2
+};
+
+struct tx_desc {
+	u32 cmd_sts;		/* Command/status field */
+	u16 reserved;
+	u16 byte_cnt;		/* buffer byte count */
+	u8 *buf_ptr;		/* pointer to buffer for this descriptor */
+	struct tx_desc *nextdesc_p;	/* Pointer to next descriptor */
+};
+
+struct rx_desc {
+	u32 cmd_sts;		/* Descriptor command status */
+	u16 byte_cnt;		/* Descriptor buffer byte count */
+	u16 buf_size;		/* Buffer size */
+	u8 *buf_ptr;		/* Descriptor buffer pointer */
+	struct rx_desc *nxtdesc_p;	/* Next descriptor pointer */
+};
+
+/*
+ * Armada100 Fast Ethernet controller Registers
+ * Refer Datasheet Appendix A.22
+ */
+struct armdfec_reg {
+	u32 phyadr;			/* PHY Address */
+	u32 pad1[3];
+	u32 smi;			/* SMI */
+	u32 pad2[0xFB];
+	u32 pconf;			/* Port configuration */
+	u32 pad3;
+	u32 pconf_ext;			/* Port configuration extend */
+	u32 pad4;
+	u32 pcmd;			/* Port Command */
+	u32 pad5;
+	u32 pstatus;			/* Port Status */
+	u32 pad6;
+	u32 spar;			/* Serial Parameters */
+	u32 pad7;
+	u32 htpr;			/* Hash table pointer */
+	u32 pad8;
+	u32 fcsal;			/* Flow control source address low */
+	u32 pad9;
+	u32 fcsah;			/* Flow control source address high */
+	u32 pad10;
+	u32 sdma_conf;			/* SDMA configuration */
+	u32 pad11;
+	u32 sdma_cmd;			/* SDMA command */
+	u32 pad12;
+	u32 ic;				/* Interrupt cause */
+	u32 iwc;			/* Interrupt write to clear */
+	u32 im;				/* Interrupt mask */
+	u32 pad13;
+	u32 *eth_idscpp[4];		/* Eth0 IP Differentiated Services Code
+					   Point to Priority 0 Low */
+	u32 eth_vlan_p;			/* Eth0 VLAN Priority Tag to Priority */
+	u32 pad14[3];
+	struct rx_desc *rxfdp[4];	/* Ethernet First Rx Descriptor
+					   Pointer */
+	u32 pad15[4];
+	struct rx_desc *rxcdp[4];	/* Ethernet Current Rx Descriptor
+					   Pointer */
+	u32 pad16[0x0C];
+	struct tx_desc *txcdp[2];	/* Ethernet Current Tx Descriptor
+					   Pointer */
+};
+
+struct armdfec_device {
+	struct eth_device dev;
+	struct armdfec_reg *regs;
+	struct tx_desc *p_txdesc;
+	struct rx_desc *p_rxdesc;
+	struct rx_desc *p_rxdesc_curr;
+	u8 *p_rxbuf;
+	u8 *p_aligned_txbuf;
+	u8 *htpr;		/* hash pointer */
+};
+
+#endif /* __ARMADA100_FEC_H__ */
diff --git a/drivers/net/mvgbe.c b/drivers/net/mvgbe.c
index c701f43ad6..c7f74467b9 100644
--- a/drivers/net/mvgbe.c
+++ b/drivers/net/mvgbe.c
@@ -32,8 +32,10 @@
 #include <net.h>
 #include <malloc.h>
 #include <miiphy.h>
+#include <asm/io.h>
 #include <asm/errno.h>
 #include <asm/types.h>
+#include <asm/system.h>
 #include <asm/byteorder.h>
 
 #if defined(CONFIG_KIRKWOOD)
diff --git a/drivers/power/Makefile b/drivers/power/Makefile
index ead00f8dae..555c97d1cc 100644
--- a/drivers/power/Makefile
+++ b/drivers/power/Makefile
@@ -28,10 +28,18 @@ LIB 	:= $(obj)libpower.o
 COBJS-$(CONFIG_FTPMU010_POWER)	+= ftpmu010.o
 COBJS-$(CONFIG_TWL4030_POWER)	+= twl4030.o
 COBJS-$(CONFIG_TWL6030_POWER)	+= twl6030.o
+COBJS-$(CONFIG_MMP_POWER)	+= mmp_freq.o
+ifeq ($(CONFIG_MACH_MMP2),y)
+SOBJS-$(CONFIG_MMP_POWER)	+= mmp2_dvfm_ll.o
+endif
+COBJS-$(CONFIG_POWEROFF_CHARGE)		+= charge.o
+COBJS-$(CONFIG_MAX17042_BATTERY)	+= max17042_battery.o
+
 
 COBJS	:= $(COBJS-y)
-SRCS 	:= $(COBJS:.o=.c)
-OBJS 	:= $(addprefix $(obj),$(COBJS))
+SOBJS	:= $(sort $(SOBJS-y))
+SRCS 	:= $(COBJS:.o=.c) $(SOBJS:.o=.S)
+OBJS 	:= $(addprefix $(obj),$(COBJS) $(SOBJS))
 
 all:	$(LIB)
 
diff --git a/drivers/power/battery00.h b/drivers/power/battery00.h
new file mode 100644
index 0000000000..afbd095123
--- /dev/null
+++ b/drivers/power/battery00.h
@@ -0,0 +1,1545 @@
+// Generate By BMP to RAW Conveter, By Leajian
+
+const unsigned char RES_battery00_BIN[] = {
+	/* Source File: C:\Documents and Settings\zhaoy\Desktop\tupian\2\2\total\2\2\battery00.bin */
+	/* File Size: 24574 Bytes */
+
+/*0x00*/	                                                 0x20, 0x00, 0xaa, 0x52, 0x30, 0x84, 0xd2, 0x94,
+/*0x10*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x20*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x30*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x40*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x50*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x60*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x70*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x80*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x90*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xa0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xb0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xc0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xd0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xe0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0xf0*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x100*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x110*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x120*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x130*/	0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,  0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94, 0xd2, 0x94,
+/*0x140*/	0x30, 0x84, 0x69, 0x4a, 0x20, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x150*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x160*/	0x00, 0x00, 0xcb, 0x5a, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x170*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x180*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x190*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1a0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1b0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1c0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1d0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1e0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x1f0*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x200*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x210*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x220*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x230*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x240*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x250*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x260*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x270*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x280*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,
+/*0x290*/	0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5,  0x13, 0xa5, 0x13, 0xa5, 0x13, 0xa5, 0xaa, 0x52,
+/*0x2a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x2b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0xf3, 0x9c, 0x75, 0xad,
+/*0x2c0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x2d0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x2e0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x2f0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x300*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x310*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x320*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x330*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x340*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x350*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x360*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x370*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x380*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x390*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3a0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3b0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3c0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3d0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3e0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x3f0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0xf3, 0x9c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x400*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x410*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb6, 0xb5,  0xb6, 0xb5, 0xb6, 0xb5, 0xb6, 0xb5, 0xb6, 0xb5,
+/*0x420*/	0x95, 0xb5, 0xca, 0x5a, 0x82, 0x10, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x430*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x440*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x450*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x460*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x470*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x480*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x490*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x500*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x510*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x520*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x530*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x540*/	0x00, 0x00, 0x00, 0x00, 0x82, 0x10, 0xca, 0x5a,  0x95, 0xb5, 0xb6, 0xb5, 0xb6, 0xb5, 0xb6, 0xb5,
+/*0x550*/	0xb6, 0xb5, 0xb6, 0xb5, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x560*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x570*/	0x17, 0xc6, 0x17, 0xc6, 0x17, 0xc6, 0x17, 0xc6,  0x17, 0xc6, 0xcb, 0x5a, 0x00, 0x00, 0x00, 0x00,
+/*0x580*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x590*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x600*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x610*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x620*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x630*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x640*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x650*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x660*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x670*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x680*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x690*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x6a0*/	0x00, 0x00, 0xcb, 0x5a, 0x17, 0xc6, 0x17, 0xc6,  0x17, 0xc6, 0x17, 0xc6, 0x17, 0xc6, 0x00, 0x00,
+/*0x6b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x6c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x79, 0xce, 0x79, 0xce, 0x79, 0xce,
+/*0x6d0*/	0x79, 0xce, 0x79, 0xce, 0x82, 0x10, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x6e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x6f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x700*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x710*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x720*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x730*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x740*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x750*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x760*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x770*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x780*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x790*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x7f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x82, 0x10, 0x79, 0xce,
+/*0x800*/	0x79, 0xce, 0x79, 0xce, 0x79, 0xce, 0x79, 0xce,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x810*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x820*/	0x00, 0x00, 0x00, 0x00, 0xba, 0xd6, 0xba, 0xd6,  0xba, 0xd6, 0xba, 0xd6, 0xba, 0xd6, 0x00, 0x00,
+/*0x830*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x840*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x850*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x860*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x870*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x880*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x890*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x8f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x900*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x910*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x920*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x930*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x940*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x950*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0xba, 0xd6, 0xba, 0xd6, 0xba, 0xd6, 0xba, 0xd6,
+/*0x960*/	0xba, 0xd6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x970*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1b, 0xe7,
+/*0x980*/	0x1b, 0xe7, 0x1b, 0xe7, 0x1b, 0xe7, 0x1b, 0xe7,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x990*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x9f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa00*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa10*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa20*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa30*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa40*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa50*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa60*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa70*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa80*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xa90*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xaa0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xab0*/	0x00, 0x00, 0x1b, 0xe7, 0x1b, 0xe7, 0x1b, 0xe7,  0x1b, 0xe7, 0x1b, 0xe7, 0x00, 0x00, 0x00, 0x00,
+/*0xac0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xad0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x5d, 0xef, 0x5d, 0xef, 0x5d, 0xef, 0x5d, 0xef,
+/*0xae0*/	0x5d, 0xef, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xaf0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb00*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb10*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb20*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb30*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb40*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb50*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb60*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb70*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb80*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xb90*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xba0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xbb0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xbc0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xbd0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xbe0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xbf0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc00*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x5d, 0xef, 0x5d, 0xef,
+/*0xc10*/	0x5d, 0xef, 0x5d, 0xef, 0x5d, 0xef, 0x30, 0x84,  0x4c, 0x6b, 0x04, 0x21, 0x00, 0x00, 0x00, 0x00,
+/*0xc20*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xc30*/	0x00, 0x00, 0x9e, 0xf7, 0x9e, 0xf7, 0x9e, 0xf7,  0x9e, 0xf7, 0x9e, 0xf7, 0x20, 0x00, 0x20, 0x00,
+/*0xc40*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc50*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc60*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc70*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc80*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xc90*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xca0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xcb0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xcc0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xcd0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xce0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xcf0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd00*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd10*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd20*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd30*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd40*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd50*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0xd60*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x9e, 0xf7,  0x9e, 0xf7, 0x9e, 0xf7, 0x9e, 0xf7, 0x9e, 0xf7,
+/*0xd70*/	0x91, 0x8c, 0x91, 0x8c, 0x0f, 0x84, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xd80*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0xde, 0xff, 0xde, 0xff,
+/*0xd90*/	0xde, 0xff, 0xde, 0xff, 0xde, 0xff, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xda0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xdb0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xdc0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xdd0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xde0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xdf0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe00*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe10*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe20*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe30*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe40*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe50*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe60*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe70*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe80*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xe90*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xea0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xeb0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0xec0*/	0xde, 0xff, 0xde, 0xff, 0xde, 0xff, 0xde, 0xff,  0xde, 0xff, 0xd2, 0x9c, 0xd2, 0x9c, 0xd2, 0x9c,
+/*0xed0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0xee0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0xef0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf00*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf10*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf20*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf30*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf40*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf50*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf60*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf70*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf80*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xf90*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xfa0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xfb0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xfc0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xfd0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xfe0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0xff0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x1000*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x1010*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x1020*/	0xff, 0xff, 0xff, 0xff, 0x34, 0xa5, 0x34, 0xa5,  0x34, 0xa5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1030*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1040*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1050*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1060*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1070*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1080*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1090*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10a0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10b0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10c0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10d0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10e0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x10f0*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1100*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1110*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1120*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1130*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1140*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1150*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1160*/	0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,  0x61, 0x10, 0x61, 0x10, 0x61, 0x10, 0x61, 0x10,
+/*0x1170*/	0x61, 0x10, 0x61, 0x10, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x75, 0xad,
+/*0x1180*/	0x75, 0xad, 0x75, 0xad, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1190*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x11a0*/	0xff, 0xff, 0xff, 0xff, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x11b0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x11c0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x11d0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x11e0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x11f0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1200*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1210*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1220*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1230*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1240*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1250*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1260*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1270*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1280*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x1290*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x12a0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x12b0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x12c0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0xff, 0xff,
+/*0x12d0*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xd6, 0xbd, 0xd6, 0xbd, 0xd6, 0xbd, 0x00, 0x00,
+/*0x12e0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x12f0*/	0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xa2, 0x18,
+/*0x1300*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1310*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1320*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1330*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1340*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1350*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1360*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1370*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1380*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1390*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13a0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13b0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13c0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13d0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13e0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x13f0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1400*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1410*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x1420*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x1430*/	0xff, 0xff, 0x18, 0xc6, 0x18, 0xc6, 0x18, 0xc6,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1440*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,
+/*0x1450*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1460*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1470*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1480*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1490*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14a0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14b0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14c0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14d0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14e0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x14f0*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1500*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1510*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1520*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1530*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1540*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1550*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1560*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1570*/	0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,  0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18, 0xc2, 0x18,
+/*0x1580*/	0xc2, 0x18, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0x79, 0xce, 0x79, 0xce,
+/*0x1590*/	0x79, 0xce, 0xd7, 0xbd, 0xc7, 0x39, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x15a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x15b0*/	0xff, 0xff, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x15c0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x15d0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x15e0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x15f0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1600*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1610*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1620*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1630*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1640*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1650*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1660*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1670*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1680*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x1690*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x16a0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x16b0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x16c0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x16d0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xff, 0xff, 0xff, 0xff,
+/*0x16e0*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xba, 0xd6,  0xba, 0xd6, 0xba, 0xd6, 0x5d, 0xef, 0xba, 0xd6,
+/*0x16f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1700*/	0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1710*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1720*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1730*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1740*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1750*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1760*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1770*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1780*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1790*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17a0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17b0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17c0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17d0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17e0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x17f0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1800*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1810*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1820*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x1830*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x1840*/	0xdb, 0xde, 0xdb, 0xde, 0xdb, 0xde, 0x3c, 0xe7,  0x3c, 0xe7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1850*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
+/*0x1860*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1870*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1880*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1890*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18a0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18b0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18c0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18d0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18e0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x18f0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1900*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1910*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1920*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1930*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1940*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1950*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1960*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1970*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1980*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x1990*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x1c, 0xe7, 0x1c, 0xe7, 0x1c, 0xe7,
+/*0x19a0*/	0xdb, 0xde, 0xdb, 0xde, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x19b0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x19c0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x19d0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x19e0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x19f0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a00*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a10*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a20*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a30*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a40*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a50*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a60*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a70*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a80*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1a90*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1aa0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1ab0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1ac0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1ad0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1ae0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x1af0*/	0xff, 0xff, 0xff, 0xff, 0x7d, 0xef, 0x7d, 0xef,  0x7d, 0xef, 0x59, 0xce, 0x59, 0xce, 0x00, 0x00,
+/*0x1b00*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1b10*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b20*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b30*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b40*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b50*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b60*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b70*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b80*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1b90*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1ba0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1bb0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1bc0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1bd0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1be0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1bf0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1c00*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1c10*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1c20*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1c30*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x1c40*/	0x24, 0x29, 0x24, 0x29, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xbe, 0xf7,
+/*0x1c50*/	0xbe, 0xf7, 0xbe, 0xf7, 0x96, 0xb5, 0x96, 0xb5,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1c60*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
+/*0x1c70*/	0xff, 0xff, 0xff, 0xff, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1c80*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1c90*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1ca0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1cb0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1cc0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1cd0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1ce0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1cf0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d00*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d10*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d20*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d30*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d40*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d50*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d60*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d70*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d80*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x1d90*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0xff, 0xff,
+/*0x1da0*/	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xb2, 0x94,
+/*0x1db0*/	0xb2, 0x94, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x1dc0*/	0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,  0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x45, 0x31,
+/*0x1dd0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1de0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1df0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e00*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e10*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e20*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e30*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e40*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e50*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e60*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e70*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e80*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x1e90*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
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+/*0x3fd0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x3fe0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x3ff0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4000*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4010*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4020*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4030*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4040*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4050*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4060*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4070*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4080*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x4090*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x40a0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x40b0*/	0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,  0x45, 0x31, 0x45, 0x31, 0x45, 0x31, 0x45, 0x31,
+/*0x40c0*/	0x45, 0x31, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,  0xcf, 0x73, 0xcf, 0x73, 0x9a, 0xd6, 0x9a, 0xd6,
+/*0x40d0*/	0x9a, 0xd6, 0xfb, 0xde, 0xfb, 0xde, 0xb2, 0x94,  0x34, 0xa5, 0x34, 0xa5, 0x34, 0xa5, 0x34, 0xa5,
+/*0x40e0*/	0x34, 0xa5, 0x34, 0xa5, 0xb2, 0x94, 0x65, 0x29,  0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,
+/*0x40f0*/	0xcf, 0x73, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4100*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4110*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4120*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4130*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4140*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4150*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4160*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4170*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4180*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4190*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41a0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41b0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41c0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41d0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41e0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x41f0*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4200*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,
+/*0x4210*/	0x45, 0x29, 0x45, 0x29, 0x45, 0x29, 0x45, 0x29,  0x45, 0x29, 0x45, 0x29, 0xcf, 0x73, 0xcf, 0x73,
+/*0x4220*/	0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0xdb, 0xde,  0xdb, 0xde, 0xdb, 0xde, 0xfb, 0xde, 0xfb, 0xde,
+/*0x4230*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4240*/	0x00, 0x00, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,  0xcf, 0x73, 0xcf, 0x73, 0x44, 0x29, 0x44, 0x29,
+/*0x4250*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4260*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4270*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4280*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4290*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42a0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42b0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42c0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42d0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42e0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x42f0*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4300*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4310*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4320*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4330*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4340*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4350*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4360*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,  0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0x44, 0x29,
+/*0x4370*/	0x44, 0x29, 0x44, 0x29, 0x44, 0x29, 0xcf, 0x73,  0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,
+/*0x4380*/	0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde,  0xfb, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4390*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0xcf, 0x73, 0xcf, 0x73,
+/*0x43a0*/	0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x43b0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x43c0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x43d0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x43e0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x43f0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4400*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4410*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4420*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4430*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4440*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4450*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4460*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4470*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4480*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4490*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x44a0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x44b0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x44c0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x44d0*/	0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,  0xcf, 0x73, 0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde,
+/*0x44e0*/	0x1c, 0xe7, 0x1c, 0xe7, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x44f0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcf, 0x73,  0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,
+/*0x4500*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4510*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4520*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4530*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4540*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4550*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4560*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4570*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4580*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4590*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45a0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45b0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45c0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45d0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45e0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x45f0*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4600*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4610*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,
+/*0x4620*/	0x24, 0x29, 0x24, 0x29, 0x24, 0x29, 0x24, 0x29,  0x24, 0x29, 0xcf, 0x73, 0xcf, 0x73, 0xcf, 0x73,
+/*0x4630*/	0xcf, 0x73, 0xcf, 0x73, 0xfb, 0xde, 0xfb, 0xde,  0xfb, 0xde, 0x1c, 0xe7, 0x1c, 0xe7, 0x00, 0x00,
+/*0x4640*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4650*/	0xef, 0x7b, 0xef, 0x7b, 0xef, 0x7b, 0xef, 0x7b,  0xef, 0x7b, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4660*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4670*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4680*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4690*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46a0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46b0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46c0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46d0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46e0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x46f0*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4700*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4710*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4720*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4730*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4740*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4750*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4760*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4770*/	0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,  0x04, 0x21, 0x04, 0x21, 0x04, 0x21, 0x04, 0x21,
+/*0x4780*/	0x04, 0x21, 0x04, 0x21, 0xef, 0x7b, 0xef, 0x7b,  0xef, 0x7b, 0xef, 0x7b, 0xef, 0x7b, 0xfb, 0xde,
+/*0x4790*/	0xfb, 0xde, 0xfb, 0xde, 0x3c, 0xe7, 0x3c, 0xe7,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x47a0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x0f, 0x7c, 0x0f, 0x7c, 0x0f, 0x7c,
+/*0x47b0*/	0x0f, 0x7c, 0x0f, 0x7c, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x47c0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x47d0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x47e0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x47f0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4800*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4810*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4820*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4830*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4840*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4850*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4860*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4870*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4880*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x4890*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x48a0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x48b0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x48c0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,
+/*0x48d0*/	0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x03, 0x21,  0x03, 0x21, 0x03, 0x21, 0x03, 0x21, 0x0f, 0x7c,
+/*0x48e0*/	0x0f, 0x7c, 0x0f, 0x7c, 0x0f, 0x7c, 0x0f, 0x7c,  0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde, 0x5d, 0xef,
+/*0x48f0*/	0x5d, 0xef, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4900*/	0x00, 0x00, 0x00, 0x00, 0x10, 0x7c, 0x10, 0x7c,  0x10, 0x7c, 0x10, 0x7c, 0x10, 0x7c, 0xe3, 0x20,
+/*0x4910*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4920*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4930*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4940*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4950*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4960*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4970*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4980*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4990*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49a0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49b0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49c0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49d0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49e0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x49f0*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4a00*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4a10*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4a20*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,
+/*0x4a30*/	0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20, 0xe3, 0x20,  0x10, 0x7c, 0x10, 0x7c, 0x10, 0x7c, 0x10, 0x7c,
+/*0x4a40*/	0x10, 0x7c, 0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde,  0x5d, 0xef, 0x5d, 0xef, 0x00, 0x00, 0x00, 0x00,
+/*0x4a50*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x84,
+/*0x4a60*/	0x30, 0x84, 0x30, 0x84, 0x30, 0x84, 0x30, 0x84,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4a70*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4a80*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4a90*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4aa0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4ab0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4ac0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4ad0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4ae0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4af0*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b00*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b10*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b20*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b30*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b40*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b50*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b60*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b70*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b80*/	0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,  0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18, 0xe3, 0x18,
+/*0x4b90*/	0xe3, 0x18, 0x30, 0x84, 0x30, 0x84, 0x30, 0x84,  0x30, 0x84, 0x30, 0x84, 0xfb, 0xde, 0xfb, 0xde,
+/*0x4ba0*/	0xfb, 0xde, 0x5d, 0xef, 0x5d, 0xef, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4bb0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x51, 0x8c, 0x51, 0x8c, 0x51, 0x8c, 0x51, 0x8c,
+/*0x4bc0*/	0x51, 0x8c, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4bd0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4be0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4bf0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c00*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c10*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c20*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c30*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c40*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c50*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c60*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c70*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c80*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4c90*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4ca0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4cb0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4cc0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4cd0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,
+/*0x4ce0*/	0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18, 0xc3, 0x18,  0xc3, 0x18, 0xc3, 0x18, 0x51, 0x8c, 0x51, 0x8c,
+/*0x4cf0*/	0x51, 0x8c, 0x51, 0x8c, 0x51, 0x8c, 0xfb, 0xde,  0xfb, 0xde, 0xfb, 0xde, 0x5d, 0xef, 0x9a, 0xd6,
+/*0x4d00*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4d10*/	0x00, 0x00, 0x91, 0x8c, 0x91, 0x8c, 0x91, 0x8c,  0x91, 0x8c, 0x91, 0x8c, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d20*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d30*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d40*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d50*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d60*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d70*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d80*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4d90*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4da0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4db0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4dc0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4dd0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4de0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4df0*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4e00*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4e10*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4e20*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4e30*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,  0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18,
+/*0x4e40*/	0xa2, 0x18, 0xa2, 0x18, 0xa2, 0x18, 0x91, 0x8c,  0x91, 0x8c, 0x91, 0x8c, 0x91, 0x8c, 0x91, 0x8c,
+/*0x4e50*/	0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde, 0xba, 0xd6,  0x08, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4e60*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0xb2, 0x94, 0xb2, 0x94,
+/*0x4e70*/	0xb2, 0x94, 0xb2, 0x94, 0xb2, 0x94, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4e80*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4e90*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4ea0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4eb0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4ec0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4ed0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4ee0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4ef0*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f00*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f10*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f20*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f30*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f40*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f50*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f60*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f70*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f80*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4f90*/	0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,  0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10, 0xa2, 0x10,
+/*0x4fa0*/	0xb2, 0x94, 0xb2, 0x94, 0xb2, 0x94, 0xb2, 0x94,  0xb2, 0x94, 0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde,
+/*0x4fb0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x4fc0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xd3, 0x94,  0xd3, 0x94, 0xd3, 0x94, 0xd3, 0x94, 0xd3, 0x94,
+/*0x4fd0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x4fe0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x4ff0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5000*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5010*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5020*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5030*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5040*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5050*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5060*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5070*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5080*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x5090*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50a0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50b0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50c0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50d0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50e0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,
+/*0x50f0*/	0x82, 0x10, 0x82, 0x10, 0x82, 0x10, 0x82, 0x10,  0x82, 0x10, 0xd3, 0x94, 0xd3, 0x94, 0xd3, 0x94,
+/*0x5100*/	0xd3, 0x94, 0xd3, 0x94, 0xfb, 0xde, 0xfb, 0xde,  0xfb, 0xde, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5110*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5120*/	0xf3, 0x9c, 0xf3, 0x9c, 0xf3, 0x9c, 0xf3, 0x9c,  0xf3, 0x9c, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5130*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5140*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5150*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5160*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5170*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5180*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5190*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51a0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51b0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51c0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51d0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51e0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x51f0*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5200*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5210*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5220*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5230*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5240*/	0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,  0x81, 0x10, 0x81, 0x10, 0x81, 0x10, 0x81, 0x10,
+/*0x5250*/	0x81, 0x10, 0x81, 0x10, 0xf3, 0x9c, 0xf3, 0x9c,  0xf3, 0x9c, 0xf3, 0x9c, 0xf3, 0x9c, 0xfb, 0xde,
+/*0x5260*/	0xfb, 0xde, 0xfb, 0xde, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5270*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x14, 0xa5, 0x14, 0xa5, 0x14, 0xa5,
+/*0x5280*/	0x14, 0xa5, 0x14, 0xa5, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5290*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52a0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52b0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52c0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52d0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52e0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x52f0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5300*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5310*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5320*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5330*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5340*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5350*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5360*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5370*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5380*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x5390*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,
+/*0x53a0*/	0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x61, 0x08,  0x61, 0x08, 0x61, 0x08, 0x61, 0x08, 0x14, 0xa5,
+/*0x53b0*/	0x14, 0xa5, 0x14, 0xa5, 0x14, 0xa5, 0x14, 0xa5,  0xfb, 0xde, 0xfb, 0xde, 0xfb, 0xde, 0x00, 0x00,
+/*0x53c0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x53d0*/	0x00, 0x00, 0x00, 0x00, 0x34, 0xa5, 0x34, 0xa5,  0x34, 0xa5, 0x34, 0xa5, 0x34, 0xa5, 0x41, 0x08,
+/*0x53e0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x53f0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5400*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5410*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5420*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5430*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5440*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5450*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5460*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5470*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5480*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5490*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54a0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54b0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54c0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54d0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54e0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x54f0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5500*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x34, 0xa5, 0x34, 0xa5, 0x34, 0xa5, 0x34, 0xa5,
+/*0x5510*/	0x34, 0xa5, 0xfb, 0xde, 0xfb, 0xde, 0x38, 0xc6,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5520*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x55, 0xad,
+/*0x5530*/	0x55, 0xad, 0x55, 0xad, 0x55, 0xad, 0x55, 0xad,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5540*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5550*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5560*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5570*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5580*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5590*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55a0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55b0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55c0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55d0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55e0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x55f0*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5600*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5610*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5620*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5630*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5640*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5650*/	0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,  0x41, 0x08, 0x41, 0x08, 0x41, 0x08, 0x41, 0x08,
+/*0x5660*/	0x41, 0x08, 0x55, 0xad, 0x55, 0xad, 0x55, 0xad,  0x55, 0xad, 0x55, 0xad, 0xfb, 0xde, 0x38, 0xc6,
+/*0x5670*/	0xe7, 0x39, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5680*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x55, 0xad, 0x55, 0xad, 0x55, 0xad, 0x55, 0xad,
+/*0x5690*/	0x55, 0xad, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56a0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56b0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56c0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56d0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56e0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x56f0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5700*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5710*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5720*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5730*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5740*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5750*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5760*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5770*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5780*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x5790*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x57a0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,
+/*0x57b0*/	0x20, 0x08, 0x20, 0x08, 0x20, 0x08, 0x20, 0x08,  0x20, 0x08, 0x20, 0x08, 0x55, 0xad, 0x55, 0xad,
+/*0x57c0*/	0x55, 0xad, 0x55, 0xad, 0x55, 0xad, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x57d0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x57e0*/	0x00, 0x00, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0xa2, 0x10, 0x20, 0x00,
+/*0x57f0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5800*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5810*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5820*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5830*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5840*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5850*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5860*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5870*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5880*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5890*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58a0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58b0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58c0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58d0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58e0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x58f0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5900*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5910*/	0x20, 0x00, 0x20, 0x00, 0xa2, 0x10, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5920*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5930*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x75, 0xad, 0x75, 0xad,
+/*0x5940*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x8a, 0x52,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5950*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5960*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5970*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5980*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5990*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59a0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59b0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59c0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59d0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59e0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x59f0*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a00*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a10*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a20*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a30*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a40*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a50*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,
+/*0x5a60*/	0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x20, 0x00,  0x20, 0x00, 0x20, 0x00, 0x20, 0x00, 0x8a, 0x52,
+/*0x5a70*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5a80*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5a90*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5aa0*/	0x55, 0xad, 0x69, 0x4a, 0x82, 0x10, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ab0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ac0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ad0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ae0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5af0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b00*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b10*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b20*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b30*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b40*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b50*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b60*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b70*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b80*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5b90*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ba0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5bb0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5bc0*/	0x00, 0x00, 0x00, 0x00, 0x82, 0x10, 0x69, 0x4a,  0x55, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5bd0*/	0x75, 0xad, 0x75, 0xad, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5be0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5bf0*/	0xf3, 0x9c, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c00*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c10*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c20*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c30*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c40*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c50*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c60*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c70*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c80*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5c90*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ca0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5cb0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5cc0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5cd0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ce0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5cf0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d00*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d10*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d20*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0xf3, 0x9c, 0x00, 0x00,
+/*0x5d30*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5d40*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x0c, 0x63, 0x75, 0xad, 0x75, 0xad,
+/*0x5d50*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d60*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d70*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d80*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5d90*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5da0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5db0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5dc0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5dd0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5de0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5df0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e00*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e10*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e20*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e30*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e40*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e50*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e60*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e70*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5e80*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0xeb, 0x5a,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5e90*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ea0*/	0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x0c, 0x63,  0xd3, 0x9c, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5eb0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ec0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ed0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ee0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5ef0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f00*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f10*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f20*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f30*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f40*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f50*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f60*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f70*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f80*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5f90*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5fa0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5fb0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5fc0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,
+/*0x5fd0*/	0x75, 0xad, 0x75, 0xad, 0x75, 0xad, 0x75, 0xad,  0x75, 0xad, 0x75, 0xad, 0xd3, 0x9c, 0xcb, 0x5a,
+/*0x5fe0*/	0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+/*0x5ff0*/	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,  0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+};
+
+// End of File
diff --git a/drivers/power/charge.c b/drivers/power/charge.c
new file mode 100644
index 0000000000..1a4a93f14a
--- /dev/null
+++ b/drivers/power/charge.c
@@ -0,0 +1,430 @@
+/*
+ * (C) Copyright 2000
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+#include <common.h>
+#include "max17042_battery.h"
+#include "battery00.h"
+#include "green_left.h"
+#include "green_mid.h"
+#include "green_right.h"
+
+#define REBOOT_CMD_REG		0xd4010018
+#define REBOOT_CMD_REBOOT	0x01
+#define REBOOT_CMD_PWROFF	0x02
+
+#define ANIMATION_THRESHOLD	3
+#define ANDROID_THRESHOLD	15
+#define CHG_CURRENT_THRESHOLD	(-30000)
+#define CHARGE_CYCLE_US		1000000
+#define LCD_TIMEOUT_CYCLE	7
+#define FORCED_BOOTUP_CYCLE	3
+
+#define GPIO86 86
+
+#ifdef CONFIG_PXA27X_KEYPAD
+static enum key{
+	HOME,
+	MENU,
+	BACK,
+	VOL_DOWN,
+	VOL_UP,
+	DOWN_UP,
+	NONE,
+};
+extern inline enum key pxa27x_key_read(void);
+#endif
+
+static int read_battery_capacity(void)
+{
+	if (board_is_mmp2_brownstone_rev5()) {
+#ifdef CONFIG_MAX17042_BATTERY
+		return max17042_get_capacity();
+#else
+		return 0;
+#endif
+	} else
+	{
+		return 0;
+	}
+}
+
+static inline int battery_is_charging(void)
+{
+	int n = 0;
+	int chg = 0;
+
+#ifdef CONFIG_MAX17042_BATTERY
+	/* judge whether current is smaller than CHG_CURRENT_THRESHOLD
+	   for 5 times sampling */
+	while (n < 5) {
+		if (max17042_get_current() > CHG_CURRENT_THRESHOLD) {
+			if (chg == 0) {
+				n = 0;
+				chg = 1;
+			} else {
+				udelay(10000);
+				n++;
+			}
+		} else {
+			if (chg == 1) {
+				n = 0;
+				chg = 0;
+			} else {
+				udelay(10000);
+				n++;
+			}
+		}
+	}
+	return chg;
+#else
+	return 0;
+#endif
+}
+
+static inline int onkey_is_pressed(void)
+{
+	u8 data, t;
+	int status;
+
+	if (machine_is_brownstone()) {
+		i2c_set_bus_num(0);
+		int res = i2c_read(0x3c, 0x03, 1, &data, 1);
+
+		if (data & 0x80)
+			return 1;
+		else
+			return 0;
+	}
+}
+
+static inline int check_dc_irq(void)
+{
+	u8 data, t;
+	int status;
+
+	if (machine_is_brownstone()) {
+		i2c_set_bus_num(0);
+		int res = i2c_read(0x3c, 0x7e, 1, &data, 1);
+
+		if (data & 0x04)
+			return 1;
+		else
+			return 0;
+	}
+}
+
+extern void show_charge_logo(unsigned char *logo, int wide, int high, int offset);
+
+void show_capacity(int capacity)
+{
+	int i = 0, round = 1;
+
+	if (capacity >= 0 && capacity < 20) {
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+		}
+	} else if (capacity >= 20 && capacity < 40) {
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 76);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+		}
+	} else if (capacity >= 40 && capacity < 60) {
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 76);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 14);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			}
+	} else if (capacity >= 60 && capacity < 80) {
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 76);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 14);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, -48);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+		}
+	} else if (capacity >= 80 && capacity < 100) {
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 76);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 14);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, -48);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+			show_charge_logo(RES_green_right_BIN, 25, 65, -110);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+		}
+
+	} else if (capacity >= 100){
+		for(i = 0; i < round; i++) {
+			show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+			show_charge_logo(RES_green_left_BIN, 25, 65, 138);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 76);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, 14);
+			show_charge_logo(RES_green_mid_BIN, 27, 65, -48);
+			show_charge_logo(RES_green_right_BIN, 25, 65, -110);
+			udelay(CHARGE_CYCLE_US);
+			udelay(CHARGE_CYCLE_US);
+		}
+	}
+}
+
+extern void *lcd_init(void);
+extern void lcd_flush(void);
+extern void *close_lcd(void);
+void show_lcd_animation(int charge_state)
+{
+	static int n_cycles = 0;
+
+	if (charge_state == 1) {
+		/* need to show lcd annimation here */
+		if (n_cycles == 0) {
+			/* open lcd and display */
+			lcd_init();
+			udelay(CHARGE_CYCLE_US);
+		}
+		n_cycles = LCD_TIMEOUT_CYCLE;
+	} else {
+		/* need to close lcd to save power */
+		if (n_cycles == 1) {
+			/* close lcd */
+			close_lcd();
+		}
+		/* keep lcd on/off and do nothing */
+		if (n_cycles != 0) {
+			n_cycles--;
+			show_capacity(read_battery_capacity());
+		}
+	}
+}
+
+static int do_charge_cycle(void)
+{
+	int t;
+	int charge_state = 0;	/* 0: normal; 1: show lcd animation; 2: force system to boot up */
+				/* 3: force system to boot up unconditionally */
+	unsigned char chg_data[2], data[2];
+
+#ifdef CONFIG_MAX17042_BATTERY
+	printf("%s: VOL:%duV CUR:%duA CAP:%d%", __func__, \
+		max17042_get_voltage(), max17042_get_current(), max17042_get_capacity());
+	/* align and clear charge info */
+	printf("                \r");
+#endif
+	/* write charger reg */
+	if (board_is_mmp2_brownstone_rev5()) {
+		chg_data[0] = 0x00;
+		chg_data[1] = 0x08;
+		i2c_set_bus_num(0);
+		int res = i2c_write(0x09, 0x14, 1, chg_data, 2);
+	}
+
+	if (onkey_is_pressed()) {
+		for (t = 0; t < FORCED_BOOTUP_CYCLE; t++) {
+			udelay(CHARGE_CYCLE_US);
+			if (!onkey_is_pressed())
+				break;
+		}
+		if (t == FORCED_BOOTUP_CYCLE)
+			charge_state = 2;
+		else
+			charge_state = 1;
+	}
+#ifdef CONFIG_PXA27X_KEYPAD
+	if (pxa27x_key_read() == DOWN_UP) {
+		for (t = 0; t < FORCED_BOOTUP_CYCLE; t++) {
+			udelay(CHARGE_CYCLE_US);
+			if (pxa27x_key_read() != DOWN_UP)
+				break;
+		}
+		if (t == FORCED_BOOTUP_CYCLE);
+			charge_state = 3;
+	}
+#endif
+	if (!charge_state)
+		udelay(CHARGE_CYCLE_US);
+
+	return charge_state;
+}
+
+static void led_enable(int en)
+{
+	unsigned int gpio;
+
+	if (board_is_mmp2_brownstone_rev5()) {
+		gpio_direction_output(GPIO86, !en);
+	}
+	return ;
+}
+
+void charge_reset(void)
+{
+	int n = 0;
+	unsigned char chg_data[2];
+
+#ifdef CONFIG_MAX17042_BATTERY
+	/* abnormal case: current is always zero*/
+	while (n < 10) {
+		if (max17042_get_current() == 0) {
+			n++;
+			udelay(10000);
+			continue;
+		} else
+			break;
+	}
+	if (n == 10) {
+		/* charger needs to be reset here */
+		printf("fuel-gauge reseting...");
+		max17042_reset();
+		printf("done\n");
+	}
+#else
+	return;
+#endif
+}
+
+void charge_detect(void)
+{
+	int cap, i;
+	int chg_to_full = 1;	/* 0: try to boot up if threshold met; 1: charge until full capacity */
+	int charge_state = 1;	/* 0: normal; 1: show lcd animation; 2: force system to boot up */
+				/* 3: force system to boot up unconditionally */
+	unsigned char chg_data[2], data[2];
+
+	/* stop charger first */
+	if (board_is_mmp2_brownstone_rev5()) {
+		chg_data[0] = 0x00;
+		chg_data[1] = 0x00;
+		i2c_set_bus_num(0);
+		int res = i2c_write(0x09, 0x14, 1, chg_data, 2);
+
+		/* wait for charger stopped totally */
+		udelay(100000);
+	}
+
+	/* return to normal flow if no battery */
+	if (read_battery_capacity() < 0) {
+		printf("No battery on board.\n");
+		return ;
+	}
+
+	charge_reset();
+
+	/* in such case, uboot will try to boot up android */
+	/* 1) DC is in; 2) no DC plugging irq 3) not triggered by power off cmd */
+	/* due to reset button pressed */
+	if (battery_is_charging() && !check_dc_irq() && \
+	    *(volatile unsigned int *)REBOOT_CMD_REG != REBOOT_CMD_PWROFF)
+		chg_to_full = 0;
+
+	/* try to boot up kernel
+	   if it is triggered by reboot cmd in last power cycle */
+	if (*(volatile unsigned int *)REBOOT_CMD_REG == REBOOT_CMD_REBOOT)
+		chg_to_full = 0;
+
+	*(volatile unsigned int *)REBOOT_CMD_REG = 0;
+
+	if (!battery_is_charging()) {
+		chg_to_full = 0;
+		cap = read_battery_capacity();
+		if (cap >= ANDROID_THRESHOLD) {
+			/* return to normal flow if battery is not in charging
+			   and with enough capacity */
+			return;
+		} else {
+			/* show some notice and wait, or shut down system directly here */
+			printf("Low battery! DC is needed.\n");
+			lcd_init();
+			for (i = 0; i < 20; i++) {
+				if (battery_is_charging())
+					break;
+				show_charge_logo(RES_battery00_BIN, 173, 71, 0);
+				udelay(CHARGE_CYCLE_US);
+			}
+		}
+	}
+
+	/* get here if battery is in charge */
+	printf("Battery is in charging...\n");
+	led_enable(1);
+
+	while(1) {
+		cap = read_battery_capacity();
+		if (cap < 0)
+			break;
+
+		if (((charge_state == 2 || chg_to_full == 0) && cap >= ANDROID_THRESHOLD) || \
+			charge_state == 3) {
+			lcd_flush();
+			break;
+		}
+		if (!battery_is_charging()) {
+			/* shut down system */
+			max8925_power_off();
+		} else if (cap < ANIMATION_THRESHOLD) {
+			close_lcd();
+			charge_state = do_charge_cycle();
+			continue;
+		} else if (cap < ANDROID_THRESHOLD) {
+			show_lcd_animation(charge_state);
+			charge_state = do_charge_cycle();
+			continue;
+		} else if (chg_to_full) {
+			/* continue charging since bootup reason is DC pulugged in */
+			show_lcd_animation(charge_state);
+			charge_state = do_charge_cycle();
+			continue;
+		} else {
+			break;
+		}
+	}
+	/* return to normal flow with enough battery capacity */
+	led_enable(0);
+
+	/* stop charger */
+	if (board_is_mmp2_brownstone_rev5()) {
+		chg_data[0] = 0x00;
+		chg_data[1] = 0x00;
+		i2c_set_bus_num(0);
+		int res = i2c_write(0x09, 0x14, 1, chg_data, 2);
+	}
+
+	return;
+}
diff --git a/drivers/power/ddr.h b/drivers/power/ddr.h
new file mode 100644
index 0000000000..37e2977aac
--- /dev/null
+++ b/drivers/power/ddr.h
@@ -0,0 +1,162 @@
+#ifndef DDR_H_
+#define DDR_H_
+
+#define	MCU_CPU_ID_REV		0x0000
+#define	DRAM_STATUS		0x0008
+#define	MEMORY_ADDRESS_MAP0			0x0010
+#define	MEMORY_ADDRESS_MAP1			0x0014
+#define	SDRAM_CONFIG0_TYPE1			0x0020
+#define	SDRAM_CONFIG1_TYPE1			0x0024
+#define	SDRAM_CONFIG0_TYPE2			0x0030
+#define	SDRAM_CONFIG1_TYPE2			0x0034
+#define	SDRAM_CTRL1				0x0050
+#define	SDRAM_CTRL2				0x0054
+#define	SDRAM_CTRL4				0x0058
+#define	SDRAM_CTRL6				0x005c
+#define	SDRAM_CTRL7				0x0060
+#define	SDRAM_CTRL13				0x0064
+#define	SDRAM_CTRL14				0x0068
+
+#define	SDRAM_TIMING1				0x0080
+#define	SDRAM_TIMING2				0x0084
+#define	SDRAM_TIMING3				0x0088
+#define	SDRAM_TIMING4				0x008C
+#define	SDRAM_TIMING5				0x0090
+#define	SDRAM_TIMING6				0x0094
+#define	SDRAM_TIMING7				0x0098
+#define	SDRAM_TIMING8				0x009c
+
+#define	EXCLUSIVE_MONITOR_CTRL		0x0100
+#define	TRUSTZONE_SEL				0x0120
+#define	TRUSTZONE_RANGE0			0x0124
+#define	TRUSTZONE_RANGE1			0x0128
+#define	TRUSTZONE_PERMISSION		0x012C
+#define	PORT_PRIORITY				0x0140
+#define	SRAM_CTRL1					0x0144
+#define	SRAM_CTRL2					0x0148
+#define	SRAM_CTRL3					0x014C
+#define	USER_INITIATED_COMMAND0		0x0160
+#define	USER_INITIATED_COMMAND1		0x0164
+#define	MODE_RD_DATA				0x0170
+#define	SMR1						0x0180
+#define	SMR2						0x0184
+#define	REGISTER_TABLE_CTRL_0		0x01C0
+#define	REGISTER_TABLE_DATA_0		0x01C8
+#define	REGISTER_TABLE_DATA_1		0x01CC
+#define	PHY_CTRL3					0x0220
+#define	PHY_CTRL7					0x0230
+#define	PHY_CTRL8					0x0234
+#define	PHY_CTRL9					0x0238
+#define	PHY_CTRL10					0x023C
+#define	PHY_CTRL11					0x0240
+#define	PHY_CTRL13					0x0248
+#define	PHY_CTRL14					0x024C
+#define	PHY_CTRL15					0x0250
+#define	PHY_CTRL16					0x0254
+#define	PHY_CTRL21					0x0258
+#define	PHY_CTRL19					0x0280
+#define	PHY_CTRL20					0x0284
+#define	PHY_CTRL22					0x0288
+#define	PHY_DQ_BYTE_SEL				0x0300
+#define	PHY_DLL_CTRL1				0x0304
+#define	PHY_DQ_BYTE_CTRL			0x0308
+#define	PHY_DLL_WL_SEL				0x0380
+#define	PHY_DLL_WL_CTRL0			0x0384
+#define	PHY_DLL_WL_CTRL1			0x0388
+#define	PHY_DLL_WL_CTRL2			0x038C
+#define	PHY_DLL_RL_CTRL				0x0390
+#define	PHY_CTRL_TESTMODE			0x0400
+#define	TEST_MODE0					0x0410
+#define	TEST_MODE1					0x0414
+#define	PERFORMANCE_COUNTER_CTRL_0	0x0440
+#define	PERFORMANCE_COUNTER_STATUS	0x0444
+#define	PERFORMANCE_COUNTER_SELECT	0x0448
+#define	PERFORMANCE_COUNTER0		0x0450
+#define	PERFORMANCE_COUNTER1		0x0454
+#define	PERFORMANCE_COUNTER2		0x0458
+#define	PERFORMANCE_COUNTER3		0x045C
+
+#define PHY_CNTRL_REG3			0x220
+
+/*#define DDR3_SDRAM_TIMING_REG1_400	0x911403CF
+#define DDR3_SDRAM_TIMING_REG2_400	0x64660404
+#define DDR3_SDRAM_TIMING_REG3_400	0xC2004453
+#define DDR3_SDRAM_TIMING_REG4_400	0x34F8A187
+#define DDR3_SDRAM_TIMING_REG5_400	0x000F2121
+#define DDR3_SDRAM_TIMING_REG6_400	0x00404200
+#define DDR3_SDRAM_TIMING_REG7_400	0x00005501
+#define DDR3_PHY_CNTRL_REG3_400		0x20004044*/
+
+#define DDR3_SDRAM_TIMING_REG1_400	0x911b00cb
+#define DDR3_SDRAM_TIMING_REG2_400	0x748803b4
+#define DDR3_SDRAM_TIMING_REG3_400	0xC208406c
+#define DDR3_SDRAM_TIMING_REG4_400	0x4698da09
+#define DDR3_SDRAM_TIMING_REG5_400	0x00140181
+#define DDR3_SDRAM_TIMING_REG6_400	0x00404200
+#define DDR3_SDRAM_TIMING_REG7_400	0x00005501
+#define DDR3_PHY_CNTRL_REG3_400		0x20004044
+
+#define LPDDR2_SDRAM_TIMING_REG1_400	0x4CDA00C5
+#define LPDDR2_SDRAM_TIMING_REG2_400	0x94860342
+#define LPDDR2_SDRAM_TIMING_REG3_400	0x2000381B
+#define LPDDR2_SDRAM_TIMING_REG4_400	0x3023009D
+#define LPDDR2_SDRAM_TIMING_REG5_400	0x20110142
+#define LPDDR2_SDRAM_TIMING_REG6_400	0x02424190
+#define LPDDR2_SDRAM_TIMING_REG7_400	0x00005501
+#define LPDDR2_PHY_CNTRL_REG3_400	0x20004444
+
+#define LPDDR2_SDRAM_TIMING_REG1_200	0x4CDA00C5
+#define LPDDR2_SDRAM_TIMING_REG2_200	0x94860342
+#define LPDDR2_SDRAM_TIMING_REG3_200	0x2000381B
+#define LPDDR2_SDRAM_TIMING_REG4_200	0x3023009D
+#define LPDDR2_SDRAM_TIMING_REG5_200	0x20110142
+#define LPDDR2_SDRAM_TIMING_REG6_200	0x02424190
+#define LPDDR2_SDRAM_TIMING_REG7_200	0x00005501
+#define LPDDR2_PHY_CNTRL_REG3_200	0x20004444
+
+#define DDR3_SDRAM_TIMING_REG1_533	0x911B03CF
+#define DDR3_SDRAM_TIMING_REG2_533	0x74780564
+#define DDR3_SDRAM_TIMING_REG3_533	0xC2005B6C
+#define DDR3_SDRAM_TIMING_REG4_533	0x3698DA09
+#define DDR3_SDRAM_TIMING_REG5_533	0x00142181
+#define DDR3_SDRAM_TIMING_REG6_533	0x04040200
+#define DDR3_SDRAM_TIMING_REG7_533	0x00006601
+#define DDR3_PHY_CNTRL_REG3_533		0x20004044
+
+#define LPDDR2_SDRAM_TIMING_REG1_533	0x911B03CF
+#define LPDDR2_SDRAM_TIMING_REG2_533	0x74780564
+#define LPDDR2_SDRAM_TIMING_REG3_533	0xC2005B6C
+#define LPDDR2_SDRAM_TIMING_REG4_533	0x3698DA09
+#define LPDDR2_SDRAM_TIMING_REG5_533	0x00142181
+#define LPDDR2_SDRAM_TIMING_REG7_533	0x00006601
+#define LPDDR2_PHY_CNTRL_REG3_533	0x20004444
+
+#define SDRAM_TIMING_REG1_667	0x99A103CF
+#define SDRAM_TIMING_REG2_667	0x969B06B4
+#define SDRAM_TIMING_REG3_667	0xC200728D
+#define SDRAM_TIMING_REG4_667	0x48390E8C
+#define SDRAM_TIMING_REG5_667	0x001921F1
+#define SDRAM_TIMING_REG7_667	0x00007701
+#define PHY_CNTRL_REG3_667	0x20004055
+
+#define DDR_400	400
+#define DDR3		0x00000008
+#define LPDDR2		0x00000014
+
+struct ddr_timing {
+	u32 reg1;
+	u32 reg2;
+	u32 reg3;
+	u32 reg4;
+	u32 reg5;
+	u32 reg6;
+	u32 reg7;
+	u32 reg8;
+};
+
+struct platform_ddr_setting {
+	u32 ddr_freq;
+	struct ddr_timing setting;
+};
+
+#endif /*DDR_H_*/
diff --git a/drivers/power/green_left.h b/drivers/power/green_left.h
new file mode 100644
index 0000000000..47def46f39
--- /dev/null
+++ b/drivers/power/green_left.h
@@ -0,0 +1,213 @@
+// Generate By BMP to RAW Conveter, By Leajian
+
+const unsigned char RES_green_left_BIN[] = {
+	/* Source File: C:\Documents and Settings\zhaoy\Desktop\tupian\3\3\green_left.bin */
+	/* File Size: 3258 Bytes */
+
+/*0x00*/	                                                 0xb5, 0xb5, 0xcb, 0x63, 0x62, 0x22, 0x00, 0x12,
+/*0x10*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x20*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x30*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0xeb, 0x63, 0x00, 0x12, 0x00, 0x12,
+/*0x40*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x50*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x62, 0x22, 0x00, 0x12,
+/*0x70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xa0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xb0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0xe0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0xf0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x00, 0x12,
+/*0x100*/	0x00, 0x12, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x110*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x120*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x130*/	0x20, 0x1a, 0x20, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x140*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x150*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x160*/	0xa1, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x170*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x180*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x190*/	0xc2, 0x22, 0xc2, 0x22, 0x81, 0x22, 0x81, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1a0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1b0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1c0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xc1, 0x2a,  0xc1, 0x2a, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x1d0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x1e0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x1f0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0xe2, 0x32, 0xe2, 0x32, 0x43, 0x2b, 0x43, 0x2b,
+/*0x200*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x210*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x220*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x22, 0x3b, 0x22, 0x3b, 0x63, 0x33,
+/*0x230*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x240*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x250*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x43, 0x63, 0x43,
+/*0x260*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x270*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x280*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x4b,
+/*0x290*/	0xa3, 0x4b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2a0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2b0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2c0*/	0xe4, 0x53, 0xe4, 0x53, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2d0*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2e0*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2f0*/	0x04, 0x44, 0x44, 0x5c, 0x44, 0x5c, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x300*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x310*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x320*/	0x45, 0x44, 0x45, 0x44, 0x85, 0x64, 0x85, 0x64,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x330*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x340*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x350*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0xc6, 0x74,  0xc6, 0x74, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x360*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x370*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x380*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0x06, 0x7d, 0x06, 0x7d, 0x06, 0x55, 0x06, 0x55,
+/*0x390*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3a0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3b0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x67, 0x85, 0x67, 0x85, 0x46, 0x5d,
+/*0x3c0*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x3d0*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x3e0*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0xa7, 0x8d, 0xa7, 0x8d,
+/*0x3f0*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x400*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x410*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0xe8, 0x95,
+/*0x420*/	0xe8, 0x95, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x430*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x440*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x450*/	0x28, 0xa6, 0x28, 0xa6, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x460*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x470*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x480*/	0xe8, 0x6d, 0x69, 0xae, 0x69, 0xae, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x490*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x4a0*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x4b0*/	0x28, 0x6e, 0x28, 0x6e, 0xa9, 0xb6, 0xa9, 0xb6,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x4c0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x4d0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x4e0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0xea, 0xbe,  0xea, 0xbe, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x4f0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x500*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x510*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x2a, 0xc7, 0x2a, 0xc7, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x520*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x530*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x540*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0x4b, 0xc7, 0x4b, 0xc7, 0xca, 0x7e,
+/*0x550*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x560*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x570*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0x8b, 0xcf, 0x8b, 0xcf,
+/*0x580*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x590*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x5a0*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xab, 0xd7,
+/*0x5b0*/	0xab, 0xd7, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5c0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5d0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5e0*/	0xcc, 0xd7, 0xcc, 0xd7, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x5f0*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x600*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x610*/	0x2a, 0x87, 0xec, 0xdf, 0xec, 0xdf, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x620*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x630*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x640*/	0x2a, 0x8f, 0x2a, 0x8f, 0xec, 0xdf, 0xec, 0xdf,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x650*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x660*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x670*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0xec, 0xdf,  0xec, 0xdf, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x680*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x690*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x6a0*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0xec, 0xdf, 0xec, 0xdf, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6b0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6c0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6d0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0xec, 0xdf, 0xec, 0xdf, 0x2a, 0x87,
+/*0x6e0*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x6f0*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x700*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0xec, 0xdf, 0xec, 0xdf,
+/*0x710*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x720*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x730*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0xcc, 0xd7,
+/*0x740*/	0xcc, 0xd7, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x750*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x760*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x770*/	0xab, 0xd7, 0xab, 0xd7, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x780*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x790*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x7a0*/	0xea, 0x86, 0x8b, 0xcf, 0x8b, 0xcf, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7b0*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7c0*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7d0*/	0xc9, 0x7e, 0xc9, 0x7e, 0x6b, 0xcf, 0x6b, 0xcf,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x7e0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x7f0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x800*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x2a, 0xc7,  0x2a, 0xc7, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x810*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x820*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x830*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x0a, 0xbf, 0x0a, 0xbf, 0x48, 0x76, 0x48, 0x76,
+/*0x840*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x850*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x860*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0xca, 0xb6, 0xca, 0xb6, 0x08, 0x6e,
+/*0x870*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x880*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x890*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x89, 0xae, 0x89, 0xae,
+/*0x8a0*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x8b0*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x8c0*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0x49, 0xa6,
+/*0x8d0*/	0x49, 0xa6, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x8e0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x8f0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x900*/	0x08, 0x9e, 0x08, 0x9e, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x910*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x920*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x930*/	0x67, 0x5d, 0xc8, 0x95, 0xc8, 0x95, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x940*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x950*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x960*/	0x26, 0x5d, 0x26, 0x5d, 0x87, 0x8d, 0x87, 0x8d,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x970*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x980*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x990*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x47, 0x85,  0x47, 0x85, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x9a0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x9b0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x9c0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0x06, 0x7d, 0x06, 0x7d, 0x85, 0x4c, 0x85, 0x4c,
+/*0x9d0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x9e0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x9f0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0xc6, 0x74, 0xc6, 0x74, 0x45, 0x44,
+/*0xa00*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xa10*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xa20*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x85, 0x64, 0x85, 0x64,
+/*0xa30*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xa40*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xa50*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x45, 0x5c,
+/*0xa60*/	0x45, 0x5c, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa70*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa80*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa90*/	0x04, 0x54, 0x04, 0x54, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xaa0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xab0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xac0*/	0xa3, 0x33, 0xc3, 0x4b, 0xc3, 0x4b, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xad0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xae0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xaf0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x43, 0x83, 0x43,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb00*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb10*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb20*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x3b,  0x43, 0x3b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xb30*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xb40*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xb50*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x02, 0x33, 0x02, 0x33, 0xe2, 0x22, 0xe2, 0x22,
+/*0xb60*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xb70*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xb80*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xc2, 0x2a, 0xc2, 0x2a, 0xc2, 0x22,
+/*0xb90*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xba0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xbb0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbc0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbd0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbe0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0x61, 0x22,
+/*0xbf0*/	0x61, 0x22, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc00*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc10*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc20*/	0x41, 0x1a, 0x41, 0x1a, 0x82, 0x22, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc30*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc40*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc50*/	0x41, 0x12, 0x20, 0x12, 0x20, 0x12, 0xaa, 0x5b,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x55, 0xad, 0x8a, 0x53, 0x42, 0x22, 0x00, 0x12,
+/*0xc90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xca0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xcb0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12,
+};
+
+// End of File
diff --git a/drivers/power/green_mid.h b/drivers/power/green_mid.h
new file mode 100644
index 0000000000..9b3088f892
--- /dev/null
+++ b/drivers/power/green_mid.h
@@ -0,0 +1,229 @@
+// Generate By BMP to RAW Conveter, By Leajian
+
+const unsigned char RES_green_mid_BIN[] = {
+	/* Source File: C:\Documents and Settings\zhaoy\Desktop\tupian\3\3\green_mid.bin */
+	/* File Size: 3518 Bytes */
+
+/*0x00*/	                                                 0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x10*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x20*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x30*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x40*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x50*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xa0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xb0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xe0*/	0x00, 0x12, 0x00, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0xf0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0x100*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0x110*/	0x20, 0x12, 0x00, 0x12, 0x00, 0x12, 0x20, 0x1a,  0x20, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x120*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x130*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x140*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x20, 0x1a, 0x20, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x150*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x160*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x170*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0x61, 0x1a,
+/*0x180*/	0x61, 0x1a, 0x81, 0x22, 0x81, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x190*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x1a0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x1b0*/	0xc2, 0x22, 0xc2, 0x22, 0x81, 0x22, 0x81, 0x22,  0xc1, 0x2a, 0xc1, 0x2a, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1c0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1d0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1e0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xc1, 0x2a, 0xc1, 0x2a, 0xe2, 0x32,
+/*0x1f0*/	0xe2, 0x32, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x200*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x210*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x220*/	0xe2, 0x32, 0xe2, 0x32, 0x22, 0x3b, 0x22, 0x3b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x230*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x240*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x250*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x22, 0x3b,  0x22, 0x3b, 0x63, 0x43, 0x63, 0x43, 0x63, 0x33,
+/*0x260*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x270*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x280*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x43, 0x63, 0x43,
+/*0x290*/	0xa3, 0x4b, 0xa3, 0x4b, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x2a0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x2b0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x2c0*/	0xa3, 0x33, 0xa3, 0x4b, 0xa3, 0x4b, 0xe4, 0x53,  0xe4, 0x53, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2d0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2e0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2f0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x53, 0xe4, 0x53, 0x44, 0x5c, 0x44, 0x5c,
+/*0x300*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x310*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x320*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x44, 0x5c,
+/*0x330*/	0x44, 0x5c, 0x85, 0x64, 0x85, 0x64, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x340*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x350*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x360*/	0x45, 0x44, 0x45, 0x44, 0x85, 0x64, 0x85, 0x64,  0xc6, 0x74, 0xc6, 0x74, 0x85, 0x4c, 0x85, 0x4c,
+/*0x370*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x380*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x390*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0xc6, 0x74, 0xc6, 0x74, 0x06, 0x7d,
+/*0x3a0*/	0x06, 0x7d, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x3b0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x3c0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x3d0*/	0x06, 0x7d, 0x06, 0x7d, 0x67, 0x85, 0x67, 0x85,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3e0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3f0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x400*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x67, 0x85,  0x67, 0x85, 0xa7, 0x8d, 0xa7, 0x8d, 0x46, 0x5d,
+/*0x410*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x420*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x430*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0xa7, 0x8d, 0xa7, 0x8d,
+/*0x440*/	0xe8, 0x95, 0xe8, 0x95, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x450*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x460*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x470*/	0x87, 0x65, 0xe8, 0x95, 0xe8, 0x95, 0x28, 0xa6,  0x28, 0xa6, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x480*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x490*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x4a0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0x28, 0xa6, 0x28, 0xa6, 0x69, 0xae, 0x69, 0xae,
+/*0x4b0*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x4c0*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x4d0*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0x69, 0xae,
+/*0x4e0*/	0x69, 0xae, 0xa9, 0xb6, 0xa9, 0xb6, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x4f0*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x500*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x510*/	0x28, 0x6e, 0x28, 0x6e, 0xa9, 0xb6, 0xa9, 0xb6,  0xea, 0xbe, 0xea, 0xbe, 0x49, 0x76, 0x49, 0x76,
+/*0x520*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x530*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x540*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0xea, 0xbe, 0xea, 0xbe, 0x2a, 0xc7,
+/*0x550*/	0x2a, 0xc7, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x560*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x570*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x580*/	0x2a, 0xc7, 0x2a, 0xc7, 0x4b, 0xc7, 0x4b, 0xc7,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x590*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x5a0*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x5b0*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0x4b, 0xc7,  0x4b, 0xc7, 0x8b, 0xcf, 0x8b, 0xcf, 0xca, 0x7e,
+/*0x5c0*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x5d0*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x5e0*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0x8b, 0xcf, 0x8b, 0xcf,
+/*0x5f0*/	0xab, 0xd7, 0xab, 0xd7, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x600*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x610*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x620*/	0xea, 0x86, 0xab, 0xd7, 0xab, 0xd7, 0xcc, 0xd7,  0xcc, 0xd7, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x630*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x640*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x650*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0xcc, 0xd7, 0xcc, 0xd7, 0xec, 0xdf, 0xec, 0xdf,
+/*0x660*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x670*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x680*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0xec, 0xdf,
+/*0x690*/	0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6a0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6b0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6c0*/	0x2a, 0x8f, 0x2a, 0x8f, 0xec, 0xdf, 0xec, 0xdf,  0xec, 0xdf, 0xec, 0xdf, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x6d0*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x6e0*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x6f0*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf,
+/*0x700*/	0xec, 0xdf, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x710*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x720*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x730*/	0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x740*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x750*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x760*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0xec, 0xdf,  0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf, 0x2a, 0x87,
+/*0x770*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x780*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x790*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0xec, 0xdf, 0xec, 0xdf,
+/*0x7a0*/	0xcc, 0xd7, 0xcc, 0xd7, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x7b0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x7c0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x7d0*/	0x0a, 0x87, 0xcc, 0xd7, 0xcc, 0xd7, 0xab, 0xd7,  0xab, 0xd7, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x7e0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x7f0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x800*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0xab, 0xd7, 0xab, 0xd7, 0x8b, 0xcf, 0x8b, 0xcf,
+/*0x810*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x820*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x830*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0x8b, 0xcf,
+/*0x840*/	0x8b, 0xcf, 0x6b, 0xcf, 0x6b, 0xcf, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x850*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x860*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x870*/	0xc9, 0x7e, 0xc9, 0x7e, 0x6b, 0xcf, 0x6b, 0xcf,  0x2a, 0xc7, 0x2a, 0xc7, 0x89, 0x7e, 0x89, 0x7e,
+/*0x880*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x890*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x8a0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x2a, 0xc7, 0x2a, 0xc7, 0x0a, 0xbf,
+/*0x8b0*/	0x0a, 0xbf, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x8c0*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x8d0*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x8e0*/	0x0a, 0xbf, 0x0a, 0xbf, 0xca, 0xb6, 0xca, 0xb6,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x8f0*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x900*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x910*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0xca, 0xb6,  0xca, 0xb6, 0x89, 0xae, 0x89, 0xae, 0x08, 0x6e,
+/*0x920*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x930*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x940*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x89, 0xae, 0x89, 0xae,
+/*0x950*/	0x49, 0xa6, 0x49, 0xa6, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x960*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x970*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x980*/	0xc8, 0x6d, 0x49, 0xa6, 0x49, 0xa6, 0x08, 0x9e,  0x08, 0x9e, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x990*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x9a0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x9b0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0x08, 0x9e, 0x08, 0x9e, 0xc8, 0x95, 0xc8, 0x95,
+/*0x9c0*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x9d0*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x9e0*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0xc8, 0x95,
+/*0x9f0*/	0xc8, 0x95, 0x87, 0x8d, 0x87, 0x8d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0xa00*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0xa10*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0xa20*/	0x26, 0x5d, 0x26, 0x5d, 0x87, 0x8d, 0x87, 0x8d,  0x47, 0x85, 0x47, 0x85, 0x06, 0x55, 0x06, 0x55,
+/*0xa30*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0xa40*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0xa50*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x47, 0x85, 0x47, 0x85, 0x06, 0x7d,
+/*0xa60*/	0x06, 0x7d, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0xa70*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0xa80*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0xa90*/	0x06, 0x7d, 0x06, 0x7d, 0xc6, 0x74, 0xc6, 0x74,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0xaa0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0xab0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0xac0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0xc6, 0x74,  0xc6, 0x74, 0x85, 0x64, 0x85, 0x64, 0x45, 0x44,
+/*0xad0*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xae0*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xaf0*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x85, 0x64, 0x85, 0x64,
+/*0xb00*/	0x45, 0x5c, 0x45, 0x5c, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xb10*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xb20*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xb30*/	0x04, 0x44, 0x45, 0x5c, 0x45, 0x5c, 0x04, 0x54,  0x04, 0x54, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xb40*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xb50*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xb60*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0x04, 0x54, 0x04, 0x54, 0xc3, 0x4b, 0xc3, 0x4b,
+/*0xb70*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xb80*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xb90*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xc3, 0x4b,
+/*0xba0*/	0xc3, 0x4b, 0x83, 0x43, 0x83, 0x43, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xbb0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xbc0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xbd0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x43, 0x83, 0x43,  0x43, 0x3b, 0x43, 0x3b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xbe0*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xbf0*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xc00*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x3b, 0x43, 0x3b, 0x02, 0x33,
+/*0xc10*/	0x02, 0x33, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xc20*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xc30*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xc40*/	0x02, 0x33, 0x02, 0x33, 0xc2, 0x2a, 0xc2, 0x2a,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xc50*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xc60*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xc70*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xc2, 0x2a,  0xc2, 0x2a, 0xa1, 0x22, 0xa1, 0x22, 0xc2, 0x22,
+/*0xc80*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xc90*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xca0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xcb0*/	0x61, 0x22, 0x61, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xcc0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xcd0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xce0*/	0xa1, 0x22, 0x61, 0x22, 0x61, 0x22, 0x41, 0x1a,  0x41, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xcf0*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xd00*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xd10*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x41, 0x1a, 0x41, 0x1a, 0x20, 0x12, 0x20, 0x12,
+/*0xd20*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xd30*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xd40*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x20, 0x12,
+/*0xd50*/	0x20, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xda0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xdb0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+};
+
+// End of File
diff --git a/drivers/power/green_right.h b/drivers/power/green_right.h
new file mode 100644
index 0000000000..32429629fc
--- /dev/null
+++ b/drivers/power/green_right.h
@@ -0,0 +1,213 @@
+// Generate By BMP to RAW Conveter, By Leajian
+
+const unsigned char RES_green_right_BIN[] = {
+	/* Source File: C:\Documents and Settings\zhaoy\Desktop\tupian\3\3\green_right.bin */
+	/* File Size: 3258 Bytes */
+
+/*0x00*/	                                                 0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x10*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x20*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x30*/	0x00, 0x12, 0x00, 0x12, 0x62, 0x22, 0xcb, 0x63,  0xb5, 0xb5, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x40*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x50*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0xeb, 0x63, 0x00, 0x12, 0x00, 0x12,
+/*0x70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0x90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x62, 0x22, 0x00, 0x12,
+/*0xa0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xb0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xd0*/	0x00, 0x12, 0x00, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0xe0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0xf0*/	0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,  0x20, 0x12, 0x20, 0x12, 0x20, 0x12, 0x20, 0x12,
+/*0x100*/	0x00, 0x12, 0x20, 0x1a, 0x20, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x110*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x120*/	0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a, 0x61, 0x1a,
+/*0x130*/	0x61, 0x1a, 0x20, 0x1a, 0x61, 0x1a, 0x61, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x140*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x150*/	0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,  0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a, 0xa1, 0x1a,
+/*0x160*/	0xa1, 0x1a, 0xa1, 0x1a, 0x61, 0x1a, 0x81, 0x22,  0x81, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x170*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x180*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0x190*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0x81, 0x22,  0xc1, 0x2a, 0xc1, 0x2a, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1a0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1b0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0x1c0*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xc1, 0x2a, 0xe2, 0x32, 0xe2, 0x32, 0x02, 0x2b,
+/*0x1d0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x1e0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,
+/*0x1f0*/	0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b, 0x02, 0x2b,  0x02, 0x2b, 0xe2, 0x32, 0x22, 0x3b, 0x22, 0x3b,
+/*0x200*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x210*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0x220*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x22, 0x3b, 0x63, 0x43,
+/*0x230*/	0x63, 0x43, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x240*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,
+/*0x250*/	0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x33,  0x63, 0x33, 0x63, 0x33, 0x63, 0x33, 0x63, 0x43,
+/*0x260*/	0xa3, 0x4b, 0xa3, 0x4b, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x270*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x280*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0x290*/	0xa3, 0x4b, 0xe4, 0x53, 0xe4, 0x53, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2a0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2b0*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0x2c0*/	0xe4, 0x3b, 0xe4, 0x53, 0x44, 0x5c, 0x44, 0x5c,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2d0*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2e0*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0x2f0*/	0x04, 0x44, 0x04, 0x44, 0x44, 0x5c, 0x85, 0x64,  0x85, 0x64, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x300*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x310*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0x320*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x85, 0x64,  0xc6, 0x74, 0xc6, 0x74, 0x85, 0x4c, 0x85, 0x4c,
+/*0x330*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x340*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x350*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0xc6, 0x74, 0x06, 0x7d, 0x06, 0x7d, 0xc6, 0x54,
+/*0x360*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x370*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x380*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0x06, 0x7d, 0x67, 0x85, 0x67, 0x85,
+/*0x390*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3a0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x3b0*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x67, 0x85, 0xa7, 0x8d,
+/*0x3c0*/	0xa7, 0x8d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x3d0*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,
+/*0x3e0*/	0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d,  0x46, 0x5d, 0x46, 0x5d, 0x46, 0x5d, 0xa7, 0x8d,
+/*0x3f0*/	0xe8, 0x95, 0xe8, 0x95, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x400*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x410*/	0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,  0x87, 0x65, 0x87, 0x65, 0x87, 0x65, 0x87, 0x65,
+/*0x420*/	0xe8, 0x95, 0x28, 0xa6, 0x28, 0xa6, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x430*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x440*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x450*/	0xa7, 0x65, 0x28, 0xa6, 0x69, 0xae, 0x69, 0xae,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x460*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x470*/	0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,  0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d, 0xe8, 0x6d,
+/*0x480*/	0xe8, 0x6d, 0xe8, 0x6d, 0x69, 0xae, 0xa9, 0xb6,  0xa9, 0xb6, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x490*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x4a0*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,  0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e,
+/*0x4b0*/	0x28, 0x6e, 0x28, 0x6e, 0x28, 0x6e, 0xa9, 0xb6,  0xea, 0xbe, 0xea, 0xbe, 0x49, 0x76, 0x49, 0x76,
+/*0x4c0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x4d0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,
+/*0x4e0*/	0x49, 0x76, 0x49, 0x76, 0x49, 0x76, 0x49, 0x76,  0xea, 0xbe, 0x2a, 0xc7, 0x2a, 0xc7, 0x89, 0x7e,
+/*0x4f0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x500*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x510*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x2a, 0xc7, 0x4b, 0xc7, 0x4b, 0xc7,
+/*0x520*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x530*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,
+/*0x540*/	0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e, 0xa9, 0x7e,  0xa9, 0x7e, 0xa9, 0x7e, 0x4b, 0xc7, 0x8b, 0xcf,
+/*0x550*/	0x8b, 0xcf, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x560*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,
+/*0x570*/	0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e,  0xca, 0x7e, 0xca, 0x7e, 0xca, 0x7e, 0x8b, 0xcf,
+/*0x580*/	0xab, 0xd7, 0xab, 0xd7, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x590*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x5a0*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x5b0*/	0xab, 0xd7, 0xcc, 0xd7, 0xcc, 0xd7, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5c0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5d0*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x5e0*/	0x0a, 0x87, 0xcc, 0xd7, 0xec, 0xdf, 0xec, 0xdf,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x5f0*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x600*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x610*/	0x2a, 0x87, 0x2a, 0x87, 0xec, 0xdf, 0xec, 0xdf,  0xec, 0xdf, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x620*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x630*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x640*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0xec, 0xdf,  0xec, 0xdf, 0xec, 0xdf, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x650*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x660*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x670*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf, 0x4a, 0x8f,
+/*0x680*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x690*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,
+/*0x6a0*/	0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f, 0x4a, 0x8f,  0x4a, 0x8f, 0xec, 0xdf, 0xec, 0xdf, 0xec, 0xdf,
+/*0x6b0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6c0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,
+/*0x6d0*/	0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f, 0x2a, 0x8f,  0x2a, 0x8f, 0x2a, 0x8f, 0xec, 0xdf, 0xec, 0xdf,
+/*0x6e0*/	0xec, 0xdf, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x6f0*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,
+/*0x700*/	0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87,  0x2a, 0x87, 0x2a, 0x87, 0x2a, 0x87, 0xec, 0xdf,
+/*0x710*/	0xcc, 0xd7, 0xcc, 0xd7, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x720*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x730*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x740*/	0xcc, 0xd7, 0xab, 0xd7, 0xab, 0xd7, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x750*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x760*/	0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,  0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87, 0x0a, 0x87,
+/*0x770*/	0x0a, 0x87, 0xab, 0xd7, 0x8b, 0xcf, 0x8b, 0xcf,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x780*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x790*/	0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,  0xea, 0x86, 0xea, 0x86, 0xea, 0x86, 0xea, 0x86,
+/*0x7a0*/	0xea, 0x86, 0xea, 0x86, 0x8b, 0xcf, 0x6b, 0xcf,  0x6b, 0xcf, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7b0*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7c0*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,  0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e,
+/*0x7d0*/	0xc9, 0x7e, 0xc9, 0x7e, 0xc9, 0x7e, 0x6b, 0xcf,  0x2a, 0xc7, 0x2a, 0xc7, 0x89, 0x7e, 0x89, 0x7e,
+/*0x7e0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x7f0*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,
+/*0x800*/	0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e, 0x89, 0x7e,  0x2a, 0xc7, 0x0a, 0xbf, 0x0a, 0xbf, 0x69, 0x76,
+/*0x810*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x820*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,
+/*0x830*/	0x69, 0x76, 0x69, 0x76, 0x69, 0x76, 0x69, 0x76,  0x69, 0x76, 0x0a, 0xbf, 0xca, 0xb6, 0xca, 0xb6,
+/*0x840*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x850*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,
+/*0x860*/	0x48, 0x76, 0x48, 0x76, 0x48, 0x76, 0x48, 0x76,  0x48, 0x76, 0x48, 0x76, 0xca, 0xb6, 0x89, 0xae,
+/*0x870*/	0x89, 0xae, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x880*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,
+/*0x890*/	0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e,  0x08, 0x6e, 0x08, 0x6e, 0x08, 0x6e, 0x89, 0xae,
+/*0x8a0*/	0x49, 0xa6, 0x49, 0xa6, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x8b0*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x8c0*/	0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,  0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d, 0xc8, 0x6d,
+/*0x8d0*/	0x49, 0xa6, 0x08, 0x9e, 0x08, 0x9e, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x8e0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x8f0*/	0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,  0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65, 0xa7, 0x65,
+/*0x900*/	0xa7, 0x65, 0x08, 0x9e, 0xc8, 0x95, 0xc8, 0x95,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x910*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x920*/	0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,  0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d, 0x67, 0x5d,
+/*0x930*/	0x67, 0x5d, 0x67, 0x5d, 0xc8, 0x95, 0x87, 0x8d,  0x87, 0x8d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x940*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x950*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,  0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d,
+/*0x960*/	0x26, 0x5d, 0x26, 0x5d, 0x26, 0x5d, 0x87, 0x8d,  0x47, 0x85, 0x47, 0x85, 0x06, 0x55, 0x06, 0x55,
+/*0x970*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x980*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,
+/*0x990*/	0x06, 0x55, 0x06, 0x55, 0x06, 0x55, 0x06, 0x55,  0x47, 0x85, 0x06, 0x7d, 0x06, 0x7d, 0xc6, 0x54,
+/*0x9a0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x9b0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,
+/*0x9c0*/	0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54, 0xc6, 0x54,  0xc6, 0x54, 0x06, 0x7d, 0xc6, 0x74, 0xc6, 0x74,
+/*0x9d0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x9e0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,
+/*0x9f0*/	0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c, 0x85, 0x4c,  0x85, 0x4c, 0x85, 0x4c, 0xc6, 0x74, 0x85, 0x64,
+/*0xa00*/	0x85, 0x64, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xa10*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,
+/*0xa20*/	0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x45, 0x44,  0x45, 0x44, 0x45, 0x44, 0x45, 0x44, 0x85, 0x64,
+/*0xa30*/	0x45, 0x5c, 0x45, 0x5c, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xa40*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xa50*/	0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,  0x04, 0x44, 0x04, 0x44, 0x04, 0x44, 0x04, 0x44,
+/*0xa60*/	0x45, 0x5c, 0x04, 0x54, 0x04, 0x54, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa70*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa80*/	0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,  0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b, 0xe4, 0x3b,
+/*0xa90*/	0xe4, 0x3b, 0x04, 0x54, 0xc3, 0x4b, 0xc3, 0x4b,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xaa0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xab0*/	0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,  0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33, 0xa3, 0x33,
+/*0xac0*/	0xa3, 0x33, 0xa3, 0x33, 0xc3, 0x4b, 0x83, 0x43,  0x83, 0x43, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xad0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xae0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,  0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x33,
+/*0xaf0*/	0x83, 0x33, 0x83, 0x33, 0x83, 0x33, 0x83, 0x43,  0x43, 0x3b, 0x43, 0x3b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb00*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb10*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,
+/*0xb20*/	0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b, 0x43, 0x2b,  0x43, 0x3b, 0x02, 0x33, 0x02, 0x33, 0x22, 0x2b,
+/*0xb30*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xb40*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,
+/*0xb50*/	0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b, 0x22, 0x2b,  0x22, 0x2b, 0x02, 0x33, 0xc2, 0x2a, 0xc2, 0x2a,
+/*0xb60*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xb70*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,
+/*0xb80*/	0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22, 0xe2, 0x22,  0xe2, 0x22, 0xe2, 0x22, 0xc2, 0x2a, 0xa1, 0x22,
+/*0xb90*/	0xa1, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xba0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,
+/*0xbb0*/	0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22,  0xc2, 0x22, 0xc2, 0x22, 0xc2, 0x22, 0xa1, 0x22,
+/*0xbc0*/	0x61, 0x22, 0x61, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbd0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbe0*/	0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,  0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22, 0xa1, 0x22,
+/*0xbf0*/	0x61, 0x22, 0x41, 0x1a, 0x41, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc00*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc10*/	0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,  0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a, 0x81, 0x1a,
+/*0xc20*/	0x81, 0x1a, 0x41, 0x1a, 0x20, 0x12, 0x20, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc30*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc40*/	0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,  0x41, 0x12, 0x41, 0x12, 0x41, 0x12, 0x41, 0x12,
+/*0xc50*/	0x41, 0x12, 0x41, 0x12, 0x62, 0x22, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc60*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc70*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc80*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x8a, 0x5b,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xc90*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xca0*/	0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,  0x00, 0x12, 0x00, 0x12, 0x00, 0x12, 0x00, 0x12,
+/*0xcb0*/	0x00, 0x12, 0x00, 0x12, 0x42, 0x22, 0x8a, 0x53,  0x55, 0xad,
+};
+
+// End of File
diff --git a/drivers/power/max17042_battery.c b/drivers/power/max17042_battery.c
new file mode 100644
index 0000000000..7525d65d49
--- /dev/null
+++ b/drivers/power/max17042_battery.c
@@ -0,0 +1,197 @@
+/*
+ * (C) Copyright 2000
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ */
+
+#include <common.h>
+#include "max17042_battery.h"
+#include <i2c.h>
+
+enum max17042_register {
+	MAX17042_STATUS		= 0x00,
+	MAX17042_VALRT_Th	= 0x01,
+	MAX17042_TALRT_Th	= 0x02,
+	MAX17042_SALRT_Th	= 0x03,
+	MAX17042_AtRate		= 0x04,
+	MAX17042_RepCap		= 0x05,
+	MAX17042_RepSOC		= 0x06,
+	MAX17042_Age		= 0x07,
+	MAX17042_TEMP		= 0x08,
+	MAX17042_VCELL		= 0x09,
+	MAX17042_Current	= 0x0A,
+	MAX17042_AvgCurrent	= 0x0B,
+	MAX17042_Qresidual	= 0x0C,
+	MAX17042_SOC		= 0x0D,
+	MAX17042_AvSOC		= 0x0E,
+	MAX17042_RemCap		= 0x0F,
+	MAX17402_FullCAP	= 0x10,
+	MAX17042_TTE		= 0x11,
+	MAX17042_V_empty	= 0x12,
+
+	MAX17042_RSLOW		= 0x14,
+
+	MAX17042_AvgTA		= 0x16,
+	MAX17042_Cycles		= 0x17,
+	MAX17042_DesignCap	= 0x18,
+	MAX17042_AvgVCELL	= 0x19,
+	MAX17042_MinMaxTemp	= 0x1A,
+	MAX17042_MinMaxVolt	= 0x1B,
+	MAX17042_MinMaxCurr	= 0x1C,
+	MAX17042_CONFIG		= 0x1D,
+	MAX17042_ICHGTerm	= 0x1E,
+	MAX17042_AvCap		= 0x1F,
+	MAX17042_ManName	= 0x20,
+	MAX17042_DevName	= 0x21,
+	MAX17042_DevChem	= 0x22,
+
+	MAX17042_TempNom	= 0x24,
+	MAX17042_TempCold	= 0x25,
+	MAX17042_TempHot	= 0x26,
+	MAX17042_AIN		= 0x27,
+	MAX17042_LearnCFG	= 0x28,
+	MAX17042_SHFTCFG	= 0x29,
+	MAX17042_RelaxCFG	= 0x2A,
+	MAX17042_MiscCFG	= 0x2B,
+	MAX17042_TGAIN		= 0x2C,
+	MAx17042_TOFF		= 0x2D,
+	MAX17042_CGAIN		= 0x2E,
+	MAX17042_COFF		= 0x2F,
+
+	MAX17042_Q_empty	= 0x33,
+	MAX17042_T_empty	= 0x34,
+
+	MAX17042_RCOMP0		= 0x38,
+	MAX17042_TempCo		= 0x39,
+	MAX17042_Rx		= 0x3A,
+	MAX17042_T_empty0	= 0x3B,
+	MAX17042_TaskPeriod	= 0x3C,
+	MAX17042_FSTAT		= 0x3D,
+
+	MAX17042_SHDNTIMER	= 0x3F,
+
+	MAX17042_VFRemCap	= 0x4A,
+
+	MAX17042_QH		= 0x4D,
+	MAX17042_QL		= 0x4E,
+};
+
+static int max17042_read_reg(u8 reg, u16 *data)
+{
+	int status;
+
+	i2c_set_bus_num(0);
+	status = i2c_read(MAX17042_I2C_ADDR, reg, 1, (u8 *)data, 2);
+	if (status < 0)
+		return status;
+	else
+		return 0;
+}
+
+static int max17042_write_reg(u8 reg, u16 data)
+{
+	int status;
+	unsigned char buffer[2];
+
+	buffer[0] = data & 0xff;
+	buffer[1] = (data & 0xff00) >> 8;
+	i2c_set_bus_num(0);
+	status = i2c_write(MAX17042_I2C_ADDR, reg, 1, buffer, 2);
+	if (status < 0)
+		return status;
+	else
+		return 0;
+}
+
+/* Capacity: % */
+int max17042_get_capacity(void)
+{
+	u16 data;
+	int ret = 0;
+
+	ret = max17042_read_reg(MAX17042_RepSOC, &data);
+	if (ret < 0)
+		return ret;
+	ret = data >> 8;
+	if (ret > 100)
+		ret = 100;
+	return ret;
+}
+
+/* Voltage: µV */
+int max17042_get_voltage(void)
+{
+	u16 data;
+	int ret = 0;
+
+	ret = max17042_read_reg(MAX17042_VCELL, &data);
+	if (ret < 0)
+		return ret;
+	return (data >> 3) * 625;
+}
+
+/* Current: µA */
+int max17042_get_current(void)
+{
+	u16 data;
+	int t;
+	int ret = 0;
+
+	ret = max17042_read_reg(MAX17042_Current, &data);
+	if (ret < 0)
+		return ret;
+	if (0x8000 & data)
+		t = ((~data & 0x7FFF) + 1) * -1;
+	else
+		t = data;
+	return t * (1562500 / MAX17042_DEFAULT_R_SNS);
+}
+
+/* send SoftPOR cmd just only when the mode is in the unlocked state.
+ * Do NOT call this reset function frequently. It would causes the
+ * fuel-gauge to forget valuable information which is learned very
+ * rarely.
+ */
+int max17042_reset(void)
+{
+	u16 reg62, reg63, status;
+	int num;
+
+	num = 0;
+	do {
+		if (max17042_write_reg(0x62, 0x0000) ||
+			max17042_write_reg(0x63, 0x0000) ||
+			max17042_write_reg(MAX17042_STATUS, 0x0000))
+			goto err;
+		if (max17042_read_reg(0x62, &reg62) ||
+			max17042_read_reg(0x63, &reg63) ||
+			max17042_read_reg(MAX17042_STATUS, &status))
+			goto err;
+		num++;
+	} while ((reg62 || reg63 || status) && (num < 50));
+
+	num = 0;
+	do {
+		/* send softPOR cmd */
+		max17042_write_reg(0x60, 0x000f);
+		udelay(2000);
+		if (max17042_read_reg(MAX17042_STATUS, &status))
+			goto err;
+		num++;
+	} while (((status & 0x2) == 0x0) && (num < 50));
+
+	return 0;
+err:
+	return -1;
+}
diff --git a/drivers/power/max17042_battery.h b/drivers/power/max17042_battery.h
new file mode 100644
index 0000000000..83f2fbe4fd
--- /dev/null
+++ b/drivers/power/max17042_battery.h
@@ -0,0 +1,27 @@
+/*
+ * (C) Copyright 2000
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MAX17042_BATTERY_H__
+#define __MAX17042_BATTERY_H__
+
+#define MAX17042_I2C_ADDR	(0x36)
+#define MAX17042_DEFAULT_R_SNS	(10000) /* mirco-ohms */
+
+/* function declarations */
+int max17042_get_capacity(void);
+int max17042_get_voltage(void);
+int max17042_get_current(void);
+int max17042_reset(void);
+
+#endif
diff --git a/drivers/power/mmp2_dvfm_ll.S b/drivers/power/mmp2_dvfm_ll.S
new file mode 100644
index 0000000000..a1c0c7149e
--- /dev/null
+++ b/drivers/power/mmp2_dvfm_ll.S
@@ -0,0 +1,738 @@
+/*
+ * Low-level frequency change code
+ *
+ * Copyright (C) 2009, Marvell Semicondutor.
+ *
+ * This software program is licensed subject to the GNU General Public License
+ * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
+ */
+
+#include <config.h>
+
+	.global freq_init_sram, freq_chg_seq
+
+@******************************************************************************
+@
+@ freq_init_sram
+@
+@ Copy frequency change code into ISRAM
+@
+@ Inputs:
+@	r0 = Start address of relocated program
+@
+@ Outputs:
+@	None
+@
+
+freq_init_sram:
+	stmfd	sp!, {r0 - r12, lr}
+	ldr	r3, =freq_sram_start
+	ldr	r4, =freq_sram_end
+	add	r4, r4, #0x200
+
+rel_ram:
+	ldmia	r3!, {r5 - r12}
+	stmia	r0!, {r5 - r12}
+	cmp	r3, r4
+	ble	rel_ram
+
+	ldmfd	sp!, {r0 - r12, pc}
+
+@******************************************************************************
+@
+@ freq_chg_seq
+@
+@ frequency change sequence
+@
+@ Inputs:
+@	r0 = Start address of relocated program
+@	r1 = Start address of relocated stack
+@	r2 = operating points
+@	r3 = chip steppings: 0 - z0, 1 - z1, 2 - a0 and 3 - a1
+@
+@ Outputs:
+@	None
+@
+
+#define PMUM_FCCR_OFF	0x0008
+#define PMUA_CC_AP_OFF	0x0004
+
+freq_chg_seq:
+
+	@ save registers on stack
+	stmfd	sp!, {r3 - r12, lr}
+
+	mov	r12, r0			@ save start address of program in r12
+	mov	r11, r1			@ save start address of stack in r11
+	mov	r10, sp			@ save sp in r10
+	mov	sp, r11			@ set up new stack address
+	stmfd	sp!, {lr}		@ store the return address
+
+#if (defined(CONFIG_MMP2_JASPER) || defined(CONFIG_MMP2_FLINT) || defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MMP2_G50))
+	ldr	r4, =0xd0000000		@ DMEM base address
+#else
+	ldr	r4, =0xb0000000		@ DMEM base address
+#endif
+	ldr	r5, =0xd4050000		@ PMUM base address
+	ldr	r6, =0xd4282800		@ PMUA base address
+	mov	pc, r0
+
+freq_sram_start:
+	cmp	r3, #0x3
+	bne	1f
+
+	ldr	r7, =0x1
+	str	r7, [r4, #0x7e0]
+	ldr	r7, =0x40
+	str	r7, [r4, #0x120]
+
+	b	1f
+	.align  5
+1:
+#if (defined(CONFIG_MMP2_JASPER) || defined(CONFIG_MMP2_FLINT) || defined(CONFIG_MACH_BROWNSTONE) || defined(CONFIG_MMP2_G50))
+	@
+	@ frequency change
+	@
+
+	@ turn on all clocks and allow freq in debug register
+	ldr	r7, =0xffffffff
+	str	r7, [r5, #0x0024]
+	@ ldr	r7, =0x00061808
+	@ str	r7, [r6, #0x88]
+
+	@ change to PLL1/2 first, start-up operation point
+	ldr	r7, =0x00000000
+	str	r7, [r5, #0x8]
+	ldr	r7, =0x08fd96d9
+	str	r7, [r6, #0x00]
+	ldr	r7, =0x78fd96d9
+	str	r7, [r6, #0x04]
+
+	@ pclk 100/dclk 400/aclk 100
+	cmp	r2, #0x0
+	bne	2f
+
+	@ select PLL2 frequency, 988MHz
+	ldr	r7, =0x08600622
+	str	r7, [r5, #0x0414]
+	ldr	r7, =0x00FFFE00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238A00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238B00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x28600622
+	str	r7, [r5, #0x0414]
+	@ select clock source, PJ4-PLL1/2, SP-PLL1/2, AXI/DDR-PLL1
+	ldr	r7, =0x00800000
+	str	r7, [r5, #0x0008]
+	@ divider setting and frequency change request, core-100, ddr-400, axi-100
+	ldr	r7, =0x08fd8041
+	str	r7, [r6, #0x00]
+	ldr	r7, =0xf8ff86db
+	str	r7, [r6, #0x04]
+
+	@ pclk 200/dclk 400/aclk 200
+2:
+	cmp	r2, #0x1
+	bne	3f
+
+	@ select PLL2 frequency, 988MHz
+	ldr	r7, =0x08600622
+	str	r7, [r5, #0x0414]
+	ldr	r7, =0x00FFFE00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238A00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238B00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x28600622
+	str	r7, [r5, #0x0414]
+	@ select clock source, PJ4-PLL1/2, SP-PLL1/2, AXI/DDR-PLL1
+	ldr	r7, =0x00800000
+	str	r7, [r5, #0x0008]
+	@ divider setting and frequency change request, core-200, ddr-400, axi-200
+	ldr	r7, =0x08fd8041
+	str	r7, [r6, #0x00]
+	ldr	r7, =0xf8fd8249
+	str	r7, [r6, #0x04]
+
+	@ pclk 400/dclk 400/aclk 200
+3:
+	cmp	r2, #0x2
+	bne	4f
+	@ select PLL2 frequency, 988MHz
+	ldr	r7, =0x08600622
+	str	r7, [r5, #0x0414]
+	ldr	r7, =0x00FFFE00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238A00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238B00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x28600622
+	str	r7, [r5, #0x0414]
+	@ select clock source, PJ4-PLL1/2, SP-PLL1/2, AXI/DDR-PLL1
+	ldr	r7, =0x00800000
+	str	r7, [r5, #0x0008]
+	@ divider setting and frequency change request, core-400, ddr-400, axi-200
+	ldr	r7, =0x08fd8041
+	str	r7, [r6, #0x00]
+	ldr	r7, =0xf8fd8000
+	str	r7, [r6, #0x04]
+
+	@ pclk 800/dclk 400/aclk 266
+4:
+	cmp	r2, #0x3
+	bne	5f
+	@ select PLL2 frequency, 988MHz
+	ldr	r7, =0x08600322
+	str	r7, [r5, #0x0414]
+	ldr	r7, =0x00FFFE00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238a00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238b00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x28600622
+	str	r7, [r5, #0x0414]
+	@ select clock source, PJ4-PLL1, SP-PLL1/2, AXI/DDR-PLL1
+	ldr	r7, =0x20800000
+	str	r7, [r5, #0x0008]
+	@ divider setting and frequency change request, core-800, ddr-400, axi-200
+	ldr	r7, =0x08fd0248
+	str	r7, [r6, #0x00]
+	ldr	r7, =0xf8fd0248
+	str	r7, [r6, #0x04]
+
+	@ pclk 988/dclk 400/aclk 266
+5:
+	cmp	r2, #0x4
+	bne	6f
+	@ select PLL2 frequency, 988MHz
+	ldr	r7, =0x08600622
+	str	r7, [r5, #0x0414]
+	ldr	r7, =0x00FFFE00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238A00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x00238B00
+	str	r7, [r5, #0x0034]
+	ldr	r7, =0x28600622
+	str	r7, [r5, #0x0414]
+	@ select clock source, PJ4-PLL2, SP-PLL1/2, AXI/DDR-PLL1
+	ldr	r7, =0x40800000
+	str	r7, [r5, #0x0008]
+	@ divider setting and frequency change request, core-988, ddr-400, axi-266
+	ldr	r7, =0x08fd0248
+	str	r7, [r6, #0x00]
+	ldr	r7, =0xf8fd0248
+	str	r7, [r6, #0x04]
+
+	b	6f
+
+	@dummy reads
+	mov	r8, #500
+	mov	r9, #0x0
+loop_delay:
+	ldr	r7, [r9, #0x0]
+	subs	r8, r8, #1
+	bne	loop_delay
+
+6:
+	@
+	@ ddr re-calibration after frequency change
+	@
+
+	ldr	r7, =freq_sram_start
+#if (defined(CONFIG_DDR_MICRON_256M))
+	ldr	r8, =mmp2_micron256_ddr
+#elif (defined(CONFIG_DDR_EPD_512M))
+	ldr	r8, =mmp2_epd512_ddr
+#elif (defined(CONFIG_MMP2_FLINT))
+	ldr	r8, =mmp2_epd256_ddr
+#elif (defined(CONFIG_DDR3_EPD_1G))
+	cmp	r3, #0x3
+	beq	a1_setting
+	ldr	r8, =mmp2_epd1024_ddr3
+	b	ddr_recalibrate
+a1_setting:
+	ldr	r8, =a1_mmp2_epd1024_ddr3
+#elif (defined(CONFIG_DDR3_EPD_512M))
+	ldr	r8, =a1_mmp2_epd512_ddr3
+#else
+	#error	"please define ddr table"
+#endif
+ddr_recalibrate:
+	sub	r8, r8, r7
+
+loop:
+	ldr	r3, [r0, r8]
+	cmp	r3, #0x80000000
+	beq	finished
+	cmp	r3, #0x40000000
+	bne	200f
+	add	r8, r8, #0x8
+	ldr	r7, [r0, r8]
+	ldr	r12, [r4, r7]
+	add	r8, r8, #0x8
+	b	loop
+200:
+	cmp	r3, #0x20000000
+	bne	300f
+	add	r8, r8, #0x8
+	ldr	r7, [r0, r8]
+	ldr	r12, [r4, r7]
+	add	r8, r8, #0x4
+	ldr	r9, [r0, r8]
+	and	r9, r9, r12
+	str	r9, [r4, r7]
+	add	r8, r8, #0x4
+	b	loop
+300:
+	cmp	r3, #0x10000000
+	bne	400f
+	add	r8, r8, #0x8
+	ldr	r7, [r0, r8]
+	ldr	r12, [r4, r7]
+	add	r8, r8, #0x4
+	ldr	r9, [r0, r8]
+	orr	r9, r9, r12
+	str	r9, [r4, r7]
+	add	r8, r8, #0x4
+	b	loop
+400:
+	ldr	r7, [r0, r8]
+	add	r8, r8, #0x4
+	ldr	r9, [r0, r8]
+	str	r9, [r4, r7]
+	add	r8, r8, #0x4
+	b	loop
+
+finished:
+	@ ldr	r7, =0x80
+	@ str	r7, [r4, #0x120]
+	ldr	r7, =0x0
+	str	r7, [r4, #0x7e0]
+
+	@dummy reads for PHY DQ byte read DLLs to update
+	mov	r8, #131
+	mov	r9, #0x0
+1:
+	ldr	r7, [r9, #0x0]
+	subs	r8, r8, #1
+	bne	1b
+
+	ldr	r7, [r4, #0x240]
+
+#else
+	@ frequency change sequence
+	ldr	r7, =0x2000088e
+	str	r7, [r5, #PMUM_FCCR_OFF]
+
+	ldr	r7, =0xf0e482f8
+	str	r7, [r6, #PMUA_CC_AP_OFF]
+
+	@ ddr caliberation
+#endif
+
+	@ return
+	ldmfd	sp!, {lr}
+	mov	sp, r10				@ restore stack address
+
+        ldmfd   sp!, {r3 - r12, pc}
+
+
+	/*
+	 * special translation for offset:
+	 *	0x10000000	or
+	 *	0x20000000	and
+	 *	0x40000000	read
+	 *	0x80000000	end
+	 */
+#if (defined(CONFIG_DDR_MICRON_256M))
+mmp2_micron256_ddr:
+	.long	0x010, 	0xD0004D56	@ CONFIG_DECODE_ADDR
+	.long	0x100, 	0x000B0001	@ MMAP
+	.long	0x110, 	0x080B0001
+
+	.long	0x020, 	0x00006320	@ CONFIG_TYPE
+	.long	0x030, 	0x00006320
+	.long	0xB40, 	0x00000000
+	.long	0xB50, 	0x00000000
+
+	.long	0x050, 	0x4CD800C5	@ TIMING
+	.long	0x060, 	0x84660342
+	.long	0x190, 	0x2000381B
+	.long	0x1C0, 	0x3023009D
+	.long	0x650, 	0x00110142
+	.long	0x660, 	0x02424190
+
+	.long	0x080, 	0x00005000	@ CTRL
+	.long	0x090, 	0x00080010
+	.long	0x0F0, 	0xC0000000
+	.long	0x1A0, 	0x20C08115
+	.long	0x280, 	0x01010101
+	.long	0x760, 	0x00000000
+	.long	0x770, 	0x03000000
+	.long	0x780, 	0x00000133
+	.long	0x7B0, 	0x01010101
+	.long	0x7D0, 	0x0000000F
+	.long	0x7E0, 	0x00000000
+
+	.long	0x540, 	0x00000000	@ MCB
+	.long	0x570, 	0x00000001
+	.long	0x580, 	0x00000000
+	.long	0x590, 	0x00000000
+	.long	0x5A0, 	0x00000000
+	.long	0x5B0, 	0x00000000
+
+	.long	0x180, 	0x00000000	@ WRITE_PROTECTION
+
+	.long	0x210, 	0x00000000	@ __PHY Deskew PLL config and PHY initialization
+	.long	0x240, 	0x80000000
+
+	.long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x20000000
+	.long	0x20000000, 0x0
+	.long	0x240,	0xdfffffff
+
+	.long	0x10000000, 0x0		@ Pad drive strength auto calibration
+	.long	0x200,	0x00110000
+	.long	0x40000000, 0x0
+	.long	0x240,	0x0
+	.long	0x20000000, 0x0
+	.long	0x200,	0xfffeffff
+
+	.long	0x140, 	0x20004455
+	.long	0x1D0, 	0x13300559
+	.long	0x1E0, 	0x03300770
+	.long	0x1F0, 	0x00000077
+
+	.long	0x230, 	0x20000088
+	.long	0xE10, 	0x00000080
+	.long	0xE20, 	0x00000080
+	.long	0xE30, 	0x00000080
+
+	.long	0xE40, 	0x00000000
+	.long	0xE50, 	0x00000000
+
+	.long	0x120, 	0x03000001	@ initialize LPDDR2
+	.long	0x40000000, 0x0
+	.long	0x1b0,	0x0
+	.long	0x410, 	0x0302003F
+	.long	0x120, 	0x01001000
+	.long	0x120, 	0x02001000
+	.long	0x410, 	0x03020001
+	.long	0x410, 	0x03020002
+	.long	0x410, 	0x03020003
+	.long	0x80000000, 0x0
+#elif (defined(CONFIG_DDR_EPD_512M))
+mmp2_epd512_ddr:
+	.long	0x010, 	0xD0004D56	@ CONFIG_DECODE_ADDR
+	.long	0x100, 	0x000C0001	@ MMAP
+	.long	0x110, 	0x100C0001
+
+	.long	0x020, 	0x00006420	@ CONFIG_TYPE
+	.long	0x030, 	0x00006420
+	.long	0xB40, 	0x00000000
+	.long	0xB50, 	0x00000000
+
+	.long	0x050, 	0x4CDA00C5	@ TIMING
+	.long	0x060, 	0x94860342
+	.long	0x190, 	0x2000381B
+	.long	0x1C0, 	0x3023009D
+	.long	0x650, 	0x00110142
+	.long	0x660, 	0x02424190
+
+	.long	0x080, 	0x00005000	@ CTRL
+	.long	0x090, 	0x00080010
+	.long	0x0F0, 	0xC0000000
+	.long	0x1A0, 	0x20C08115
+	.long	0x280, 	0x01010101
+	.long	0x760, 	0x00000000
+	.long	0x770, 	0x03000000
+	.long	0x780, 	0x00000133
+	.long	0x7B0, 	0x01010101
+	.long	0x7D0, 	0x0000000F
+	.long	0x7E0, 	0x00000000
+
+	.long	0x540, 	0x00000000	@ MCB
+	.long	0x570, 	0x00000001
+	.long	0x580, 	0x00000000
+	.long	0x590, 	0x00000000
+	.long	0x5A0, 	0x00000000
+	.long	0x5B0, 	0x00000000
+
+	.long	0x180, 	0x00000000	@ WRITE_PROTECTION
+
+	.long	0x210, 	0x00000000	@ __PHY Deskew PLL config and PHY initialization
+	.long	0x240, 	0x80000000
+
+	.long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x20000000
+	.long	0x20000000, 0x0
+	.long	0x240,	0xdfffffff
+
+	.long	0x10000000, 0x0		@ Pad drive strength auto calibration
+	.long	0x200,	0x00110000
+	.long	0x40000000, 0x0
+	.long	0x240,	0x0
+	.long	0x20000000, 0x0
+	.long	0x200,	0xfffeffff
+
+	.long	0x140, 	0x20004433
+	.long	0x1D0, 	0x13300559
+	.long	0x1E0, 	0x03300990
+	.long	0x1F0, 	0x00000077
+
+	.long	0x230, 	0x20000088
+	.long	0xE10, 	0x00000080
+	.long	0xE20, 	0x00000080
+	.long	0xE30, 	0x00000080
+
+	.long	0xE40, 	0x00000000
+	.long	0xE50, 	0x00000000
+
+	.long	0x120, 	0x03000001	@ initialize LPDDR2
+	.long	0x40000000, 0x0
+	.long	0x1b0,	0x0
+	.long	0x410, 	0x0302003F
+	.long	0x120, 	0x01001000
+	.long	0x120, 	0x02001000
+	.long	0x410, 	0x03020001
+	.long	0x410, 	0x03020002
+	.long	0x410, 	0x03020003
+	.long	0x80000000, 0x0
+#elif (defined(CONFIG_MMP2_FLINT))
+mmp2_epd256_ddr:
+	/*	offset	value	*/
+	.long	0x0,	0xD0004D56	@ CONFIG_DECODE_ADDR
+
+	.long	0x100, 	0x000B0001	@ MMAP
+	.long	0x110, 	0x080B0001
+
+	.long	0x20, 	0x00006320	@ CONFIG_TYPE
+	.long	0x30, 	0x00006320
+
+	.long	0x50, 	0x4cd800c5	@ TIMING
+	.long	0x60, 	0x84660342
+	.long	0x190, 	0x2000381B
+	.long	0x1C0, 	0x3023009D
+	.long	0x650, 	0x00110142
+	.long	0x660, 	0x02424190
+
+	.long	0xf0, 	0xc0000000	@ CTRL
+	.long	0x1a0, 	0x20c08115
+	.long	0x760, 	0x0
+	.long	0x770, 	0x0
+
+	.long	0x210, 	0x00000000	@ __PHY Deskew PLL config and PHY initialization
+	.long	0x240, 	0x80000000
+
+	.long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x20000000
+	.long	0x20000000, 0x0
+	.long	0x240,	0xdfffffff
+
+	.long	0x10000000, 0x0		@ Pad drive strength auto calibration
+	.long	0x200,	0x00110000
+	.long	0x40000000, 0x0
+	.long	0x240,	0x0
+	.long	0x20000000, 0x0
+	.long	0x200,	0xfffeffff
+
+	.long	0x140, 	0x20004433
+	.long	0x1D0, 	0x177C2779
+	.long	0x1e0, 	0x0aa00770
+	.long	0x1f0, 	0xc0000077
+
+	.long	0x230, 	0x20000108
+	.long	0xE10, 	0x00000100
+	.long	0xE20, 	0x00000100
+	.long	0xE30, 	0x00000100
+
+	.long	0xE10, 	0x205c7d00
+	.long	0xE20, 	0x205c7d00
+	.long	0xE30, 	0x205c7d00
+
+	.long	0x120, 	0x03000001	@ initialize LPDDR2
+	.long	0x40000000, 0x0
+	.long	0x1b0,	0x0
+	.long	0x410, 	0x0302003f
+	.long	0x120, 	0x01001000
+	.long	0x120, 	0x02001000
+	.long	0x410, 	0x03020001
+	.long	0x410, 	0x03020002
+	.long	0x410, 	0x03020003
+	.long	0x80000000, 0x0
+#elif (defined(CONFIG_DDR3_EPD_1G))
+a1_mmp2_epd1024_ddr3:
+	@ .long	0x010, 	0xD0004D56	@ CONFIG_DECODE_ADDR
+	@ .long	0x100, 	0x000D0001	@ MMAP
+	@ .long	0x110, 	0x200D0001
+
+	@ .long	0x020, 	0x00022430	@ CONFIG_TYPE
+	@ .long	0x030, 	0x00022430
+	@ .long	0xB40, 	0x00000000
+	@ .long	0xB50, 	0x00000000
+
+	@ .long	0x050, 	0x911500cA	@ TIMING
+	@ .long	0x060, 	0x646602C4
+	@ .long	0x190, 	0xc2003053
+	@ .long	0x1C0, 	0x34F4A187
+	@ .long	0x650, 	0x000F0141
+	@ .long	0x660, 	0x04040200
+
+	@ .long	0x080, 	0x90045000	@ CTRL
+	@ .long	0x090, 	0x00100000
+	@ .long	0x0F0, 	0xC0000000
+	@ .long	0x1A0, 	0x20C0C409
+	@ .long	0x280, 	0x01010101
+	@ .long	0x760, 	0x00000201
+	@ .long	0x770, 	0x0200000A
+	@ .long	0x780, 	0x00000133
+	@ .long	0x7B0, 	0x01010101
+	@ .long	0x7D0, 	0x00000001
+	@ .long	0x7E0, 	0x00000000
+
+	@ .long	0x540, 	0x00000000	@ MCB
+	@ .long	0x570, 	0x00000001
+	@ .long	0x580, 	0x00000000
+	@ .long	0x590, 	0x00000000
+	@ .long	0x5A0, 	0x00000000
+	@ .long	0x5B0, 	0x00000000
+
+	@ .long	0x180, 	0x00000000	@ WRITE_PROTECTION
+
+	@ .long	0x210, 	0x00000000	@ __PHY Deskew PLL config and PHY initialization
+	.long	0x240, 	0x80000000
+
+	@ .long	0x10000000, 0x0		@ Pad drive strength auto calibration
+	@ .long	0x200,	0x00110000
+	@ .long	0x20000000, 0x0
+	@ .long	0x200,	0xfffeffff
+
+	@ .long	0x140, 	0x20004055
+	@ .long	0x1D0, 	0x17721869
+	@ .long	0x1E0, 	0x07700860
+	@ .long	0x1F0, 	0x00000086
+
+	.long	0x10000000, 0x0
+	.long	0x230, 	0xf0000000
+	@ .long	0xE10, 	0x00000040
+	@ .long	0xE20, 	0x00000040
+	@ .long	0xE30, 	0x00000040
+
+	@ .long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x20000000
+	@ .long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x40000000
+	@ .long	0x20000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	@ .long	0x240,	0xdfffffff
+
+	.long	0x120,	0x00000080
+	.long	0x10000000, 0x0
+	.long	0x80,	0x00000040
+	.long	0x120,	0x01000100
+	@ .long	0xE40, 	0x00000000
+	@ .long	0xE50, 	0x00000000
+
+	@ .long	0x120, 	0x03000001	@ initialize LPDDR2
+	@ .long	0x40000000, 0x0
+	@ .long	0x1b0,	0x0
+	@ .long	0x120, 	0x01001000
+	@ .long	0x120, 	0x02001000
+	.long	0x80000000, 0x0
+
+mmp2_epd1024_ddr3:
+	.long	0x010, 	0xD0004D56	@ CONFIG_DECODE_ADDR
+	.long	0x100, 	0x000D0001	@ MMAP
+	.long	0x110, 	0x200D0001
+
+	.long	0x020, 	0x00222430	@ CONFIG_TYPE
+	.long	0x030, 	0x00222430
+	.long	0xB40, 	0x00000000
+	.long	0xB50, 	0x00000000
+
+	.long	0x050, 	0x911500cA	@ TIMING
+	.long	0x060, 	0x646602C4
+	.long	0x190, 	0xc2003053
+	.long	0x1C0, 	0x34F4A187
+	.long	0x650, 	0x000F0141
+	.long	0x660, 	0x04040200
+
+	.long	0x080, 	0x00005000	@ CTRL
+	.long	0x090, 	0x00100010
+	.long	0x0F0, 	0xC0000000
+	.long	0x1A0, 	0x20C0C409
+	.long	0x280, 	0x01010101
+	.long	0x760, 	0x00000201
+	.long	0x770, 	0x0100000A
+	.long	0x780, 	0x00000133
+	.long	0x7B0, 	0x01010101
+	.long	0x7D0, 	0x0000000F
+	.long	0x7E0, 	0x00000000
+
+	.long	0x540, 	0x00000000	@ MCB
+	.long	0x570, 	0x00000001
+	.long	0x580, 	0x00000000
+	.long	0x590, 	0x00000000
+	.long	0x5A0, 	0x00000000
+	.long	0x5B0, 	0x00000000
+
+	.long	0x180, 	0x00000000	@ WRITE_PROTECTION
+
+	.long	0x210, 	0x00000000	@ __PHY Deskew PLL config and PHY initialization
+	.long	0x240, 	0x80000000
+
+	.long	0x10000000, 0x0		@ Pad drive strength auto calibration
+	.long	0x200,	0x00110000
+	.long	0x20000000, 0x0
+	.long	0x200,	0xfffeffff
+
+	.long	0x140, 	0x20004055
+	.long	0x1D0, 	0x17721869
+	.long	0x1E0, 	0x07700860
+	.long	0x1F0, 	0x00000086
+
+	.long	0x230, 	0xd0000040
+	.long	0xE10, 	0x00000040
+	.long	0xE20, 	0x00000040
+	.long	0xE30, 	0x00000040
+
+	.long	0x10000000, 0x0		@ DLL reset, Need this after any DCLK freq change
+	.long	0x240,	0x20000000
+	.long	0x20000000, 0x0
+	.long	0x240,	0xdfffffff
+
+	.long	0x40000000, 0x0
+	.long	0x240,	0x0
+
+	.long	0xE40, 	0x00000000
+	.long	0xE50, 	0x00000000
+
+	.long	0x120, 	0x03000001	@ initialize LPDDR2
+	.long	0x40000000, 0x0
+	.long	0x1b0,	0x0
+	.long	0x120, 	0x01001000
+	.long	0x120, 	0x02001000
+	.long	0x80000000, 0x0
+#elif (defined(CONFIG_DDR3_EPD_512M))
+a1_mmp2_epd512_ddr3:
+	.long	0x240, 	0x80000000
+	.long	0x10000000, 0x0
+	.long	0x230, 	0xf0000000
+	.long	0x240,	0x20000000
+	.long	0x240,	0x40000000
+	.long	0x120,	0x00000080
+	.long	0x10000000, 0x0
+	.long	0x80,	0x00000040
+	.long	0x120,	0x01000100
+	.long	0x80000000, 0x0
+#else
+	#error	"please define ddr table"
+#endif
+
+freq_sram_end:
+	nop
diff --git a/drivers/power/mmp_freq.c b/drivers/power/mmp_freq.c
new file mode 100644
index 0000000000..9da698bb7e
--- /dev/null
+++ b/drivers/power/mmp_freq.c
@@ -0,0 +1,2055 @@
+/*
+ *  U-Boot command for frequency change support
+ *
+ *  Copyright (C) 2008, 2009 Marvell International Ltd.
+ *  All Rights Reserved
+ *  Ning Jiang <ning.jiang@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include "ddr.h"
+#include <i2c.h>
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifndef CONFIG_MACH_MMP2
+
+#if defined(CONFIG_MACH_ABILENE)
+
+struct platform_ddr_setting ddr_setting[] = {
+	{
+		.ddr_freq = 400,
+		.setting = {
+			.reg1 = 0x911403CF,
+			.reg2 = 0x64660414,
+			.reg3 = 0xC2003053,
+			.reg4 = 0x34F4A187,
+			.reg5 = 0x000F20C1,
+			.reg6 = 0x04040200,
+			.reg7 = 0x00005501,
+		},
+	},
+	{
+		.ddr_freq = 531,
+		.setting = {
+			.reg1 = 0x911B03CF,
+			.reg2 = 0x74780564,
+			.reg3 = 0xC200406C,
+			.reg4 = 0x3694DA09,
+			.reg5 = 0x00142101,
+			.reg6 = 0x04040200,
+			.reg7 = 0x00006601,
+		},
+	},
+};
+
+#elif defined(CONFIG_MACH_YELLOWSTONE)
+
+struct platform_ddr_setting ddr_setting[] = {
+	{
+		.ddr_freq = 400,
+		.setting = {
+			.reg1 = 0x911403CF,
+			.reg2 = 0x64660404,
+			.reg3 = 0xC2004453,
+			.reg4 = 0x34F4A187,
+			.reg5 = 0x000F20C1,
+			.reg6 = 0x04040200,
+			.reg7 = 0x00005501,
+		},
+	},
+	{
+		.ddr_freq = 531,
+		.setting = {
+			.reg1 = 0x911B03CF,
+			.reg2 = 0x84880564,
+			.reg3 = 0xC2004B6C,
+			.reg4 = 0x3694DA09,
+			.reg5 = 0x00142101,
+			.reg6 = 0x04040200,
+			.reg7 = 0x00006601,
+		},
+	},
+};
+
+#elif defined(CONFIG_MACH_MK2) || defined(CONFIG_MACH_ORCHID)
+
+struct platform_ddr_setting ddr_setting[] = {
+	{
+		.ddr_freq = 200,
+		.setting = {
+			.reg1 = 0x488E0232,
+			.reg2 = 0x524301A5,
+			.reg3 = 0x201C1C12,
+			.reg4 = 0x3012804F,
+			.reg5 = 0x0A0900A1,
+			.reg6 = 0x04040200,
+			.reg7 = 0x00005201,
+			.reg8 = 0x00000033,
+		},
+	},
+	{
+		.ddr_freq = 400,
+		.setting = {
+			.reg1 = 0x4CDA00C5,
+			.reg2 = 0x94860342,
+			.reg3 = 0x2000381B,
+			.reg4 = 0x3023009D,
+			.reg5 = 0x20110142,
+			.reg6 = 0x02424190,
+			.reg7 = 0x00005501,
+			.reg8 = 0x00000066,
+		},
+	},
+};
+
+#else
+#error "unknown machine for DFC.\n"
+#endif
+
+#endif
+
+#ifndef CONFIG_MACH_MMP2
+#define PLL1_DIV_BY_2		400
+#define PLL1			800
+#define PLL1_CLKOUT_P		1063
+#define PLL2			1066
+#define VCXO                    26
+#define REF_VOLT		1275
+#define STEP			6
+#define VHIGH			1299
+/* A1 MMP3 currently operates vcore above 1200mV*/
+#define VLOW			1299
+
+#define	PMUA_BASE		0xD4282800
+#define	PMUM_BASE		0xD4050000
+#define MCU1_BASE		0xd0000000
+#define MCU2_BASE		0xd0010000
+
+#define	PMUA_DM_CC_MOH		(PMUA_BASE+0x000C)
+#define	PMUA_DM2_CC_MOH		(PMUA_BASE+0x0158)
+#define	PMUA_DM_CC_SEA		(PMUA_BASE+0x0008)
+#define	PMUA_DM2_CC_SEA		(PMUA_BASE+0x0154)
+
+#define	PMUA_CC_MOH		(PMUA_BASE+0x0004)
+#define PMUA_CC2_MOH		(PMUA_BASE+0x0150)
+#define PMUA_CC3_MOH		(PMUA_BASE+0x0188)
+
+#define	PMUA_CC_SEA		(PMUA_BASE+0x0000)
+#define	PMUA_CC2_SEA		(PMUA_BASE+0x014c)
+
+#define	PMUA_PLL_SEL_STATUS	(PMUA_BASE+0x00C4)
+#define PMUA_CORE_STATUS	(PMUA_BASE+0x0090)
+
+#define	PMUA_MOH_IMR		(PMUA_BASE+0x0098)
+#define	PMUA_MOH_ISR		(PMUA_BASE+0x00A0)
+#define	PMUA_PJ_IRWC		(PMUA_BASE+0x009c)
+
+#define PMUM_CGR_SP		(PMUM_BASE+0x0024)
+#define PMUM_CGR_PJ		(PMUM_BASE+0x1024)
+
+#define PMUM_DEBUG_1		(PMUA_BASE+0x0088)
+#define PMUM_DEBUG_2		(PMUA_BASE+0x0190)
+
+#define	PMUM_PLL2CR		(PMUM_BASE+0x0034)
+#define	PMUM_PLL2CR1		(PMUM_BASE+0x0414)
+#define	PMUM_PLL2CR2		(PMUM_BASE+0x0418)
+#define	PMUM_PLL2CR3		(PMUM_BASE+0x041c)
+#define PMUM_PLL_DIFF_CNTRL	(PMUM_BASE+0x0068)
+#define PMUA_MC_SLP_REQ_PJ	(PMUA_BASE+0x00b4)
+#define PMUA_MC_PAR_CTRL	(PMUA_BASE+0x011c)
+#define PMUA_BUS_CLK_RES_CTRL	(PMUA_BASE+0x006c)
+#define	PMUM_FCCR		(PMUM_BASE+0x0008)
+
+struct operating_point {
+	int op_id;
+	u32 pclk;
+	u32 pclk_mm;
+	u32 baclk;
+	u32 dclk;
+	u32 dclk2;
+	u32 dclk_lp;
+	u32 dclk_ddr;
+	u32 aclk;
+	u32 aclk2;
+	u32 phclk;
+	u32 atclk;
+	u32 cp_pclk;
+	u32 cp_baclk;
+	u32 cp_clk_src;
+	u32 ap_clk_src;
+	u32 ddr_clk_src;
+	u32 ddr_clk_src_lp;
+	u32 ddr_clk_src_ddr;
+	u32 axi_clk_src;
+	u32 pll2freq;
+	u32 pll1clkoutp;
+	u32 pdclk;
+	u32 xpclk;
+	u32 cp_pdclk;
+	u32 gc_clk_src;
+	u32 vcore;
+};
+
+#define OP(p, pd, ba, xp, d, a, v) \
+	{			\
+	.pclk	= p,		\
+	.pdclk	= pd,		\
+	.baclk	= ba,		\
+	.xpclk	= xp,		\
+	.dclk	= d,		\
+	.aclk	= a,		\
+	.vcore	= v,		\
+	}
+
+#define OP_MMP3(p, pm, ba, dlp, dddr3, a1, a2, ph, at) \
+	{			\
+	.pclk = p,		\
+	.pclk_mm = pm,		\
+	.baclk	= ba,		\
+	.dclk = dlp,		\
+	.dclk_ddr3 = dddr3,	\
+	.aclk	= a1,		\
+	.aclk2	= a2,		\
+	.phclk = ph,		\
+	.atclk = at,		\
+	}
+
+struct operating_point pxa2128_op_array[] = {
+	{
+		.op_id = 0,
+		.pclk = 100,
+		.pclk_mm = 100,
+		.baclk = 100,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 200,
+		.aclk2 = 100,
+		.phclk = 1, /*6.5MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 1,
+		.pclk = 26,
+		.pclk_mm = 26,
+		.baclk = 50,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 50,
+		.aclk2 = 50,
+		.phclk = 1, /*6.5MHz*/
+		.atclk = 13,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = VCXO,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 2,
+		.pclk = 50,
+		.pclk_mm = 50,
+		.baclk = 50,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 100,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 3,
+		.pclk = 100,
+		.pclk_mm = 50,
+		.baclk = 50,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 100,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 4,
+		.pclk = 200,
+		.pclk_mm = 200,
+		.baclk = 200,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 200,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 5,
+		.pclk = 400,
+		.pclk_mm = 200,
+		.baclk = 400,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 6,
+		.pclk = 800,
+		.pclk_mm = 400,
+		.baclk = 400,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*200MHz*/
+		.atclk = 265,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 7,
+		.pclk = 531,
+		.pclk_mm = 265,
+		.baclk = 531,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 2, /*177MHz*/
+		.atclk = 354,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_CLKOUT_P,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 8,
+		.pclk = 1063,
+		.pclk_mm = 265,
+		.baclk = 531,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 2, /*177MHz*/
+		.atclk = 354,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_CLKOUT_P,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 9,/*PP 5_2*/
+		.pclk = 400,
+		.pclk_mm = 400,
+		.baclk = 400,
+		.dclk_lp = 200,
+		.dclk_ddr = 400,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1_DIV_BY_2,
+		.ddr_clk_src_ddr = PLL1,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = -1,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 10,
+		.pclk = 100,
+		.pclk_mm = 100,
+		.baclk = 100,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 200,
+		.aclk2 = 100,
+		.phclk = 1, /*6.5MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 11,
+		.pclk = 26,
+		.pclk_mm = 26,
+		.baclk = 50,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 50,
+		.aclk2 = 50,
+		.phclk = 1, /*6.5MHz*/
+		.atclk = 13,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = VCXO,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 12,
+		.pclk = 50,
+		.pclk_mm = 50,
+		.baclk = 50,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 100,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 13,
+		.pclk = 100,
+		.pclk_mm = 50,
+		.baclk = 50,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 100,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 14,
+		.pclk = 200,
+		.pclk_mm = 200,
+		.baclk = 200,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 200,
+		.aclk2 = 100,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 15,
+		.pclk = 400,
+		.pclk_mm = 200,
+		.baclk = 400,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VLOW,
+	},
+
+	{
+		.op_id = 16,
+		.pclk = 800,
+		.pclk_mm = 400,
+		.baclk = 400,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*200MHz*/
+		.atclk = 265,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = PLL2,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 17,
+		.pclk = 531,
+		.pclk_mm = 265,
+		.baclk = 531,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 2, /*177MHz*/
+		.atclk = 354,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_CLKOUT_P,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 18,
+		.pclk = 1063,
+		.pclk_mm = 265,
+		.baclk = 531,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 2, /*177MHz*/
+		.atclk = 354,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_CLKOUT_P,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+
+	{
+		.op_id = 19,/*PP 5_2*/
+		.pclk = 400,
+		.pclk_mm = 400,
+		.baclk = 400,
+		.dclk_lp = 400,
+		.dclk_ddr = 531,
+		.aclk = 400,
+		.aclk2 = 200,
+		.phclk = 1, /*100MHz*/
+		.atclk = 133,
+		.cp_pclk = 200,
+		.cp_baclk = 100,
+		.cp_clk_src = PLL1_DIV_BY_2,
+		.ap_clk_src = PLL1_DIV_BY_2,
+		.ddr_clk_src_lp = PLL1,
+		.ddr_clk_src_ddr = PLL1_CLKOUT_P,
+		.axi_clk_src = PLL1_DIV_BY_2,
+		.pll2freq = -1,
+		.pll1clkoutp = PLL1_CLKOUT_P,
+		.vcore = VHIGH,
+	},
+};
+
+/*struct operating_point pxa2128_op_array[] = {
+	pclk_mp pclk_mm bclk lp_dclk ddr3_dclk aclk1 aclk2 phclk atclk
+	OP_MMP3(100, 100, 100, 200, 200, 200, 100, 100, 133),
+	OP_MMP3(400, 400, 400, 400, 533, 400, 200, 200, 133),
+	OP_MMP3(400, 400, 400, 400, 533, 400, 200, 200, 133),
+	OP_MMP3(400, 400, 400, 400, 533, 400, 200, 200, 133),
+	OP_MMP3(400, 400, 400, 400, 533, 400, 200, 200, 133),
+	OP_MMP3(800, 400, 400, 400, 533, 400, 200, 200, 266),
+	OP_MMP3(1066, 533, 400, 400, 533, 400, 200, 176, 355),
+	OP_MMP3(531, 531, 531, 400, 531, 400, 200, 177, 354),
+	OP_MMP3(1063, 531, 531, 400, 531, 400, 200, 177, 354),
+};*/
+
+struct operating_point pxa920_op_array[] = {
+	/* pclk pdclk baclk xpclk  dclk  aclk vcore */
+	OP(156,   78,   78,  156,   78,   78, 1225), /* op0 */
+	OP(78,   39,   39,   78,   78,   78, 1225),
+	OP(156,   78,   78,  156,  104,  104, 1225),
+	OP(312,  156,  156,  312,  156,  156, 1225),
+	OP(624,  156,  156,  312,  156,  156, 1225),
+	OP(0,    0,    0,    0,    0,    0,    0), /* op5 */
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0), /* op10 */
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(806,  201,  201,  403,  201,  208, 1300),
+	OP(780,  195,  195,  390,  195,  208, 1300),
+	OP(801,  200,  200,  400,  200,  208, 1300), /* op15 */
+	OP(797,  199,  199,  398,  199,  208, 1300),
+	OP(936,  156,  156,  312,  156,  156, 1400),
+	OP(988,  164,  164,  329,  164,  197, 1400),
+};
+
+struct operating_point pxa921_op_array[] = {
+	/* pclk pdclk baclk xpclk  dclk  aclk vcore */
+	OP(156,   78,   78,  156,   78,   78, 1225), /* op0 */
+	OP(78,   39,   39,   78,   78,   78, 1225),
+	OP(156,  156,  156,  156,  156,  156, 1225),
+	OP(312,  156,  156,  312,  156,  156, 1225),
+	OP(500,  250,  250,  250,  250,  156, 1225),
+	OP(0,    0,    0,    0,    0,    0,    0), /* op5 */
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(1001, 250,  250,  500,  250,  208, 1350), /* op10 */
+};
+
+struct operating_point pxa910_op_array[] = {
+	/* pclk pdclk baclk xpclk  dclk  aclk vcore */
+	OP(156,   78,   78,  156,   78,   78, 1225), /* op0 */
+	OP(78,   39,   39,   78,   78,   78, 1225),
+	OP(208,  104,  104,  104,  104,  104, 1225),
+	OP(312,  156,  156,  156,  156,  156, 1225),
+	OP(624,  156,  156,  312,  156,  156, 1225),
+	OP(0,    0,    0,    0,    0,    0,    0), /* op5 */
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0), /* op10 */
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(0,    0,    0,    0,    0,    0,    0),
+	OP(806,  201,  201,  403,  201,  208, 1300),
+	OP(780,  195,  195,  390,  195,  208, 1300),
+	OP(801,  200,  200,  400,  200,  208, 1300), /* op15 */
+	OP(797,  199,  199,  398,  199,  208, 1300),
+	OP(936,  156,  156,  312,  156,  156, 1400),
+	OP(988,  164,  164,  329,  164,  197, 1400),
+};
+
+union pmum_pll2cr1 {
+	struct {
+		unsigned int reserved0:8;
+		unsigned int en:1;
+		unsigned int ctrl:1;
+		unsigned int pll2fbd:9;
+		unsigned int pll2refd:5;
+		unsigned int reserved2:8;
+	} b;
+	unsigned int v;
+};
+
+union pmua_pllsel1 {
+	struct {
+		unsigned int cpclksel:3;
+		unsigned int apclksel:3;
+		unsigned int ddrclksel:3;
+		unsigned int axiclksel:3;
+		unsigned int reserved0:20;
+	} b;
+	unsigned int v;
+};
+
+union pmum_fccr1 {
+	struct {
+		unsigned int pll1fbd:9;
+		unsigned int pll1refd:5;
+		unsigned int pll1cen:1;
+		unsigned int mfc:1;
+		unsigned int pll1_mfc_rst_time:2;
+		unsigned int rsrvd:5;
+		unsigned int ddrclksel:3;
+		unsigned int seaclksel:3;
+		unsigned int mohclksel:3;
+	} b;
+	unsigned int v;
+};
+
+union pmua_bus_clk_ctrl1 {
+	struct {
+		unsigned int mc_rst:1;
+		unsigned int mc2_rst:1;
+		unsigned int rsrvd1:4;
+		unsigned int saxi_clk_sel:3;
+		unsigned int ddr2clksel:3;
+		unsigned int rsrvd:20;
+	} b;
+	unsigned int v;
+};
+
+union pmua_cc1 {
+	struct {
+		unsigned int core_clk_div:3;
+		unsigned int atclk_div:3;
+		unsigned int rsrvd3:3;
+		unsigned int phclk_div:3;
+		unsigned int ddr_clk_div:3;
+		unsigned int soc_axi_clk_div:3;
+		unsigned int rsrvd2:4;
+		unsigned int ddr2_freq_chg_req:1;
+		unsigned int rsrvd1:1;
+		unsigned int sp_freq_chg_req:1;
+		unsigned int ddr_freq_chg_req:1;
+		unsigned int saxi_freq_chg_req:1;
+		unsigned int core_allow_spd_chg:1;
+		unsigned int rsrvd:3;
+		unsigned int core_rd_st_clear:1;
+	} b;
+	unsigned int v;
+};
+
+union pmua_cc2_sp1 {
+	struct {
+		unsigned int saxi2_clk_div:3;
+		unsigned int rsrvd1:6;
+		unsigned int ddr_clk2_div:3;
+		unsigned int rsrvd:20;
+	} b;
+	unsigned int v;
+};
+
+union pmua_cc2_pj1 {
+	struct {
+		unsigned int saxi_clk2_div:3;
+		unsigned int rsrvd3:6;
+		unsigned int mp1_pclken_div:4;
+		unsigned int mp2_pclken_div:4;
+		unsigned int mm_pclken_div:4;
+		unsigned int aclken_div:4;
+		unsigned int mp2_sw_rstn:1;
+		unsigned int mm_sw_rstn:1;
+		unsigned int phclk_en:1;
+		unsigned int mp1_pclken_dis:1;
+		unsigned int mp2_pclken_dis:1;
+		unsigned int mm_pclken_dis:1;
+		unsigned int pj_force_pclkon:1;
+	} b;
+	unsigned int v;
+};
+
+union pmua_cc3_pj1 {
+	struct {
+		unsigned int rst_mp1_wdog:1;
+		unsigned int rst_mp2_wdog:1;
+		unsigned int rst_mm_wdog:1;
+		unsigned int timer_sw_rst:1;
+		unsigned int timer_clken:1;
+		unsigned int rsrvd:3;
+		unsigned int timer_clk_ratio:5;
+		unsigned int preset_atresetn:1;
+		unsigned int mp1_wd_rst_mask:1;
+		unsigned int mp2_wd_rst_mask:1;
+		unsigned int mm_wd_rst_mask:1;
+		unsigned int ddr_clk2_div:3;
+		unsigned int atclk_pclkdg_rtio:5;
+		unsigned int rsrvd1:7;
+	} b;
+	unsigned int v;
+};
+
+union pmua_dm_cc1 {
+	struct {
+		unsigned int core_clk_div:3;
+		unsigned int at_clk_div:3;
+		unsigned int rsrvd1:3;
+		unsigned int ddr_clk2_div:3;
+		unsigned int ddr_clk_div:3;
+		unsigned int soc_axi_clk_div:3;
+		unsigned int rsrvd:6;
+		unsigned int sea_rd_status:1;
+		unsigned int moh_rd_status:1;
+		unsigned int reserved:6;
+	} b;
+	unsigned int v;
+};
+
+union pmua_dm2_cc_pj1 {
+	struct {
+		unsigned int soc_axi2_div:3;
+		unsigned int rsrvd:6;
+		unsigned int mp1_pclen_div:4;
+		unsigned int mp2_pclen_div:4;
+		unsigned int mm_pclen_div:4;
+		unsigned int aclken_div:4;
+		unsigned int periphclk_div:3;
+		unsigned int reserved:4;
+	} b;
+	unsigned int v;
+};
+
+union pmua_dm2_cc_sp1 {
+	struct {
+		unsigned int reserved:29;
+		unsigned int soc_axi2_div:3;
+	} b;
+	unsigned int v;
+};
+
+#define CLK_SRC_VCTCXO		(1u<<0)
+#define CLK_SRC_PLL1_312	(1u<<1)
+#define CLK_SRC_PLL1_624	(1u<<2)
+#define CLK_SRC_PLL2		(1u<<3)
+#define CLK_SRC_PCLKOUT_P	(1u<<4)
+
+
+static int fc_lock_ref_cnt;
+
+static void get_fc_lock(void)
+{
+	union pmua_dm_cc1 dm_cc_ap;
+
+	fc_lock_ref_cnt++;
+
+	if (fc_lock_ref_cnt == 1) {
+		int timeout = 100000;
+		/* AP-CP FC mutual exclusion */
+		dm_cc_ap.v = __raw_readl(PMUA_DM_CC_MOH);
+		while (dm_cc_ap.b.sea_rd_status && timeout) {
+			dm_cc_ap.v = __raw_readl(PMUA_DM_CC_MOH);
+			timeout--;
+		}
+		if (timeout <= 0)
+			printf("cp does not release its fc lock\n");
+	}
+}
+
+static void put_fc_lock(void)
+{
+	union pmua_cc1 cc_ap;
+
+	fc_lock_ref_cnt--;
+
+	if (fc_lock_ref_cnt < 0)
+		printf("unmatched put_fc_lock\n");
+
+	if (fc_lock_ref_cnt == 0) {
+		/* write 1 to MOH_RD_ST_CLEAR to clear MOH_RD_STATUS */
+		cc_ap.v = __raw_readl(PMUA_CC_MOH);
+		cc_ap.b.core_rd_st_clear = 1;
+		__raw_writel(cc_ap.v, PMUA_CC_MOH);
+		cc_ap.b.core_rd_st_clear = 0;
+		__raw_writel(cc_ap.v, PMUA_CC_MOH);
+	}
+}
+/*Turning all the clocks, AIB clocks and programing debug
+*registers
+*/
+
+void freq_change_prep(void)
+{
+	__raw_writel(0x1, PMUM_DEBUG_1);
+	__raw_writel(0x0, PMUM_DEBUG_2);
+	__raw_writel(0x0818E23E, PMUM_CGR_SP);
+	__raw_writel(0x0818E23E, PMUM_CGR_PJ);
+}
+
+static u32 get_pll2_freq(void)
+{
+	union pmum_pll2cr1 pll2cr;
+
+	pll2cr.v = __raw_readl(PMUM_PLL2CR);
+	if ((pll2cr.b.ctrl == 1) && (pll2cr.b.en == 0))
+		return 0;
+	return 13 * pll2cr.b.pll2fbd / pll2cr.b.pll2refd;
+}
+
+#if 0
+static void turn_off_pll2(void)
+{
+	union pmum_pll2cr1 pll2cr;
+
+	pll2cr.v = __raw_readl(PMUM_PLL2CR);
+	pll2cr.b.ctrl = 1; /* Let SW control PLL2 */
+	pll2cr.b.en = 0;   /* disable PLL2 by en bit */
+	__raw_writel(pll2cr.v, PMUM_PLL2CR);
+}
+#endif
+
+void turn_on_pll2(u32 pll2freq)
+{
+	union pmum_pll2cr1 pll2cr;
+	u32 pll2cr2;
+	pll2cr.v = 0;
+	pll2cr.b.pll2refd = 3;
+	pll2cr.b.pll2fbd = (2*pll2freq*pll2cr.b.pll2refd)/26;
+	pll2cr.b.ctrl = 1;
+
+	__raw_writel(pll2cr.v, PMUM_PLL2CR);
+	__raw_writel(0x05310599, PMUM_PLL2CR1);
+
+	pll2cr2 = __raw_readl(PMUM_PLL2CR2);
+	__raw_writel(pll2cr2 | 1, PMUM_PLL2CR2);
+
+	__raw_writel(0x25310599, PMUM_PLL2CR1);
+
+	udelay(200);
+
+	pll2cr.b.en = 1;
+	__raw_writel(pll2cr.v, PMUM_PLL2CR);
+
+	udelay(200);
+	printf("PLL2 is initialized at %dMHz\n", pll2freq);
+}
+
+static unsigned int to_clk_src(unsigned int sel, u32 pll2freq)
+{
+	unsigned int clk = 0;
+
+	switch (sel) {
+	case 0:
+		clk = PLL1_DIV_BY_2;
+		break;
+	case 1:
+		clk = PLL1;
+		break;
+	case 2:
+		clk = pll2freq;
+		break;
+	case 3:
+		clk = PLL1_CLKOUT_P;
+		break;
+	case 4:
+		clk = 26;
+		break;
+	default:
+		printf("Wrong clock source\n");
+		break;
+	}
+
+	/*printf("clock source was: %u\n",clk);*/
+	return clk;
+}
+
+static void get_current_op(struct operating_point *cop)
+{
+	union pmua_pllsel1 pllsel;
+	union pmua_dm_cc1 dm_cc_cp, dm_cc_ap;
+	union pmua_dm2_cc_pj1 dm2_cc_ap;
+	union pmua_dm2_cc_sp1 dm2_cc_cp;
+	u32 temp = 0;
+
+	u32 ddr_type = __raw_readl(MCU1_BASE + SDRAM_CTRL4) & 0x0000001C;
+
+	get_fc_lock();
+	dm_cc_ap.v = __raw_readl(PMUA_DM_CC_MOH);
+	dm_cc_cp.v = __raw_readl(PMUA_DM_CC_SEA);
+	dm2_cc_ap.v = __raw_readl(PMUA_DM2_CC_MOH);
+	dm2_cc_cp.v = __raw_readl(PMUA_DM2_CC_SEA);
+	pllsel.v = __raw_readl(PMUA_PLL_SEL_STATUS);
+
+	cop->pll2freq = get_pll2_freq();
+	cop->ap_clk_src = to_clk_src(pllsel.b.apclksel, cop->pll2freq);
+	cop->cp_clk_src = to_clk_src(pllsel.b.cpclksel, cop->pll2freq);
+	cop->axi_clk_src = to_clk_src(pllsel.b.axiclksel, cop->pll2freq);
+	cop->ddr_clk_src = to_clk_src(pllsel.b.ddrclksel, cop->pll2freq);
+
+	temp = cop->ap_clk_src/(dm_cc_ap.b.core_clk_div + 1);
+	cop->pclk = temp / (dm2_cc_ap.b.mp1_pclen_div + 1);
+	cop->pclk_mm = temp / (dm2_cc_ap.b.mm_pclen_div + 1);
+	cop->baclk = temp / (dm2_cc_ap.b.aclken_div + 1);
+	cop->cp_pclk = cop->cp_clk_src/(dm_cc_cp.b.core_clk_div+1);
+
+	if (ddr_type == DDR3) {
+		cop->dclk_ddr = cop->ddr_clk_src/(dm_cc_ap.b.ddr_clk_div + 1)/2;
+		temp = cop->dclk_ddr;
+	} else {
+		cop->dclk_lp = cop->ddr_clk_src/(dm_cc_ap.b.ddr_clk_div + 1)/2;
+		temp = cop->dclk_lp;
+	}
+
+	cop->aclk = cop->axi_clk_src/(dm_cc_ap.b.soc_axi_clk_div + 1);
+	cop->aclk2 = cop->axi_clk_src/(dm2_cc_ap.b.soc_axi2_div + 1);
+
+	#ifdef MMP3_DFC_DEBUG
+	printf("dm_cc_ap.b.core_clk_div: %u\n", dm_cc_ap.b.core_clk_div);
+	printf("dm2_cc_ap.b.mp1_pclen_div: %u\n", dm2_cc_ap.b.mp1_pclen_div);
+	printf("dm2_cc_ap.b.mm_pclen_div: %u\n", dm2_cc_ap.b.mm_pclen_div);
+	printf("dm2_cc_ap.b.aclken_div: %u\n", dm2_cc_ap.b.aclken_div);
+	printf("cop->pclk: %u and cop->baclk :%u\n", cop->pclk, cop->baclk);
+	printf("DDR: %u and current op->aclk:"
+	"%u, current op->aclk2: %u\n", temp,
+	cop->aclk, cop->aclk2);
+	#endif
+
+	put_fc_lock();
+}
+/*
+static void set_ap_clk_sel(struct operating_point *top)
+{
+	union pmum_fccr1 fccr;
+
+	fccr.v = __raw_readl(PMUM_FCCR);
+	if (top->ap_clk_src == 312)
+		fccr.b.mohclksel = 0;
+	else if (top->ap_clk_src == 624)
+		fccr.b.mohclksel = 1;
+	else if (top->ap_clk_src == top->pll2freq)
+		fccr.b.mohclksel = 2;
+	else if (top->ap_clk_src == 26)
+		fccr.b.mohclksel = 3;
+	__raw_writel(fccr.v, PMUM_FCCR);
+}
+
+static void set_axi_clk_sel(struct operating_point *top)
+{
+	union pmum_fccr1 fccr;
+
+	fccr.v = __raw_readl(PMUM_FCCR);
+	if (top->axi_clk_src == 312) {
+		fccr.b.axiclksel1 = 0;
+		fccr.b.axiclksel0 = 0;
+	} else if (top->axi_clk_src == 624) {
+		fccr.b.axiclksel1 = 0;
+		fccr.b.axiclksel0 = 1;
+	} else if (top->axi_clk_src == top->pll2freq) {
+		fccr.b.axiclksel1 = 1;
+		fccr.b.axiclksel0 = 0;
+	} else if (top->axi_clk_src == 26) {
+		fccr.b.axiclksel1 = 1;
+		fccr.b.axiclksel0 = 1;
+	}
+	__raw_writel(fccr.v, PMUM_FCCR);
+}
+
+static void set_ddr_clk_sel(struct operating_point *top)
+{
+	union pmum_fccr1 fccr;
+
+	fccr.v = __raw_readl(PMUM_FCCR);
+	if (top->ddr_clk_src == 312)
+		fccr.b.ddrclksel = 0;
+	else if (top->ddr_clk_src == 624)
+		fccr.b.ddrclksel = 1;
+	else if (top->ddr_clk_src == top->pll2freq)
+		fccr.b.ddrclksel = 2;
+	else if (top->ddr_clk_src == 26)
+		fccr.b.ddrclksel = 3;
+	__raw_writel(fccr.v, PMUM_FCCR);
+}
+*/
+
+static void enable_fc_intr(void)
+{
+	u32 fc_int_msk;
+
+	fc_int_msk = __raw_readl(PMUA_MOH_IMR);
+	fc_int_msk &= ~(0xfff);
+	/* fc_int_msk |= (7<<3); */
+	/*
+	 * enable AP FC done interrupt for one step,
+	 * while not use three interrupts by three steps
+	 */
+	fc_int_msk |= (1<<3);
+	fc_int_msk |= (1<<4);
+	fc_int_msk |= (1<<5);
+	__raw_writel(fc_int_msk, PMUA_MOH_IMR);
+}
+
+static void wait_for_fc_done(void)
+{
+	int timeout = 1000000;
+	u32 check = __raw_readl(PMUA_MOH_ISR);
+	u32 temp = 0x8;
+
+	while ((!(temp & check)) && timeout) {
+		check = __raw_readl(PMUA_MOH_ISR);
+		timeout--;
+	}
+	if (timeout <= 0)
+		panic("AP frequency change timeout!\n");
+	__raw_writel(0x1fff, PMUA_MOH_ISR);
+	__raw_writel(0x0, PMUA_MOH_ISR);
+	__raw_writel(0x0, PMUA_MOH_IMR);
+	udelay(1000);
+}
+
+/*
+static void wait_for_ap_fc_done(void)
+{
+	while (!((1<<3) & __raw_readl(PMUA_MOH_ISR)))
+		;
+	__raw_writel(0x0, PMUA_MOH_ISR);
+}
+
+static void wait_for_axi_fc_done(void)
+{
+	while (!((1<<5) & __raw_readl(PMUA_MOH_ISR)))
+		;
+	__raw_writel(0x0, PMUA_MOH_ISR);
+}
+
+static void wait_for_ddr_fc_done(void)
+{
+	while (!((1<<4) & __raw_readl(PMUA_MOH_ISR)))
+
+		;
+	__raw_writel(0x0, PMUA_MOH_ISR);
+}
+*/
+
+#define debug_wt_reg(val, reg)						\
+do {									\
+	__raw_writel(val, reg);						\
+	/*printf(" %08x ==> [%x]\n", val, reg);*/				\
+} while (0)
+
+#define _insert_tbl(tbl_num, tbl_entry, base, reg, data, pause, end)	\
+do {									\
+	int tmp = 0;							\
+	debug_wt_reg(data, base + REGISTER_TABLE_DATA_0);		\
+	tmp |= reg;							\
+	if (pause)							\
+		tmp |= (1 << 16);					\
+	if (end)							\
+		tmp |= (1 << 17);					\
+	debug_wt_reg(tmp, base + REGISTER_TABLE_DATA_1);		\
+	tmp = (1 << 31);						\
+	tmp |= (tbl_num << 5);						\
+	tmp |= tbl_entry;						\
+	debug_wt_reg(tmp, base + REGISTER_TABLE_CTRL_0);		\
+	tbl_entry++;							\
+} while (0)
+
+#define tbl_add_com(num, ent, base, reg, data) \
+	_insert_tbl(num, ent, base, reg, data, 0, 0)
+#define tbl_add_pop(num, ent, base, reg, data) \
+	_insert_tbl(num, ent, base, reg, data, 1, 0)
+#define tbl_add_eop(num, ent, base, reg, data) \
+	_insert_tbl(num, ent, base, reg, data, 1, 1)
+
+static void mc4_prgm_tble_lpddr_h2l(u32 base, struct ddr_timing *timing)
+{
+	u32 entry = 0, data;
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL14, 0x2);	/* halt mc4 scheduler */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL4,
+		__raw_readl(base + SDRAM_CTRL4));	/* cas latency */
+	tbl_add_com(0, entry, base, SDRAM_TIMING1, timing->reg1);
+	tbl_add_com(0, entry, base, SDRAM_TIMING2, timing->reg2);
+	tbl_add_com(0, entry, base, SDRAM_TIMING3, timing->reg3);
+	tbl_add_com(0, entry, base, SDRAM_TIMING4, timing->reg4);
+	tbl_add_com(0, entry, base, SDRAM_TIMING5, timing->reg5);
+	tbl_add_com(0, entry, base, SDRAM_TIMING6, timing->reg6);
+	tbl_add_com(0, entry, base, SDRAM_TIMING7, timing->reg7);
+	tbl_add_com(0, entry, base, SDRAM_TIMING8, timing->reg8);
+
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x20000000);	/* reset master dll */
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x40000000);	/* update master dll */
+	tbl_add_pop(0, entry, base, PHY_CTRL14, 0x80000000);	/* sync 2x clk */
+
+	data = __raw_readl(base + SDRAM_CTRL1) | (0x40);
+	tbl_add_com(0, entry, base, SDRAM_CTRL1, data);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x03001000);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020001);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020002);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020003);
+	tbl_add_eop(0, entry, base, SDRAM_CTRL14, 0x0);
+}
+
+static void mc4_prgm_tble_lpddr_l2h(u32 base, struct ddr_timing *timing)
+{
+	u32 entry = 0, data;
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL14, 0x2);	/* halt mc4 scheduler */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL4,
+		__raw_readl(base + SDRAM_CTRL4));	/* cas latency */
+	tbl_add_com(0, entry, base, SDRAM_TIMING1, timing->reg1);
+	tbl_add_com(0, entry, base, SDRAM_TIMING2, timing->reg2);
+	tbl_add_com(0, entry, base, SDRAM_TIMING3, timing->reg3);
+	tbl_add_com(0, entry, base, SDRAM_TIMING4, timing->reg4);
+	tbl_add_com(0, entry, base, SDRAM_TIMING5, timing->reg5);
+	tbl_add_com(0, entry, base, SDRAM_TIMING6, timing->reg6);
+	tbl_add_com(0, entry, base, SDRAM_TIMING7, timing->reg7);
+	tbl_add_pop(0, entry, base, SDRAM_TIMING8, timing->reg8);
+
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x20000000);	/* reset master dll */
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x40000000);	/* update master dll */
+	tbl_add_pop(0, entry, base, PHY_CTRL14, 0x80000000);	/* sync 2x clk */
+
+	data = __raw_readl(base + SDRAM_CTRL1) | (0x40);
+	tbl_add_com(0, entry, base, SDRAM_CTRL1, data);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x03001000);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020001);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020002);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND1, 0x03020003);
+	tbl_add_eop(0, entry, base, SDRAM_CTRL14, 0x0);
+}
+
+static void mc4_prgm_tble_ddr3_h2l(u32 base, struct ddr_timing *timing)
+{
+	u32 entry = 0, data;
+
+	tbl_add_pop(0, entry, base, SDRAM_CTRL14, 0x2);	/* halt mc4 scheduler */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL4,
+		__raw_readl(base + SDRAM_CTRL4));	/* cas latency */
+	tbl_add_com(0, entry, base, SDRAM_TIMING1, timing->reg1);
+	tbl_add_com(0, entry, base, SDRAM_TIMING2, timing->reg2);
+	tbl_add_com(0, entry, base, SDRAM_TIMING3, timing->reg3);
+	tbl_add_com(0, entry, base, SDRAM_TIMING4, timing->reg4);
+	tbl_add_com(0, entry, base, SDRAM_TIMING5, timing->reg5);
+	tbl_add_com(0, entry, base, SDRAM_TIMING6, timing->reg6);
+	tbl_add_com(0, entry, base, SDRAM_TIMING7, timing->reg7);
+
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x20000000);	/* reset master dll */
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x40000000);	/* update master dll */
+	tbl_add_pop(0, entry, base, PHY_CTRL14, 0x80000000);	/* sync 2x clk */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL14, 0x2);
+	data = __raw_readl(base + SDRAM_CTRL1) & ~(0x40);
+	tbl_add_com(0, entry, base, SDRAM_CTRL1, data);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x01000100);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x01000400);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x01001000);
+	tbl_add_eop(0, entry, base, SDRAM_CTRL14, 0x0);
+}
+
+static void mc4_prgm_tble_ddr3_l2h(u32 base, struct ddr_timing *timing)
+{
+	u32 entry = 0, data;
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL14, 0x2);	/* halt mc4 scheduler */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL4,
+		__raw_readl(base + SDRAM_CTRL4));	/* cas latency */
+	tbl_add_com(0, entry, base, SDRAM_TIMING1, timing->reg1);
+	tbl_add_com(0, entry, base, SDRAM_TIMING2, timing->reg2);
+	tbl_add_com(0, entry, base, SDRAM_TIMING3, timing->reg3);
+	tbl_add_com(0, entry, base, SDRAM_TIMING4, timing->reg4);
+	tbl_add_com(0, entry, base, SDRAM_TIMING5, timing->reg5);
+	tbl_add_com(0, entry, base, SDRAM_TIMING6, timing->reg6);
+	tbl_add_pop(0, entry, base, SDRAM_TIMING7, timing->reg7);
+
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x20000000);	/* reset master dll */
+	tbl_add_com(0, entry, base, PHY_CTRL14, 0x40000000);	/* update master dll */
+	tbl_add_pop(0, entry, base, PHY_CTRL14, 0x80000000);	/* sync 2x clk */
+
+	tbl_add_com(0, entry, base, SDRAM_CTRL14, 0x2);
+	data = __raw_readl(base + SDRAM_CTRL1) | (0x40);
+	tbl_add_com(0, entry, base, SDRAM_CTRL1, data);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x03000100);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x03000400);
+	tbl_add_com(0, entry, base, USER_INITIATED_COMMAND0, 0x03001000);
+	tbl_add_eop(0, entry, base, SDRAM_CTRL14, 0x0);
+}
+
+void mc4_fc_prgm_tble_seq(u32 base, u32 crnt_frq, u32 nxt_frq, int dtyp)
+{
+
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(ddr_setting); i++) {
+		if (nxt_frq == ddr_setting[i].ddr_freq)
+			break;
+	}
+
+	if (i == ARRAY_SIZE(ddr_setting)) {
+		printf("ddr freq do not support, should not run here!\n");
+		return;
+	}
+
+	if (dtyp == DDR3) {
+		if (crnt_frq > nxt_frq) {
+			mc4_prgm_tble_ddr3_h2l(base, &ddr_setting[i].setting);
+		} else {
+			mc4_prgm_tble_ddr3_l2h(base, &ddr_setting[i].setting);
+		}
+	}
+
+	if (dtyp == LPDDR2) {
+		if (crnt_frq > nxt_frq) {
+			mc4_prgm_tble_lpddr_h2l(base, &ddr_setting[i].setting);
+		} else {
+			mc4_prgm_tble_lpddr_l2h(base, &ddr_setting[i].setting);
+		}
+	}
+
+	return;
+}
+
+void ddr_fc_program_table(unsigned int base, unsigned int current_freq,
+				unsigned int next_freq, u32 ddr_type)
+{
+	u32 temp = __raw_readl(PMUA_MC_SLP_REQ_PJ);
+
+	mc4_fc_prgm_tble_seq(base, current_freq, next_freq, ddr_type);
+
+	if (base == MCU1_BASE)
+		temp &= ~(0x30);
+	else
+		temp &= ~(0xc0);
+
+	if (ddr_type == DDR3) {
+		if (current_freq < next_freq) {
+			if (base == MCU1_BASE)
+				temp |= 0x30;
+			else
+				temp |= 0xc0;
+		} else {
+			if (base == MCU1_BASE)
+				temp |= 0x20;
+			else
+				temp |= 0x80;
+		}
+	} else {
+		if (current_freq < next_freq)
+			temp |= 0x50;
+		else
+			temp |= 0x0;
+	}
+
+	__raw_writel(temp, PMUA_MC_SLP_REQ_PJ);
+}
+
+void allow_speed_change(int i)
+{
+	union pmua_cc1 cc_ap;
+
+	cc_ap.v = __raw_readl(PMUA_CC_MOH);
+	cc_ap.b.core_allow_spd_chg = i;
+	__raw_writel(cc_ap.v, PMUA_CC_MOH);
+}
+
+static void PMUcore2_fc_seq(struct operating_point *cop,
+	struct operating_point *top)
+{
+	union pmua_cc1 cc_ap;
+	union pmua_cc2_pj1 cc2_ap;
+	union pmua_cc3_pj1 cc3_ap;
+	union pmum_fccr1 fccr;
+	union pmua_bus_clk_ctrl1 bus_clk_ctrl;
+
+	int coreFlag = 0;
+	int axiFlag = 0;
+	int ddrFlag = 0;
+	u32 ddr_type = 0;
+	u32 dclk2x;
+	u32 temp, temp1, ddr_src;
+
+#ifdef CONFIG_MMP3_DVC
+	if (top->vcore > cop->vcore) {
+		if (set_volt(top->vcore) == 0)
+			printf("Voltage is changed to: %dmV\n", top->vcore);
+		else
+			printf("Voltage change was unsuccessful\n");
+	}
+#endif
+
+	ddr_type = __raw_readl(MCU1_BASE + SDRAM_CTRL4) & 0x0000001C;
+	printf("DDR Type: %s\n", (ddr_type == DDR3) ? "DDR3" : "LPDDR");
+
+	if (ddr_type == DDR3)
+		dclk2x = top->dclk_ddr * 2;
+	else
+		dclk2x = top->dclk_lp * 2;
+
+	__raw_writel(0x04, PMUA_MC_PAR_CTRL);
+
+	bus_clk_ctrl.v = __raw_readl(PMUA_BUS_CLK_RES_CTRL);
+	fccr.v = __raw_readl(PMUM_FCCR);
+	cc_ap.v = __raw_readl(PMUA_CC_MOH);
+	cc2_ap.v = __raw_readl(PMUA_CC2_MOH);
+	cc3_ap.v = __raw_readl(PMUA_CC3_MOH);
+
+	if (cop->pll2freq != PLL2 && top->pll2freq == PLL2)
+		turn_on_pll2(top->pll2freq);
+	if (cop->pll1clkoutp != PLL1_CLKOUT_P &&
+		top->pll1clkoutp == PLL1_CLKOUT_P)
+			__raw_writel(0x011, PMUM_PLL_DIFF_CNTRL);
+
+	cc_ap.b.rsrvd = 0;
+	cc_ap.b.rsrvd1 = 1;
+	cc_ap.b.rsrvd2 = (1 << 3) | (1 << 2) | (1 << 1) | (1 << 0);
+	cc_ap.b.rsrvd3 = 3;
+	cc2_ap.b.rsrvd3 = 0;
+	fccr.b.rsrvd = 0;
+	bus_clk_ctrl.b.rsrvd = 0;
+	bus_clk_ctrl.b.rsrvd1 = 0;
+
+	cc_ap.b.atclk_div = top->ap_clk_src / top->atclk - 1;
+	cc_ap.b.phclk_div = top->phclk;
+	cc_ap.b.core_allow_spd_chg = 0;
+
+	if (ddr_type == DDR3) {
+		temp1 = top->dclk_ddr;
+		temp = cop->dclk_ddr;
+		ddr_src = top->ddr_clk_src_ddr;
+	} else {
+		temp1 = top->dclk_lp;
+		temp = cop->dclk_lp;
+		ddr_src = top->ddr_clk_src_lp;
+	}
+
+	if (temp != temp1) {
+
+		if (ddr_src == PLL1) {
+			fccr.b.ddrclksel = 1;
+			bus_clk_ctrl.b.ddr2clksel = 1;
+			cc_ap.b.ddr_clk_div = (ddr_src / dclk2x) - 1;
+			cc3_ap.b.ddr_clk2_div = (ddr_src / dclk2x) - 1;
+		}
+		if (ddr_src == PLL1_DIV_BY_2) {
+			fccr.b.ddrclksel = 0;
+			bus_clk_ctrl.b.ddr2clksel = 0;
+			cc_ap.b.ddr_clk_div = (ddr_src / dclk2x) - 1;
+			cc3_ap.b.ddr_clk2_div = (ddr_src / dclk2x) - 1;
+		}
+		if (ddr_src == PLL1_CLKOUT_P) {
+			fccr.b.ddrclksel = 3;
+			bus_clk_ctrl.b.ddr2clksel = 3;
+			cc_ap.b.ddr_clk_div = (ddr_src / dclk2x) - 1;
+			cc3_ap.b.ddr_clk2_div = (ddr_src / dclk2x) - 1;
+		}
+		if (ddr_src == PLL2) {
+			fccr.b.ddrclksel = 2;
+			bus_clk_ctrl.b.ddr2clksel = 2;
+			cc_ap.b.ddr_clk_div = (ddr_src / dclk2x) - 1;
+			cc3_ap.b.ddr_clk2_div = (ddr_src / dclk2x) - 1;
+		}
+		if (ddr_src == VCXO) {
+			fccr.b.ddrclksel = 4;
+			bus_clk_ctrl.b.ddr2clksel = 4;
+			cc_ap.b.ddr_clk_div = (ddr_src / dclk2x) - 1;
+			cc3_ap.b.ddr_clk2_div = (ddr_src / dclk2x) - 1;
+		}
+		cc_ap.b.ddr_freq_chg_req = 1;
+		cc_ap.b.ddr2_freq_chg_req = 1;
+		ddrFlag = 1;
+	}
+
+	/* as part of work around for silicon bug
+	*  we are triggering core freq change if ddrFlag is set
+	*/
+	if (cop->pclk != top->pclk || cop->pclk_mm != top->pclk_mm) {
+
+		if (top->ap_clk_src == PLL1) {
+			fccr.b.mohclksel = 1;
+			cc_ap.b.core_clk_div = (top->ap_clk_src / top->pclk)
+						- 1;
+			temp = PLL1 / (cc_ap.b.core_clk_div + 1);
+			cc2_ap.b.mp1_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mp2_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mm_pclken_div = (temp / top->pclk_mm) - 1;
+			cc2_ap.b.aclken_div = (temp / top->baclk) - 1;
+		}
+		if (top->ap_clk_src == PLL1_DIV_BY_2) {
+			fccr.b.mohclksel = 0;
+			cc_ap.b.core_clk_div = (top->ap_clk_src / top->pclk)
+						- 1;
+			temp = PLL1_DIV_BY_2 / (cc_ap.b.core_clk_div + 1);
+			cc2_ap.b.mp1_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mp2_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mm_pclken_div = (temp / top->pclk_mm) - 1;
+			cc2_ap.b.aclken_div = (temp / top->baclk) - 1;
+		}
+		if (top->ap_clk_src == PLL1_CLKOUT_P) {
+			fccr.b.mohclksel = 3;
+			cc_ap.b.core_clk_div = (top->ap_clk_src / top->pclk)
+						- 1;
+			temp = PLL1_CLKOUT_P / (cc_ap.b.core_clk_div + 1);
+			cc2_ap.b.mp1_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mp2_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mm_pclken_div = (temp / top->pclk_mm) - 1;
+			cc2_ap.b.aclken_div = (temp / top->baclk) - 1;
+		}
+		if (top->ap_clk_src == PLL2) {
+			fccr.b.mohclksel = 2;
+			cc_ap.b.core_clk_div = (top->ap_clk_src / top->pclk)
+						- 1;
+			temp = PLL2 / (cc_ap.b.core_clk_div + 1);
+			cc2_ap.b.mp1_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mp2_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mm_pclken_div = (temp / top->pclk_mm) - 1;
+			cc2_ap.b.aclken_div = (temp / top->baclk) - 1;
+		}
+		if (top->ap_clk_src == VCXO) {
+			fccr.b.mohclksel = 4;
+			cc_ap.b.core_clk_div = (top->ap_clk_src / top->pclk)
+						- 1;
+			temp = VCXO / (cc_ap.b.core_clk_div + 1);
+			cc2_ap.b.mp1_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mp2_pclken_div = (temp / top->pclk) - 1;
+			cc2_ap.b.mm_pclken_div = (temp / top->pclk_mm) - 1;
+			cc2_ap.b.aclken_div = (temp / top->baclk) - 1;
+		}
+		cc_ap.b.sp_freq_chg_req = 1;
+		coreFlag = 1;
+	}
+
+	if (cop->aclk != top->aclk || cop->aclk2 != top->aclk2) {
+		cc_ap.b.soc_axi_clk_div = (top->axi_clk_src / top->aclk) - 1;
+		cc2_ap.b.saxi_clk2_div = (top->axi_clk_src / top->aclk2) - 1;
+		if (top->axi_clk_src == PLL1)
+			bus_clk_ctrl.b.saxi_clk_sel = 1;
+		if (top->axi_clk_src == PLL1_DIV_BY_2)
+			bus_clk_ctrl.b.saxi_clk_sel = 0;
+		if (top->axi_clk_src == PLL2)
+			bus_clk_ctrl.b.saxi_clk_sel = 2;
+		if (top->axi_clk_src == PLL1_CLKOUT_P)
+			bus_clk_ctrl.b.saxi_clk_sel = 3;
+		if (top->axi_clk_src == VCXO)
+			bus_clk_ctrl.b.saxi_clk_sel = 4;
+		cc_ap.b.saxi_freq_chg_req = 1;
+		axiFlag = 1;
+	}
+
+	__raw_writel(bus_clk_ctrl.v, PMUA_BUS_CLK_RES_CTRL);
+	__raw_writel(fccr.v, PMUM_FCCR);
+	__raw_writel(cc_ap.v, PMUA_CC_MOH);
+	__raw_writel(cc2_ap.v, PMUA_CC2_MOH);
+	__raw_writel(cc3_ap.v, PMUA_CC3_MOH);
+
+	if (ddrFlag == 1) {
+
+		if (ddr_type == DDR3) {
+
+			ddr_fc_program_table(MCU1_BASE, cop->dclk_ddr,
+				top->dclk_ddr, ddr_type);
+			ddr_fc_program_table(MCU2_BASE, cop->dclk_ddr,
+				top->dclk_ddr, ddr_type);
+		} else {
+			ddr_fc_program_table(MCU1_BASE, cop->dclk_lp,
+				top->dclk_lp, ddr_type);
+			ddr_fc_program_table(MCU2_BASE, cop->dclk_lp,
+				top->dclk_lp, ddr_type);
+		}
+
+	}
+
+	if (coreFlag == 1 || axiFlag == 1 || ddrFlag == 1) {
+		allow_speed_change(1);
+		wait_for_fc_done();
+		allow_speed_change(0);
+	}
+
+	#ifdef CONFIG_MMP3_DVC
+	if (top->vcore < cop->vcore) {
+		if (set_volt(top->vcore) == 0)
+			printf("Voltage is changed to: %dmV\n", top->vcore);
+		else
+			printf("Voltage change was unsuccessful\n");
+	}
+	#endif
+}
+
+struct proc_op_array {
+	unsigned int cpuid;
+	unsigned int chip_id;
+	char *cpu_name;
+	struct operating_point *op_array;
+	unsigned int nr_op;
+};
+
+static struct proc_op_array proc_op_arrays[] = {
+{0x8000, 0xc921, "PXA921", pxa921_op_array, ARRAY_SIZE(pxa921_op_array)},
+{0x8000, 0xc920, "PXA920", pxa920_op_array, ARRAY_SIZE(pxa920_op_array)},
+{0x8000, 0xc910, "PXA910", pxa910_op_array, ARRAY_SIZE(pxa910_op_array)},
+{0x8000, 0x2128, "PXA2128", pxa2128_op_array, ARRAY_SIZE(pxa2128_op_array)},
+};
+
+int setop(int num)
+{
+	u32 ddr_type;
+	struct proc_op_array *proc = NULL;
+	struct operating_point *op;
+	unsigned int chip_id;
+	int i, j;
+	/*u32 gc_clk_res, lcd_clk_res;*/
+	struct operating_point cop;
+	/* pmua_cc cc_cp, cc_ap; */
+
+	ddr_type = __raw_readl(MCU1_BASE + SDRAM_CTRL4) & 0x0000001C;
+	chip_id = __raw_readl(0xd4282c00) & 0xffff;
+
+	for (i = 0; i < ARRAY_SIZE(proc_op_arrays); i++) {
+		proc = proc_op_arrays + i;
+		if (proc->chip_id == chip_id)
+			break;
+	}
+	if (i >= ARRAY_SIZE(proc_op_arrays))
+		return -1;
+
+	printf("Total defined OPs:%d (%d ~ %d)\n",
+		proc->nr_op, 0, (proc->nr_op - 1));
+	op = proc->op_array;
+	/*printf("in the set_op num: %d, op_num: %d, pclk: %d,
+	pclk_src: %u\n",num, op[num].op_id, op[num].pclk,op[num].ap_clk_src);*/
+
+	j = proc->nr_op - 1;
+	if (op[num].pclk == 0 || op[num].op_id == -1 || num > j) {
+		printf("op is not supported\n");
+		return -1;
+	}
+
+	freq_change_prep();
+	enable_fc_intr();
+	get_fc_lock();
+	get_current_op(&cop);
+	PMUcore2_fc_seq(&cop, &op[num]);
+	put_fc_lock();
+	return 0;
+}
+
+void show_op(void)
+{
+	struct operating_point cop;
+	u32 temp;
+	get_current_op(&cop);
+	if ((__raw_readl(MCU1_BASE + SDRAM_CTRL4) & 0x0000001C) == DDR3)
+		temp = cop.dclk_ddr;
+	else
+		temp = cop.dclk_lp;
+	printf("OP: MPs at %3uMHz, MM at %3uMHz, DDR at %3uMHz, "
+		"AXI_1 at %3uMHz, AXI_2 at %3uMHz\n",
+		cop.pclk, cop.pclk_mm, temp, cop.aclk, cop.aclk2);
+}
+
+void pj_cycle_monitor(void)
+{
+	u32 oldtimer, timer;
+	ulong   cycles_this_interval;
+	/* clear cycle counter and event counters */
+	__asm__ __volatile__ (
+	"mcr p15, 0, %[reg], c9, c12, 0"
+		:
+		:
+		[reg] "r" (0x6)
+		);
+	/* disable cycle counter */
+	__asm__ __volatile__ (
+	"mcr p15, 0, %[reg], c9, c12, 2"
+		:
+		:
+		[reg] "r" (0x80000000)
+		);
+	/* reset counter: FIXME - parameter of 0 OK? */
+	__asm__ __volatile__ (
+	"mcr p15, 0, %[reg], c9, c13, 0"
+		:
+		:
+		[reg] "r" (0)
+		);
+	/* enable cycle counter */
+	__asm__ __volatile__ (
+	"mcr p15, 0, %[reg], c9, c12, 1"
+		:
+		:
+		[reg] "r" (0x80000000)
+		);
+	/* start cycle counter and event counters */
+	__asm__ __volatile__ (
+	"mcr p15, 0, %[reg], c9, c12, 0"
+		:
+		:
+		[reg] "r" (0x7)
+		);
+	/* wait 100 mS */
+	__raw_writel(0x1, (CONFIG_SYS_TIMERBASE + 0xa4));
+	oldtimer = __raw_readl(CONFIG_SYS_TIMERBASE + 0xa4);
+	__raw_writel(0x1, (CONFIG_SYS_TIMERBASE + 0xa4));
+	oldtimer = __raw_readl(CONFIG_SYS_TIMERBASE + 0xa4);
+	while (1) {
+		__raw_writel(0x1, (CONFIG_SYS_TIMERBASE + 0xa4));
+		timer = __raw_readl(CONFIG_SYS_TIMERBASE + 0xa4);
+		__raw_writel(0x1, (CONFIG_SYS_TIMERBASE + 0xa4));
+		timer = __raw_readl(CONFIG_SYS_TIMERBASE + 0xa4);
+		if (timer >= oldtimer)
+			timer = timer - oldtimer;
+		else
+			timer = (0xffffffff - oldtimer) + timer;
+		if (timer >= (CONFIG_SYS_HZ/10))
+			break;
+	}
+	/* end of wait */
+	/* pmu read   */
+	/* cnt cycles */
+	__asm__ __volatile__ (
+	"mrc p15, 0, %[reg], c9, c13, 0" :
+	[reg] "=r" (cycles_this_interval)
+	);
+	/* cycles_this_interval has the value */
+	/* store the data in a globally visible space */
+	/**(volatile unsigned long *)0xd4282c24 = cycles_this_interval;*/
+	printf("%lu cycles\n", cycles_this_interval);
+}
+
+static const char *op_help_text[] = {
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| op num | pclk_mp0 | pclk_mp1 | pclk_mm | bclk | lp_dclk | d3_dclk | aclk1 | aclk2 | phclk | atclk |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 0   | 100      | 100      | 100     | 100  | 200     | 400     | 200   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 1   | 26       | 26       | 26      | 50   | 200     | 400     | 50    | 50    | 6.5   | 13    |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 2   | 50       | 50       | 50      | 50   | 200     | 400     | 100   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 3   | 100      | 100      | 50      | 50   | 200     | 400     | 100   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 4   | 200      | 200      | 200     | 200  | 200     | 400     | 200   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 5   | 400      | 400      | 200     | 400  | 200     | 400     | 400   | 200   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 6   | 800      | 800      | 400     | 400  | 200     | 400     | 400   | 200   | 200   | 266   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 7   | 531      | 531      | 265     | 531  | 200     | 400     | 400   | 200   | 177   | 354   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 8   | 1063     | 1063     | 265     | 531  | 200     | 400     | 400   | 200   | 177   | 354   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 9   | 400      | 400      | 400     | 400  | 200     | 400     | 400   | 200   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 10  | 100      | 100      | 100     | 100  | 400     | 531     | 200   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 11  | 26       | 26       | 26      | 50   | 400     | 531     | 50    | 50    | 6.5   | 13    |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 12  | 50       | 50       | 50      | 50   | 400     | 531     | 100   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 13  | 100      | 100      | 50      | 50   | 400     | 531     | 100   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 14  | 200      | 200      | 200     | 200  | 400     | 531     | 200   | 100   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 15  | 400      | 400      | 200     | 400  | 400     | 531     | 400   | 200   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 16  | 800      | 800      | 400     | 400  | 400     | 531     | 400   | 200   | 200   | 266   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 17  | 531      | 531      | 265     | 531  | 400     | 531     | 400   | 200   | 177   | 354   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 18  | 1063     | 1063     | 265     | 531  | 400     | 531     | 400   | 200   | 177   | 354   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+	"| OP 19  | 400      | 400      | 400     | 400  | 400     | 531     | 400   | 200   | 100   | 133   |\n",
+	"-----------------------------------------------------------------------------------------------------\n",
+};
+
+#endif /* non CONFIG_MACH_MMP2 */
+
+#ifdef CONFIG_MACH_MMP2
+#define DVFM_BASE_ADDR		0xd1020000
+#define DVFM_STACK_ADDR		0xd1028000
+extern void freq_init_sram(int addr);
+extern void freq_chg_seq(int vaddr, int vstack, int op, int flag);
+
+int do_op(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	int op;
+
+	if (argc != 2) {
+		printf("usage:\n%s\n", cmdtp->usage);
+		return 1;
+	}
+
+	op = simple_strtoul(argv[1], NULL, 0);
+	dcache_disable();
+	freq_init_sram(DVFM_BASE_ADDR);
+	freq_chg_seq(DVFM_BASE_ADDR, DVFM_STACK_ADDR, op, 3);
+	dcache_enable();
+	printf("op %d setting successfully\n", op);
+
+	return 0;
+}
+#else /* non CONFIG_MACH_MMP2 */
+int do_op(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong num;
+	printf("Performance before OP mode change: ");
+	pj_cycle_monitor();
+	if (argc == 2) {
+		if (strict_strtoul(argv[1], 0, &num) == 0) {
+			if (setop(num) < 0)
+				return -1;
+			printf("Freq change is done for OP: %lu\n", num);
+			printf("Performance after OP mode change: ");
+			pj_cycle_monitor();
+			show_op();
+		}
+	}
+
+	if (argc < 2) {
+		int i;
+
+		printf("Wrong argument, select op mode from below table: \n");
+		for (i = 0; i < ARRAY_SIZE(op_help_text); i++)
+			printf("%s", op_help_text[i]);
+		printf("Current Operating freq is:\n");
+		show_op();
+	}
+
+	return 0;
+}
+#endif /* CONFIG_MACH_MMP2 */
+
+U_BOOT_CMD(
+	op,	2,	1,	do_op,
+	"change operating point",
+	"[ op number ]"
+);
+
+#ifdef CONFIG_BROWNSTONE_VOLT
+
+#define VBUCK1_CNT(x)	((x < 0) ? -1 :			\
+				((x <= 1380) ? ((x - 750) / 10)	\
+				: -1))
+#define MAX8649_I2C_SLAVE_ADDR  0x60
+#endif
+
+#if defined(CONFIG_MMP_POWER) || defined(CONFIG_BROWNSTONE_VOLT)
+
+int set_volt(u32 vol)
+{
+	int res = -1;
+	u8 data;
+	u32 cnt_steps;
+
+#if defined(CONFIG_BROWNSTONE_VOLT)
+
+	cnt_steps = VBUCK1_CNT(vol);
+	if (cnt_steps < 0) {
+		return -1;
+	}
+	i2c_set_bus_num(0);
+	res = i2c_read(MAX8649_I2C_SLAVE_ADDR, 0x02, 1, &data, 1);
+	printf("SD1 old raw val is 0x%x res %d\n", data, res);
+	data &= ~0x3f;
+	data |= cnt_steps;
+	res = i2c_write(MAX8649_I2C_SLAVE_ADDR, 0x02, 1, &data, 1);
+	res = i2c_read(MAX8649_I2C_SLAVE_ADDR, 0x02, 1, &data, 1);
+	printf("SD1 new raw val is 0x%x res %d\n", data, res);
+
+#elif defined(CONFIG_MACH_ABILENE) || defined(CONFIG_MACH_MK2)
+
+#define MAX77601_SLAVE_ADDR 	0x1c
+#define MAX77601_VDVSSD0_REG 	0x1b
+#define MAX77601_SD0_REG 	0x16
+
+#define VOL_BASE		600000
+#define VOL_STEP		12500
+#define VOL_HIGH		1350000
+
+	vol *= 1000;
+	if ((vol < VOL_BASE) || (vol > VOL_HIGH)) {
+		printf("out of range when set voltage!\n");
+		return -1;
+	}
+
+	data = (vol - VOL_BASE) / VOL_STEP;
+	printf("Sending 0x%x to MAX77601\n", data);
+	i2c_set_bus_num(0);
+	res = i2c_write(MAX77601_SLAVE_ADDR, MAX77601_VDVSSD0_REG, 1, &data, 1);
+	res = i2c_write(MAX77601_SLAVE_ADDR, MAX77601_SD0_REG, 1, &data, 1);
+
+#elif defined(CONFIG_MACH_YELLOWSTONE)
+
+#define FAIR_CHILD_SLAVE_ADDR 	0x60
+#define FAIR_CHILD_VDVSSD0_REG 	0x1
+
+#define VOL_BASE		600000
+#define VOL_STEP		10000
+#define VOL_HIGH		1230000
+
+	vol *= 1000;
+	if ((vol < VOL_BASE) || (vol > VOL_HIGH)) {
+		printf("out of range when set voltage!\n");
+		return -1;
+	}
+
+	data = (vol - VOL_BASE) / VOL_STEP;
+	data |= 0x80;
+	printf("Sending 0x%x to fair child pmic\n", data);
+	i2c_set_bus_num(0);
+	res = i2c_write(FAIR_CHILD_SLAVE_ADDR, FAIR_CHILD_VDVSSD0_REG, 1, &data, 1);
+
+#elif defined(CONFIG_MACH_ORCHID)
+
+#define PM812_SLAVE_ADDR 	0x31
+#define PM812_VBUCK1_SET0_REG 	0x3c
+
+#define VOL_BASE		600000
+#define VOL_STEP		12500
+#define VOL_HIGH		1350000
+
+	vol *= 1000;
+	if ((vol < VOL_BASE) || (vol > VOL_HIGH)) {
+		printf("out of range when set voltage!\n");
+		return -1;
+	}
+
+	data = (vol - VOL_BASE) / VOL_STEP;
+	printf("Sending 0x%x to pm812\n", data);
+	i2c_set_bus_num(0);
+	res = i2c_write(PM812_SLAVE_ADDR, PM812_VBUCK1_SET0_REG, 1, &data, 1);
+
+#endif
+
+	return res;
+}
+
+int do_setvolt(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	ulong vol;
+	int res = -1;
+	if ((argc < 1) || (argc > 2))
+		return -1;
+
+	if (argc == 1) {
+		printf("usage: setvolt xxxx\n"
+			"for tavorevb and ttd_dkb, xxxx can be 725..1500, step 25\n"
+			"for aspenite and zylonite2, xxxx can be\n"
+			"493  521  550  578  606  635  663  691  720  748  776\n"
+			"805  833  861  890  918  947  975  1003 1032 1060 1088\n"
+			"1117 1145 1173 1202 1230 1258 1287 1315 1343 1372 1400\n"
+			"1429 1457 1485 1514 1542 1570 1599\n"
+			"for mmp2 bonnell, xxxx can be 750..1380, step 10\n"
+			"for mmp2 brownstone V1/2/3/4, xxxx can be 750..1380, step 25\n"
+			"for mmp2 brownstone V5, xxxx can be 790..1450, step 25\n"
+			"for mmp2 g50, xxxx can be 1140 1210 1280 1350\n"
+			"for mmp3 abliene/mk2, xxxx can be 600..1350, step 13 or 25\n"
+			"for mmp3 yellowstone, xxxx can be 600..1230, step 10\n"
+			"for mmp3 orchid, xxxx can be 600..1350, step 13 or 25\n"
+			);
+
+		return 0;
+	}
+	res = strict_strtoul(argv[1], 0, &vol);
+	if (res == 0 && set_volt(vol) == 0)
+		printf("Voltage change was successful\n");
+	else
+		printf("Voltage change was unsuccessful\n");
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	setvolt, 6, 1, do_setvolt,
+	"Setting voltages",
+	""
+);
+#endif
diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c
index 8eeb48fb2a..0174744dfe 100644
--- a/drivers/serial/ns16550.c
+++ b/drivers/serial/ns16550.c
@@ -19,6 +19,12 @@
 #ifdef CONFIG_SYS_NS16550_PORT_MAPPED
 #define serial_out(x,y)	outb(x,(ulong)y)
 #define serial_in(y)	inb((ulong)y)
+#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE > 0)
+#define serial_out(x,y) out_be32(y,x)
+#define serial_in(y) 	in_be32(y)
+#elif defined(CONFIG_SYS_NS16550_MEM32) && (CONFIG_SYS_NS16550_REG_SIZE < 0)
+#define serial_out(x,y) out_le32(y,x)
+#define serial_in(y) 	in_le32(y)
 #else
 #define serial_out(x,y) writeb(x,y)
 #define serial_in(y) 	readb(y)
diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c
index 0d56e78c50..0d6ad6283a 100644
--- a/drivers/serial/serial.c
+++ b/drivers/serial/serial.c
@@ -28,15 +28,6 @@
 #ifdef CONFIG_NS87308
 #include <ns87308.h>
 #endif
-#ifdef CONFIG_KIRKWOOD
-#include <asm/arch/kirkwood.h>
-#elif defined(CONFIG_ORION5X)
-#include <asm/arch/orion5x.h>
-#elif defined(CONFIG_ARMADA100)
-#include <asm/arch/armada100.h>
-#elif defined(CONFIG_PANTHEON)
-#include <asm/arch/pantheon.h>
-#endif
 
 #if defined (CONFIG_SERIAL_MULTI)
 #include <serial.h>
diff --git a/drivers/spi/kirkwood_spi.c b/drivers/spi/kirkwood_spi.c
index a1c307059c..6f502f05c4 100644
--- a/drivers/spi/kirkwood_spi.c
+++ b/drivers/spi/kirkwood_spi.c
@@ -27,6 +27,7 @@
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
+#include <asm/io.h>
 #include <asm/arch/kirkwood.h>
 #include <asm/arch/spi.h>
 #include <asm/arch/mpp.h>
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 7d5b504c7c..9b45026f8a 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -29,6 +29,8 @@ LIB	:= $(obj)libusb_gadget.o
 ifdef CONFIG_USB_ETHER
 COBJS-y += ether.o epautoconf.o config.o usbstring.o
 COBJS-$(CONFIG_USB_ETH_RNDIS) += rndis.o
+COBJS-$(CONFIG_CMD_FASTBOOT) += fastboot.o
+COBJS-$(CONFIG_MV_UDC)	+= mv_udc.o
 else
 # Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE
 ifdef CONFIG_USB_DEVICE
diff --git a/drivers/usb/gadget/fastboot.c b/drivers/usb/gadget/fastboot.c
new file mode 100644
index 0000000000..9273bf0a89
--- /dev/null
+++ b/drivers/usb/gadget/fastboot.c
@@ -0,0 +1,397 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+#include <common.h>
+#include <fastboot.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/cdc.h>
+#include <linux/usb/gadget.h>
+#include "gadget_chips.h"
+#include <mmc.h>
+#include "../../../../../kernel/kernel/arch/arm/mach-mmp/include/mach/wistron.h"
+
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+#define DEVSPEED	USB_SPEED_HIGH
+#else
+#define DEVSPEED	USB_SPEED_FULL
+#endif
+
+static char CUSTOMER_SERIAL_NUM[SN_SIZE] = "";
+
+struct fb_dev {
+	struct usb_gadget	*gadget;
+	struct usb_request	*req;		/* for control responses */
+	u8			config;
+	struct usb_ep		*in_ep, *out_ep;
+	const struct usb_endpoint_descriptor
+				*in, *out;
+	struct usb_request	*tx_req, *rx_req;
+};
+
+static u8 control_req[512];
+struct fb_dev l_fbdev;
+unsigned fb_packet_sent;
+static void tx_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	fb_packet_sent = 1;
+}
+
+void fb_tx_data(void *data, unsigned long len)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_request *req = dev->tx_req;
+	struct usb_ep *tx_ep = dev->in_ep;
+
+	while (len > 0) {
+		req->length = (len > tx_ep->maxpacket)
+			? tx_ep->maxpacket : len;
+		req->buf = data;
+		req->context = NULL;
+		req->complete = tx_complete;
+		fb_packet_sent = 0;
+		usb_ep_queue(dev->in_ep, req, 0);
+		while (!fb_packet_sent)
+			usb_gadget_handle_interrupts();
+
+		data += req->length;
+		len -= req->length;
+	}
+}
+
+void fb_tx_status(const char *status)
+{
+	fb_tx_data((void *)status, strlen(status));
+}
+
+static struct usb_device_descriptor device_desc = {
+	.bLength = sizeof(struct usb_device_descriptor),
+	.bDescriptorType =	USB_DT_DEVICE,
+	.bcdUSB =		__constant_cpu_to_le16(0x0200),
+
+	.idVendor =		__constant_cpu_to_le16(CONFIG_USBD_VENDORID),
+	.idProduct =		__constant_cpu_to_le16(CONFIG_USBD_PRODUCTID),
+	.iManufacturer =	0x1,
+	.iProduct =		0x2,
+	.iSerialNumber =	0x3,
+	.bNumConfigurations =	1
+};
+
+static struct usb_config_descriptor fb_config = {
+	.bLength = sizeof(struct usb_config_descriptor),
+	.bDescriptorType = USB_DT_CONFIG,
+
+	.bNumInterfaces = 1,
+	.bConfigurationValue = 1,
+	.iConfiguration = 4,
+	.bmAttributes = USB_CONFIG_ATT_ONE,
+	.bMaxPower = 0x80
+};
+
+static struct usb_interface_descriptor control_intf = {
+	.bLength  = sizeof(struct usb_interface_descriptor),
+	.bDescriptorType = USB_DT_INTERFACE,
+	.bInterfaceNumber = 0,
+	.bNumEndpoints = 0x2,
+	.bInterfaceClass = USB_CLASS_VENDOR_SPEC,
+	.bInterfaceSubClass = 0x42,
+	.bInterfaceProtocol = USB_CLASS_HID,
+};
+
+static struct usb_endpoint_descriptor fb_source_desc = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+
+	.bEndpointAddress = USB_DIR_IN,
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usb_endpoint_descriptor fb_sink_desc = {
+	.bLength = USB_DT_ENDPOINT_SIZE,
+	.bDescriptorType = USB_DT_ENDPOINT,
+
+	.bEndpointAddress = USB_DIR_OUT,
+	.bmAttributes =	USB_ENDPOINT_XFER_BULK,
+};
+
+static const struct usb_descriptor_header *fb_function[4] = {
+	(struct usb_descriptor_header *)&control_intf,
+	(struct usb_descriptor_header *)&fb_source_desc,
+	(struct usb_descriptor_header *)&fb_sink_desc,
+	NULL,
+};
+
+static struct usb_qualifier_descriptor dev_qualifier = {
+	.bLength =		sizeof dev_qualifier,
+	.bDescriptorType =	USB_DT_DEVICE_QUALIFIER,
+
+	.bcdUSB =		__constant_cpu_to_le16(0x0200),
+	.bDeviceClass =		USB_CLASS_VENDOR_SPEC,
+	.bMaxPacketSize0 =	64,
+
+	.bNumConfigurations =	1,
+};
+
+static struct usb_string strings[] = {
+	{ 1,	CONFIG_USBD_MANUFACTURER, },
+	{ 2,	CONFIG_USBD_PRODUCT_NAME, },
+	{ 3,	CUSTOMER_SERIAL_NUM, },
+	{ 4,	CONFIG_USBD_CONFIGURATION_STR, },
+	{0, NULL},
+};
+
+static struct usb_gadget_strings	stringtab = {
+	.language	= 0x0409,	/* en-us */
+	.strings = strings,
+};
+
+static void fb_setup_complete(struct usb_ep *ep, struct usb_request *req)
+{
+}
+
+static int fb_bind(struct usb_gadget *gadget)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_ep	*in_ep, *out_ep;
+	int gcnum;
+	gcnum = usb_gadget_controller_number(gadget);
+	if (gcnum >= 0)
+		device_desc.bcdDevice = cpu_to_le16(0x0300 + gcnum);
+	else {
+		/*
+		 * can't assume CDC works.  don't want to default to
+		 * anything less functional on CDC-capable hardware,
+		 * so we fail in this case.
+		 */
+		error("controller '%s' not recognized",
+			gadget->name);
+		return -ENODEV;
+	}
+
+	/* all we really need is bulk IN/OUT */
+	usb_ep_autoconfig_reset(gadget);
+	in_ep = usb_ep_autoconfig(gadget, &fb_source_desc);
+	if (!in_ep) {
+		error("can't autoconfigure on %s\n",
+			gadget->name);
+		return -ENODEV;
+	}
+	in_ep->driver_data = in_ep;	/* claim */
+
+	out_ep = usb_ep_autoconfig(gadget, &fb_sink_desc);
+	if (!out_ep) {
+		error("can't autoconfigure on %s\n",
+			gadget->name);
+		return -ENODEV;
+	}
+#ifdef CONFIG_USB_GADGET_DUALSPEED
+	fb_source_desc.wMaxPacketSize = __constant_cpu_to_le16(512);
+	fb_sink_desc.wMaxPacketSize = fb_source_desc.wMaxPacketSize;
+#endif
+	out_ep->driver_data = out_ep;	/* claim */
+	device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
+	usb_gadget_set_selfpowered(gadget);
+	dev->in_ep = in_ep;
+	dev->out_ep = out_ep;
+
+	dev->gadget = gadget;
+	set_gadget_data(gadget, dev);
+	gadget->ep0->driver_data = dev;
+	dev->req = usb_ep_alloc_request(gadget->ep0, 0);
+	dev->req->buf = control_req;
+	dev->req->complete = fb_setup_complete;
+	dev->tx_req = usb_ep_alloc_request(dev->in_ep, 0);
+	dev->rx_req = usb_ep_alloc_request(dev->out_ep, 0);
+	return 0;
+}
+
+static void fb_unbind(struct usb_gadget *gadget)
+{
+	return;
+}
+
+static void rx_complete(struct usb_ep *ep, struct usb_request *req)
+{
+	rcv_cmd();
+	req->length = 512;
+	req->complete = rx_complete;
+	usb_ep_queue(ep, req, 0);
+}
+
+static int
+fb_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl)
+{
+	struct fb_dev		*dev = get_gadget_data(gadget);
+	struct usb_request	*req = dev->req;
+	int			value = -EOPNOTSUPP;
+	u16			wValue = le16_to_cpu(ctrl->wValue);
+	u16			wLength = le16_to_cpu(ctrl->wLength);
+
+	switch (ctrl->bRequest) {
+	case USB_REQ_GET_DESCRIPTOR:
+		if (ctrl->bRequestType != USB_DIR_IN)
+			break;
+		switch (wValue >> 8) {
+
+		case USB_DT_DEVICE:
+			value = min(wLength, (u16) sizeof device_desc);
+			memcpy(req->buf, &device_desc, value);
+			break;
+		case USB_DT_CONFIG:
+			value  = usb_gadget_config_buf(&fb_config, req->buf,
+					512, fb_function);
+			if (value >= 0)
+				value = min(wLength, (u16) value);
+			break;
+
+		case USB_DT_STRING:
+			value = usb_gadget_get_string(&stringtab,
+					wValue & 0xff, req->buf);
+
+			if (value >= 0)
+				value = min(wLength, (u16) value);
+
+			break;
+		case USB_DT_DEVICE_QUALIFIER:
+			value = min(wLength, (u16) sizeof dev_qualifier);
+			memcpy(req->buf, &dev_qualifier, value);
+			break;
+		}
+		break;
+	case USB_REQ_SET_CONFIGURATION:
+		dev->out = &fb_sink_desc;
+		dev->in = &fb_source_desc;
+		dev->rx_req->length = 512;
+		dev->rx_req->complete = rx_complete;
+		usb_ep_enable(dev->out_ep, dev->out);
+		usb_ep_enable(dev->in_ep, dev->in);
+		value = usb_ep_queue(dev->out_ep, dev->rx_req, 0);
+		if (value)
+			error("rx submit --> %d", value);
+		value = 0;
+		break;
+	}
+
+	/* respond with data transfer before status phase? */
+	if (value >= 0) {
+		req->length = value;
+		req->zero = value < wLength
+				&& (value % gadget->ep0->maxpacket) == 0;
+		value = usb_ep_queue(gadget->ep0, req, 0);
+		if (value < 0) {
+			debug("ep_queue --> %d\n", value);
+			req->status = 0;
+		}
+	}
+
+	/* host either stalls (value < 0) or reports success */
+	return value;
+}
+
+static void fb_disconnect(struct usb_gadget *gadget)
+{
+	return;
+}
+
+void fb_halt(void)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_gadget *gadget = dev->gadget;
+	usb_gadget_disconnect(gadget);
+}
+
+static struct usb_gadget_driver fb_driver = {
+	.speed		= DEVSPEED,
+
+	.bind		= fb_bind,
+	.unbind		= fb_unbind,
+
+	.setup		= fb_setup,
+	.disconnect	= fb_disconnect,
+};
+
+void fb_init(void)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_gadget *gadget;
+	char *s;
+	s = getenv("fb_serial");
+	if (s != NULL) {
+		printf("Fastboot serial no set as:%s\n", s);
+		strings[2].s = s;
+	}
+	usb_gadget_register_driver(&fb_driver);
+	gadget = dev->gadget;
+	usb_gadget_connect(dev->gadget);
+
+
+#if 1	//Read customer serial number for "fastboot devices"
+	struct mmc *mmc_0;
+	char nvs_block[EMMC_BLOCK_SIZE];
+        mmc_0 = find_mmc_device(0);
+        if (mmc_0) {
+                if (mmc_init(mmc_0)){
+                        printf("MMC 0 card init failed!\n");
+                        return 0;
+                }
+        }
+	mmc_0->block_dev.block_read(0, NVS_OFFSET/EMMC_BLOCK_SIZE, 1, (struct WISTRON_NVS *)nvs_block);
+	
+	struct WISTRON_NVS *wis_nvs = nvs_block;
+	
+	if (strlen(wis_nvs->sn_customer) == 0) {
+		strcpy(CUSTOMER_SERIAL_NUM, "FZA1B");
+	} else {		
+		strcpy(CUSTOMER_SERIAL_NUM, wis_nvs->sn_customer);
+	}
+#endif
+}
+
+void fb_run(void)
+{
+	usb_gadget_handle_interrupts();
+}
+
+int fb_get_rcv_len(void)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_request *req = dev->rx_req;
+	return req->length;
+}
+
+void *fb_get_buf(void)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_request *req = dev->rx_req;
+	return req->buf;
+}
+
+void fb_set_buf(void *buf)
+{
+	struct fb_dev *dev = &l_fbdev;
+	struct usb_request *req = dev->rx_req;
+	req->buf = buf;
+}
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index 9bb7e2e77a..5d7b638b38 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -150,6 +150,11 @@
 #define	gadget_is_m66592(g)	0
 #endif
 
+#ifdef CONFIG_USB_GADGET_MV
+#define gadget_is_mv(g)        (!strcmp("mv_udc", (g)->name))
+#else
+#define gadget_is_mv(g)        0
+#endif
 
 /*
  * CONFIG_USB_GADGET_SX2
@@ -216,5 +221,7 @@ static inline int usb_gadget_controller_number(struct usb_gadget *gadget)
 		return 0x20;
 	else if (gadget_is_m66592(gadget))
 		return 0x21;
+	else if (gadget_is_mv(gadget))
+		return 0x22;
 	return -ENOENT;
 }
diff --git a/drivers/usb/gadget/mv_udc.c b/drivers/usb/gadget/mv_udc.c
new file mode 100644
index 0000000000..4f50c863ff
--- /dev/null
+++ b/drivers/usb/gadget/mv_udc.c
@@ -0,0 +1,559 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <linux/types.h>
+#include <usb/mv_udc.h>
+
+#ifndef DEBUG
+#define DBG(x...) do {} while (0)
+#else
+#define DBG(x...) printf(x)
+static const char *reqname(unsigned r)
+{
+	switch (r) {
+	case USB_REQ_GET_STATUS: return "GET_STATUS";
+	case USB_REQ_CLEAR_FEATURE: return "CLEAR_FEATURE";
+	case USB_REQ_SET_FEATURE: return "SET_FEATURE";
+	case USB_REQ_SET_ADDRESS: return "SET_ADDRESS";
+	case USB_REQ_GET_DESCRIPTOR: return "GET_DESCRIPTOR";
+	case USB_REQ_SET_DESCRIPTOR: return "SET_DESCRIPTOR";
+	case USB_REQ_GET_CONFIGURATION: return "GET_CONFIGURATION";
+	case USB_REQ_SET_CONFIGURATION: return "SET_CONFIGURATION";
+	case USB_REQ_GET_INTERFACE: return "GET_INTERFACE";
+	case USB_REQ_SET_INTERFACE: return "SET_INTERFACE";
+	default: return "*UNKNOWN*";
+	}
+}
+#endif
+
+#define PAGE_SIZE	4096
+#define QH_MAXNUM	32
+static struct usb_endpoint_descriptor ep0_out_desc = {
+	.bLength = sizeof(struct usb_endpoint_descriptor),
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = 0,
+	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
+};
+
+static struct usb_endpoint_descriptor ep0_in_desc = {
+	.bLength = sizeof(struct usb_endpoint_descriptor),
+	.bDescriptorType = USB_DT_ENDPOINT,
+	.bEndpointAddress = USB_DIR_IN,
+	.bmAttributes =	USB_ENDPOINT_XFER_CONTROL,
+};
+
+#define WAIT_FOR_SETUP		0
+#define DATA_STATE_XMIT		1
+#define DATA_STATE_RECV		2
+#define WAIT_FOR_OUT_STATUS	3
+static unsigned int ep0_state = WAIT_FOR_SETUP;
+
+struct ept_queue_head *epts;
+struct ept_queue_item *items[2 * NUM_ENDPOINTS];
+static int mv_pullup(struct usb_gadget *gadget, int is_on);
+static int mv_ep_enable(struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc);
+static int mv_ep_disable(struct usb_ep *ep);
+static int mv_ep_queue(struct usb_ep *ep,
+		struct usb_request *req, gfp_t gfp_flags);
+static struct usb_request *
+mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags);
+static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req);
+
+static struct usb_gadget_ops mv_udc_ops = {
+	.pullup = mv_pullup,
+};
+
+static struct usb_ep_ops mv_ep_ops = {
+	.enable         = mv_ep_enable,
+	.disable        = mv_ep_disable,
+	.queue          = mv_ep_queue,
+	.alloc_request  = mv_ep_alloc_request,
+	.free_request   = mv_ep_free_request,
+};
+
+static struct mv_ep ep[2 * NUM_ENDPOINTS];
+static struct mv_drv controller = {
+	.gadget = {
+		.ep0 = &ep[0].ep,
+		.name = "mv_udc",
+	},
+};
+
+static struct usb_request *
+mv_ep_alloc_request(struct usb_ep *ep, unsigned int gfp_flags)
+{
+	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+	return &mv_ep->req;
+}
+
+static void mv_ep_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+	return;
+}
+
+static void ep_enable(int num, int in)
+{
+	struct ept_queue_head *head;
+	struct mv_udc *udc = controller.udc;
+	unsigned n;
+	head = epts + 2*num + in;
+
+	n = readl(&udc->epctrl[num]);
+	if (in)
+		n |= (CTRL_TXE | CTRL_TXR | CTRL_TXT_BULK);
+	else
+		n |= (CTRL_RXE | CTRL_RXR | CTRL_RXT_BULK);
+
+	if (num != 0)
+		head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE) | CONFIG_ZLT;
+	writel(n, &udc->epctrl[num]);
+}
+
+static int mv_ep_enable(struct usb_ep *ep,
+		const struct usb_endpoint_descriptor *desc)
+{
+	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+	int num, in;
+	num = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (desc->bEndpointAddress & USB_DIR_IN) != 0;
+	ep_enable(num, in);
+	mv_ep->desc = desc;
+	return 0;
+}
+
+static int mv_ep_disable(struct usb_ep *ep)
+{
+	return 0;
+}
+
+static int mv_ep_queue(struct usb_ep *ep,
+		struct usb_request *req, gfp_t gfp_flags)
+{
+	struct mv_ep *mv_ep = container_of(ep, struct mv_ep, ep);
+	struct mv_udc *udc = controller.udc;
+	struct ept_queue_item *item;
+	struct ept_queue_head *head;
+	unsigned phys;
+	int bit, num, len, in;
+	num = mv_ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (mv_ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+	item = items[2 * num + in];
+	head = epts + 2 * num + in;
+	phys = (unsigned)req->buf;
+	len = req->length;
+
+	item->next = TERMINATE;
+	item->info = INFO_BYTES(len) | INFO_IOC | INFO_ACTIVE;
+	item->page0 = phys;
+	item->page1 = (phys & 0xfffff000) + 0x1000;
+
+	head->next = (unsigned) item;
+	head->info = 0;
+
+	DBG("ept%d %s queue len %x, buffer %x\n",
+			num, in ? "in" : "out", len, phys);
+
+	if (in)
+		bit = EPT_TX(num);
+	else
+		bit = EPT_RX(num);
+
+	flush_cache(phys, len);
+	flush_cache((unsigned long)item, sizeof(struct ept_queue_item));
+	flush_cache((unsigned long)head, sizeof(struct ept_queue_head));
+	writel(bit, &udc->epprime);
+
+	return 0;
+}
+
+static void handle_ep_complete(struct mv_ep *ep)
+{
+	struct ept_queue_item *item;
+	int num, in, len;
+	num = ep->desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+	in = (ep->desc->bEndpointAddress & USB_DIR_IN) != 0;
+	item = items[2 * num + in];
+
+	if (item->info & 0xff)
+		printf("EP%d/%s FAIL nfo=%x pg0=%x\n",
+			num, in ? "in" : "out", item->info, item->page0);
+
+	len = (item->info >> 16) & 0x7fff;
+	ep->req.length -= len;
+	DBG("ept%d %s complete %x\n",
+			num, in ? "in" : "out", len);
+	ep->req.complete(&ep->ep, &ep->req);
+
+	if (num == 0) {
+		switch (ep0_state) {
+		case DATA_STATE_XMIT:
+			/* receive status phase */
+			ep->req.length = 0;
+			ep->desc = &ep0_out_desc;
+			ep0_state = WAIT_FOR_OUT_STATUS;
+			usb_ep_queue(&ep->ep, &ep->req, 0);
+			break;
+		case DATA_STATE_RECV:
+			/* send status phase */
+			ep->req.length = 0;
+			ep->desc = &ep0_in_desc;
+			ep0_state = WAIT_FOR_OUT_STATUS;
+	                usb_ep_queue(&ep->ep, &ep->req, 0);
+			break;
+		case WAIT_FOR_OUT_STATUS:
+			ep0_state = WAIT_FOR_SETUP;
+			break;
+		}
+	}
+}
+
+#define SETUP(type, request) (((type) << 8) | (request))
+
+static void handle_setup(void)
+{
+	struct usb_request *req = &ep[0].req;
+	struct mv_udc *udc = controller.udc;
+	struct ept_queue_head *head;
+	struct usb_ctrlrequest r;
+	int status = 0;
+	int num, in, _num, _in, i;
+	char *buf;
+	head = epts;
+
+	invalidate_dcache_range((unsigned long)head,
+			(unsigned long)head + sizeof(struct ept_queue_head));
+	memcpy(&r, head->setup_data, sizeof(struct usb_ctrlrequest));
+	writel(EPT_RX(0), &udc->epstat);
+	DBG("handle setup %s, %x, %x index %x value %x\n", reqname(r.bRequest),
+	    r.bRequestType, r.bRequest, r.wIndex, r.wValue);
+
+	switch (SETUP(r.bRequestType, r.bRequest)) {
+	case SETUP(USB_RECIP_ENDPOINT, USB_REQ_CLEAR_FEATURE):
+		_num = r.wIndex & 15;
+		_in = !!(r.wIndex & 0x80);
+
+		if ((r.wValue == 0) && (r.wLength == 0)) {
+			req->length = 0;
+			for (i = 0; i < NUM_ENDPOINTS * 2; i++) {
+				if (!ep[i].desc)
+					continue;
+				num = ep[i].desc->bEndpointAddress
+					& USB_ENDPOINT_NUMBER_MASK;
+				in = (ep[i].desc->bEndpointAddress
+						& USB_DIR_IN) != 0;
+				if ((num == _num) && (in == _in)) {
+					ep_enable(num, in);
+					ep[0].desc = &ep0_in_desc;
+					ep0_state = WAIT_FOR_OUT_STATUS;
+					usb_ep_queue(controller.gadget.ep0,
+							req, 0);
+					break;
+				}
+			}
+		}
+		return;
+
+	case SETUP(USB_RECIP_DEVICE, USB_REQ_SET_ADDRESS):
+		/*
+		 * write address delayed (will take effect
+		 * after the next IN txn)
+		 */
+		writel((r.wValue << 25) | (1 << 24), &udc->devaddr);
+		req->length = 0;
+		ep[0].desc = &ep0_in_desc;
+		ep0_state = WAIT_FOR_OUT_STATUS;
+		usb_ep_queue(controller.gadget.ep0, req, 0);
+		return;
+
+	case SETUP(USB_DIR_IN | USB_RECIP_DEVICE, USB_REQ_GET_STATUS):
+		req->length = 2;
+		buf = (char *)req->buf;
+		buf[0] = 1 << USB_DEVICE_SELF_POWERED;
+		buf[1] = 0;
+		ep[0].desc = &ep0_in_desc;
+		usb_ep_queue(controller.gadget.ep0, req, 0);
+		ep0_state = DATA_STATE_XMIT;
+		return;
+	}
+
+	if (r.wLength) {
+		if (r.bRequestType & USB_DIR_IN)
+			ep[0].desc = &ep0_in_desc;
+		else
+			ep[0].desc = &ep0_out_desc;
+	} else
+		ep[0].desc = &ep0_in_desc;
+
+	/* pass request up to the gadget driver */
+	if (controller.driver)
+		status = controller.driver->setup(&controller.gadget, &r);
+	else
+		status = -ENODEV;
+
+	if (!status) {
+		if (r.wLength) {
+			/* DATA phase from gadget, STATUS phase from udc */
+			ep0_state = (r.bRequestType & USB_DIR_IN)
+				?  DATA_STATE_XMIT : DATA_STATE_RECV;
+		} else
+			ep0_state = WAIT_FOR_OUT_STATUS;
+		return;
+	}
+
+	DBG("STALL reqname %s type %x value %x, index %x\n",
+	    reqname(r.bRequest), r.bRequestType, r.wValue, r.wIndex);
+	writel((1<<16) | (1 << 0), &udc->epctrl[0]);
+}
+
+static void stop_activity(void)
+{
+	int i, num, in;
+	struct ept_queue_head *head;
+	struct mv_udc *udc = controller.udc;
+
+	ep[0].desc = &ep0_out_desc;
+	ep0_state = WAIT_FOR_SETUP;
+
+	writel(readl(&udc->epstat), &udc->epstat);
+	writel(readl(&udc->epcomp), &udc->epcomp);
+	writel(0xffffffff, &udc->epflush);
+
+	flush_cache((unsigned long)epts,
+			QH_MAXNUM * sizeof(struct ept_queue_head));
+	/* error out any pending reqs */
+	for (i = 0; i < NUM_ENDPOINTS; i++) {
+		if (i != 0)
+			writel(0, &udc->epctrl[i]);
+		if (ep[i].desc) {
+			num = ep[i].desc->bEndpointAddress
+				& USB_ENDPOINT_NUMBER_MASK;
+			in = (ep[i].desc->bEndpointAddress & USB_DIR_IN) != 0;
+			head = epts + (num * 2) + (in);
+			head->next = TERMINATE;
+			head->info = 0;
+		}
+	}
+}
+
+void udc_irq(void)
+{
+	struct mv_udc *udc = controller.udc;
+	unsigned n = readl(&udc->usbsts);
+	writel(n, &udc->usbsts);
+	int bit, i, num, in;
+
+	n &= (STS_SLI | STS_URI | STS_PCI | STS_UI | STS_UEI);
+	if (n == 0)
+		return;
+
+	if (n & STS_URI) {
+		DBG("-- reset --\n");
+		stop_activity();
+	}
+	if (n & STS_SLI)
+		DBG("-- suspend --\n");
+
+	if (n & STS_PCI) {
+		DBG("-- portchange --\n");
+		bit = (readl(&udc->portsc) >> 26) & 3;
+		if (bit == 2) {
+			controller.gadget.speed = USB_SPEED_HIGH;
+			for (i = 1; i < NUM_ENDPOINTS * 2; i++)
+				if (ep[i].desc)
+					ep[i].ep.maxpacket = 512;
+		} else {
+			controller.gadget.speed = USB_SPEED_FULL;
+		}
+	}
+
+	if (n & STS_UEI)
+		printf("<UEI %x>\n", readl(&udc->epcomp));
+
+	if (n & STS_UI) {
+		n = readl(&udc->epcomp);
+		if (n) {
+			writel(n, &udc->epcomp);
+
+			for (i = 0; i < NUM_ENDPOINTS * 2; i++) {
+				if (ep[i].desc) {
+					num = ep[i].desc->bEndpointAddress
+						& USB_ENDPOINT_NUMBER_MASK;
+					in = (ep[i].desc->bEndpointAddress
+							& USB_DIR_IN) != 0;
+					bit = (in) ? EPT_TX(num) : EPT_RX(num);
+					if (n & bit)
+						handle_ep_complete(&ep[i]);
+				}
+			}
+		}
+
+		n = readl(&udc->epstat);
+		if (n & EPT_RX(0))
+			handle_setup();
+	}
+}
+
+int usb_gadget_handle_interrupts(void)
+{
+	u32 value;
+	struct mv_udc *udc = controller.udc;
+
+	value = readl(&udc->usbsts);
+	if (value)
+		udc_irq();
+
+	return value;
+}
+
+static int mv_pullup(struct usb_gadget *gadget, int is_on)
+{
+	struct mv_udc *udc = controller.udc;
+	if (is_on) {
+		/* RESET */
+		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RST, &udc->usbcmd);
+		udelay(200);
+
+		writel((unsigned) epts, &udc->epinitaddr);
+
+		/* select DEVICE mode */
+		writel(USBMODE_DEVICE, &udc->usbmode);
+
+		writel(0xffffffff, &udc->epflush);
+
+		/* Turn on the USB connection by enabling the pullup resistor */
+		writel(USBCMD_ITC(MICRO_8FRAME) | USBCMD_RUN, &udc->usbcmd);
+	} else {
+		stop_activity();
+		writel(USBCMD_FS2, &udc->usbcmd);
+		udelay(800);
+		if (controller.driver)
+			controller.driver->disconnect(gadget);
+	}
+
+	return 0;
+}
+
+void udc_disconnect(void)
+{
+	struct mv_udc *udc = controller.udc;
+	/* disable pullup */
+	stop_activity();
+	writel(USBCMD_FS2, &udc->usbcmd);
+	udelay(800);
+	if (controller.driver)
+		controller.driver->disconnect(&controller.gadget);
+}
+
+static int mvudc_probe(void)
+{
+	struct ept_queue_head *head;
+	int i;
+	static int mvudc_init;
+
+	if (mvudc_init)
+		return 1;
+	else
+		mvudc_init = 1;
+	controller.gadget.ops = &mv_udc_ops;
+	controller.udc = (struct mv_udc *)CONFIG_USB_REG_BASE;
+	epts = memalign(PAGE_SIZE, QH_MAXNUM * sizeof(struct ept_queue_head));
+	memset(epts, 0, QH_MAXNUM * sizeof(struct ept_queue_head));
+	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
+		/*
+		 * For item0 and item1, they are served as ep0
+		 * out&in seperately
+		 */
+		head = epts + i;
+		if (i < 2)
+			head->config = CONFIG_MAX_PKT(EP0_MAX_PACKET_SIZE)
+				| CONFIG_ZLT | CONFIG_IOS;
+		else
+			head->config = CONFIG_MAX_PKT(EP_MAX_PACKET_SIZE)
+				| CONFIG_ZLT;
+		head->next = TERMINATE;
+		head->info = 0;
+
+		items[i] = memalign(PAGE_SIZE, sizeof(struct ept_queue_item));
+	}
+
+	INIT_LIST_HEAD(&controller.gadget.ep_list);
+	ep[0].ep.maxpacket = 64;
+	ep[0].ep.name = "ep0";
+	ep[0].desc = &ep0_out_desc;
+	INIT_LIST_HEAD(&controller.gadget.ep0->ep_list);
+	for (i = 0; i < 2 * NUM_ENDPOINTS; i++) {
+		if (i != 0) {
+			ep[i].ep.maxpacket = 512;
+			ep[i].ep.name = "ep-";
+			list_add_tail(&ep[i].ep.ep_list,
+				      &controller.gadget.ep_list);
+			ep[i].desc = NULL;
+		}
+		ep[i].ep.ops = &mv_ep_ops;
+	}
+	return 0;
+}
+
+int usb_gadget_register_driver(struct usb_gadget_driver *driver)
+{
+	struct mv_udc *udc;
+	int             retval;
+
+	if (!driver
+			|| driver->speed < USB_SPEED_FULL
+			|| !driver->bind
+			|| !driver->setup) {
+		DBG("bad parameter.\n");
+		return -EINVAL;
+	}
+
+	if (!mvudc_probe()) {
+		udc = controller.udc;
+		usb_lowlevel_init();
+		/* select ULPI phy */
+		writel(PTS(PTS_ENABLE) | PFSC, &udc->portsc);
+	}
+	retval = driver->bind(&controller.gadget);
+	if (retval) {
+		DBG("driver->bind() returned %d\n", retval);
+		return retval;
+	}
+	controller.driver = driver;
+
+	return 0;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+	return 0;
+}
diff --git a/drivers/usb/host/ehci-kirkwood.c b/drivers/usb/host/ehci-kirkwood.c
index 5570fc699d..6300587db0 100644
--- a/drivers/usb/host/ehci-kirkwood.c
+++ b/drivers/usb/host/ehci-kirkwood.c
@@ -27,6 +27,7 @@
 #include <usb.h>
 #include "ehci.h"
 #include "ehci-core.h"
+#include <asm/arch/cpu.h>
 #include <asm/arch/kirkwood.h>
 
 #define rdl(off)	readl(KW_USB20_BASE + (off))
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 3790f91e72..e53b4b9759 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -42,6 +42,9 @@ COBJS-$(CONFIG_VIDEO_SED13806) += sed13806.o
 COBJS-$(CONFIG_VIDEO_SM501) += sm501.o
 COBJS-$(CONFIG_VIDEO_SMI_LYNXEM) += smiLynxEM.o videomodes.o
 COBJS-$(CONFIG_VIDEO_VCXK) += bus_vcxk.o
+COBJS-$(CONFIG_HDMI) += hdmi.o
+COBJS-$(CONFIG_MMP_HDMI) += hdmi-mmp.o
+COBJS-$(CONFIG_PXA168_FB) += pxa168fb.o
 
 COBJS	:= $(sort $(COBJS-y))
 SRCS	:= $(COBJS:.o=.c)
diff --git a/drivers/video/hdmi-mmp.c b/drivers/video/hdmi-mmp.c
new file mode 100644
index 0000000000..ca9b6d8aa7
--- /dev/null
+++ b/drivers/video/hdmi-mmp.c
@@ -0,0 +1,465 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ */
+
+#include <asm/io.h>
+#include <asm-generic/errno.h>
+#include <hdmi.h>
+#include <linux/ctype.h>
+#include <linux/fb.h>
+#include <malloc.h>
+#include "hdmi-mmp.h"
+
+struct hdmi_mmp_dev {
+	struct hdmi_dev hdmi_dev;
+	void *base;
+};
+
+unsigned *hdmi_base;
+
+static struct hdmi_mmp_dev *mdp;
+static struct hdmi_mmp_dev mdev;
+
+void hdmi_direct_write(void *base, unsigned addr, unsigned data)
+{
+	writel(data, base + BASE_OFFSET + addr);
+}
+
+unsigned hdmi_direct_read(void *base, unsigned addr)
+{
+	return readl(base + BASE_OFFSET + addr);
+}
+
+unsigned hdmi_read(void *base, unsigned addr)
+{
+	writel(addr | 1 << 30, base + BASE_OFFSET + HDMI_ADDR);
+	return readl((base + BASE_OFFSET + HDMI_DATA)) & 0xff;
+}
+
+void hdmi_write(void *base, unsigned addr, unsigned data)
+{
+	writel(data & 0xff, base + BASE_OFFSET + HDMI_DATA);
+	writel(addr | 1 << 31, base + BASE_OFFSET + HDMI_ADDR);
+}
+
+static void hdmi_write_multi(struct hdmi_mmp_dev *md, u32 addr, u8 *buf,
+		u32 length)
+{
+	u32 i;
+	for (i = 0; i < length; i++)
+		hdmi_write(md->base, addr + i, *(buf + i));
+}
+
+static int hdmi_mmp_init_controller(struct hdmi_dev *dev)
+{
+	struct hdmi_mmp_dev *md = (struct hdmi_mmp_dev *)dev;
+	u32 i, cnt, tmp;
+
+	printf("Init mmp hdmi ctroller...\n");
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_2, 1<<27);
+
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_0, 0X00249b6d);
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_1, 0x0249cccc);
+	/* hdmi_direct_write(md->base, HDMI_PHY_CFG_2, 0X00003c30); */
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_2, 0X00003c10);
+	tmp = hdmi_direct_read(md->base, HDMI_PHY_CFG_3);
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_3, (tmp | 0X0000001));
+	udelay(50000);
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_3, (tmp & (~0X0000001)));
+	/* temporatyly set the aduio cfg */
+	/* hdmi_direct_write(md->base, HDMI_AUDIO_CFG, 0x869); */
+
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL0, 0);
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL1, 0);
+
+	/* Set MemSize */
+	hdmi_write(md->base, HDTX_MEMSIZE_L, 0xff);
+	hdmi_write(md->base, HDTX_MEMSIZE_H, 0xff);
+
+	/* Disable audio FIFO reset (H/W bug) */
+	hdmi_write(md->base, HDTX_FIFO_CTRL, 0);
+
+	/* Set deep color fifo read and write pointers */
+	hdmi_write(md->base, HDTX_DC_FIFO_WR_PTR, 0);
+	hdmi_write(md->base, HDTX_DC_FIFO_RD_PTR, 0x1f);
+
+	/* Set BCH Rotate Flag, disable rotate */
+	/* No register are affected ??? */
+
+	hdmi_write(md->base, HDTX_HDMI_CTRL, 0);
+
+	/* Set Swap Control, no TMDS channel swap */
+	hdmi_write(md->base, HDTX_SWAP_CTRL, 0);
+
+	/* Set Tmds Clock as 0x0F83E0(hard code value from DE) */
+	hdmi_write(md->base, HDTX_TDATA3_0, 0xe0);
+	hdmi_write(md->base, HDTX_TDATA3_1, 0x83);
+	hdmi_write(md->base, HDTX_TDATA3_2, 0xf);
+
+	/* Set I2S Audio Bus Parameters */
+	hdmi_write(md->base, HDTX_AUD_CTRL, 0x4);
+	hdmi_write(md->base, HDTX_I2S_CTRL, 0x8);
+
+	/* Disable audio transmission */
+	/*hdmi_write(md->base, HDTX_AUD_CTRL, 0x4); */
+	hdmi_write(md->base, HDTX_ACR_CTRL, 0x2);
+	hdmi_write(md->base, HDTX_ACR_N0, 0);
+	hdmi_write(md->base, HDTX_ACR_N1, 0);
+	hdmi_write(md->base, HDTX_ACR_N2, 0);
+
+	hdmi_write(md->base, HDTX_HDMI_CTRL, 0);
+
+	hdmi_write(md->base, HDTX_I2S_DLEN, 0);
+	hdmi_write(md->base, HDTX_CHSTS_0, 0);
+	hdmi_write(md->base, HDTX_CHSTS_1, 0);
+	hdmi_write(md->base, HDTX_CHSTS_2, 0);
+	hdmi_write(md->base, HDTX_CHSTS_3, 0);
+	hdmi_write(md->base, HDTX_CHSTS_4, 0);
+
+	/* Mute audio and video */
+	hdmi_write(md->base, HDTX_AVMUTE_CTRL, 0x3);
+
+	/* Clear all packet transmission */
+	for (i = 0; i < VPP_BE_HDMITX_MAX_PKT_INDEX; i++)
+	{
+		tmp = HDTX_PKT0_BYTE0 + 0x20 * i;
+		for (cnt = 0; cnt < 0x1f; cnt++)
+			hdmi_write(md->base, tmp, 0);
+	}
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL0, 0);
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL1, 0);
+
+	/* ACR given more priority than audio sample packets */
+	/* No register are affected ??? */
+
+	/* Why twice from VG ??? */
+	hdmi_write(md->base, HDTX_GCP_CFG0, 0);
+	hdmi_write(md->base, HDTX_GCP_CFG0, 0);
+
+	/* use program timing */
+	hdmi_write(md->base, HDTX_VIDEO_CTRL, 0x8);
+	hdmi_write(md->base, HDTX_HDMI_CTRL, 0x8);
+
+	/* reset program timing */
+	for (i = HDTX_HTOT_L; i <= HDTX_VSTART_H; i++)
+		hdmi_write(md->base, i, 0x0);
+
+	/* Clear UBits, user data of SPDIF header */
+	tmp = HDTX_UBITS_0;
+	for (i = 0; i < 14; i++, tmp++)
+		hdmi_write(md->base, tmp, 0x0);
+
+	/* Reset HBR Control. Spec doesn't have it!!! */
+	hdmi_write(md->base, HDTX_HBR_PKT, 0x0);
+
+	/* Clear Audio channel select. No swap */
+	tmp = HDTX_AUD_CH1_SEL;
+	for (i = 0; i < 8; i++, tmp++)
+		hdmi_write(md->base, tmp, i);
+
+	/* HPD Select. We do not have it !!! */
+	hdmi_write(md->base, TX_HDCP_HPD_SEL, 0x0);
+
+	/* Deep color control for pixel packing phase */
+	hdmi_write(md->base, HDTX_DC_PP_CTRL, 0x0);
+
+	/* host packets aligned with vsync rise edge timing */
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL2, 0x0);
+
+	/* Enable PHY FIFO */
+	hdmi_write(md->base, HDTX_PHY_FIFO_SOFT_RST, 0x1);
+	hdmi_write(md->base, HDTX_PHY_FIFO_SOFT_RST, 0x0);
+
+	/* Set HDCP Color */
+	hdmi_write(md->base, TX_HDCP_FIX_CLR_0, 0x80);
+	hdmi_write(md->base, TX_HDCP_FIX_CLR_1, 0x10);
+	hdmi_write(md->base, TX_HDCP_FIX_CLR_2, 0x80);
+
+	return 0;
+}
+
+void hdmi_3d_sync_view(void)
+{
+	u32 reg;
+
+	/*
+	reg = hdmi_direct_read(hdmi_base, HDMI_3D_CTRL);
+	reg &= ~ ((1 << 1) | (1 << 2) | (1 << 3));
+	reg |= 1 << 2;
+	hdmi_direct_write(hdmi_base, HDMI_3D_CTRL, 0);
+	*/
+	reg = 0x5;
+	hdmi_direct_write(hdmi_base, HDMI_3D_CTRL, reg);
+}
+
+static int hdmi_mmp_set_freq(struct hdmi_mmp_dev *md)
+{
+	int ret = 0;
+
+	/* Fix the pll2refdiv to 1(+2), to get 8.66MHz ref clk
+	 * Stable val recomended between 8-12MHz. To get the reqd
+	 * freq val, just program the fbdiv
+	 * freq takes effect during a fc req
+	 */
+	u32 residual;
+	volatile unsigned int temp = 0;
+	u32 freq;
+	unsigned int postdiv;
+	unsigned int freq_offset_inner;
+	unsigned int hdmi_pll_fbdiv;
+	unsigned int hdmi_pll_refdiv;
+	unsigned int kvco;
+	unsigned int freq_offset_inner_16;
+	unsigned int VPLL_CALCLK_DIV = 1;
+	unsigned int VDDM = 1;
+	unsigned int VDDL = 0x9;
+	unsigned int ICP = 0x9;
+	unsigned int VREG_IVREF = 2;
+	unsigned int INTPI = 5;
+	unsigned int VTH_VPLL_CA = 2;
+	int count = 0x10000;
+
+	ret = hdmi_get_freq ((struct hdmi_dev *)md, &freq);
+	if (ret)
+		return ret;
+
+	freq /= 1000;
+	/* round to freq = N*100k Hz */
+	residual = freq % 100;
+	freq = residual? (freq + 100 - residual) : freq;
+	freq /= 1000;
+
+	switch (freq) {
+	case 25:
+		postdiv = 0x3;
+		freq_offset_inner = 0x1C47;
+		freq_offset_inner_16 = 1;
+		hdmi_pll_fbdiv = 39;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	case 27:
+		postdiv = 0x3;
+		freq_offset_inner = 0x2d03;
+		freq_offset_inner_16 = 1;
+		hdmi_pll_fbdiv = 42;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	case 54:
+		postdiv = 0x2;
+		freq_offset_inner = 0x2d03;
+		freq_offset_inner_16 = 1;
+		hdmi_pll_fbdiv = 42;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	case 74:
+		postdiv = 0x2;
+		freq_offset_inner = 0x084B;
+		freq_offset_inner_16 = 0;
+		hdmi_pll_fbdiv = 57;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	case 108:
+		postdiv = 0x1;
+		freq_offset_inner = 0x2d03;
+		freq_offset_inner_16 = 1;
+		hdmi_pll_fbdiv = 42;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	case 148:
+		postdiv = 0x1;
+		freq_offset_inner = 0x084B;
+		freq_offset_inner_16 = 0;
+		hdmi_pll_fbdiv = 57;
+		hdmi_pll_refdiv = 0;
+		kvco = 0x4;
+		break;
+	default:
+		printf("not supported freq %d\n", freq);
+		return -EINVAL;
+	}
+
+	hdmi_direct_write(md->base, HDMI_CLOCK_CFG, 1|1<<2|1<<4|4<<5|5<<9|5<<13);
+	/*hdmi_direct_write(md->base, HDMI_CLOCK_CFG, 1|1<<2|4<<5|5<<9|5<<13); */
+
+	/* power up the pll */
+	temp |= HDMI_PLL_CFG_3_HDMI_PLL_ON;
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_3, temp);
+
+	temp = ((INTPI << HDMI_PLL_CFG_0_INTPI_BASE)	|
+			(HDMI_PLL_CFG_0_CLK_DET_EN)	|
+			(VDDM << HDMI_PLL_CFG_0_VDDM_BASE)	|
+			(VDDL << HDMI_PLL_CFG_0_VDDL_BASE)	|
+			(ICP << HDMI_PLL_CFG_0_ICP_BASE)	|
+			(kvco << HDMI_PLL_CFG_0_KVCO_BASE)	|
+			(VREG_IVREF << HDMI_PLL_CFG_0_VREG_IVREF_BASE)	|
+			(VPLL_CALCLK_DIV << HDMI_PLL_CFG_0_VPLL_CALCLK_DIV_BASE) |
+			(postdiv << HDMI_PLL_CFG_0_POSTDIV_BASE)	|
+			(ICP  << HDMI_PLL_CFG_0_ICP_BASE));
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_0, temp);
+
+	temp = ((HDMI_PLL_CFG_1_MODE) |
+			(HDMI_PLL_CFG_1_EN_PANNEL)|
+			(HDMI_PLL_CFG_1_EN_HDMI)|
+			(VTH_VPLL_CA << HDMI_PLL_CFG_1_VTH_VPLL_CA_BASE)|
+			(freq_offset_inner << HDMI_PLL_CFG_1_FREQ_OFFSET_INNER_BASE)|
+			(freq_offset_inner_16 << 20));
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_1, temp);
+
+	temp = 0;
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_2, temp);
+
+	/* Power Down the pll and set the divider ratios*/
+	temp = (hdmi_pll_fbdiv << HDMI_PLL_CFG_3_HDMI_PLL_FBDIV_BASE)|
+		(hdmi_pll_refdiv << HDMI_PLL_CFG_3_HDMI_PLL_REFDIV_BASE);
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_3, temp);
+
+	/* power up the pll */
+	temp |= HDMI_PLL_CFG_3_HDMI_PLL_ON;
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_3, temp);
+
+	/*wait 10us : just an estimate*/
+	udelay(100);
+
+	/* release the pll out of reset*/
+	temp |= HDMI_PLL_CFG_3_HDMI_PLL_RSTB;
+	hdmi_direct_write(md->base, HDMI_PLL_CFG_3, temp);
+
+	/* PLL_LOCK should be 1, */
+	temp = hdmi_direct_read(md->base, HDMI_PLL_CFG_3);
+	temp &= 0x400000;
+	while ( !temp )	{
+		temp = hdmi_direct_read(md->base, HDMI_PLL_CFG_3);
+		temp &= 0x400000;
+		udelay(10);
+		count--;
+		if (count <= 0) {
+			printf("%s PLL lock error, PLL_CFG_3 %x\n",
+				__func__, temp);
+			return -EIO;
+		}
+	}
+	/* pll stablize in 10ms */
+	udelay(10000);
+	return ret;
+}
+
+static int hdmi_send_packet (struct hdmi_mmp_dev *md, char *buf, int idx)
+{
+	u32 v;
+
+	hdmi_write_multi (md->base, HDTX_PKT0_BYTE0 + 0x20 * idx, buf, 32);
+	printf("packet addr 0x%x type 0x%x\n", HDTX_PKT0_BYTE0 + 0x20 * idx, *buf);
+
+	v = hdmi_read(md->base, HDTX_HST_PKT_CTRL0);
+	printf("ctrl0 0x%x\n", v);
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL0, v | (1 << idx));
+	/* HW bug */
+	v &= ~(1 << idx);
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL0, v);
+	v = hdmi_read(md->base, HDTX_HST_PKT_CTRL1);
+	hdmi_write(md->base, HDTX_HST_PKT_CTRL1, v | (1 << idx));
+}
+
+static int hdmi_mmp_get_reg (struct hdmi_dev *dev)
+{
+	struct hdmi_mmp_dev *md = (struct hdmi_mmp_dev *)dev;
+	int i;
+
+	printf("************direct register*******************\n");
+	for (i = 0x8; i <= 0x30; i += 4)
+		printf("direct offset 0x%x is 0x%x\n", i, hdmi_direct_read(md->base, i));
+	printf("************indirect register*******************\n");
+	for (i = 0; i < 0x13e; i++)
+		printf("offset 0x%x is 0x%x\n", i, hdmi_read(md->base, i));
+}
+
+static int hdmi_mmp_set_reg (struct hdmi_dev *dev)
+{
+	struct hdmi_mmp_dev *md = (struct hdmi_mmp_dev *)dev;
+
+	return 0;
+}
+
+static int hdmi_mmp_set_mode (struct hdmi_dev *dev, cea_mode_id id)
+{
+	char *buf;
+	u32 v;
+	struct hdmi_mmp_dev *md = (struct hdmi_mmp_dev *)dev;
+
+	dev->mode_id = id;
+	hdmi_mmp_set_freq (md);
+	buf = malloc (32);
+
+	hdmi_write(md->base, HDTX_PHY_FIFO_SOFT_RST, 0x0);
+	hdmi_write(md->base, HDTX_PHY_FIFO_SOFT_RST, 0x1);
+	hdmi_write(md->base, HDTX_PHY_FIFO_SOFT_RST, 0x0);
+	/* get proper avi packet */
+	hdmi_avi_info_frame (dev, buf);
+	/* write avi packet */
+	hdmi_send_packet (dev, buf, 0);
+	memset (buf, 0, 32);
+	hdmi_vender_info_frame (dev, buf);
+	hdmi_send_packet (dev, buf, 2);
+	free(buf);
+
+	v = hdmi_read(md->base, HDTX_HDMI_CTRL);
+	v &= ~0x78;
+	hdmi_write(md->base, HDTX_HDMI_CTRL, v | 0x1 | (dev->pixel_rept));
+	/* auto detect lcd timing */
+	hdmi_write(md->base, HDTX_VIDEO_CTRL, 0x58);
+	if (dev->mode_3d)
+		hdmi_direct_write(md->base, HDMI_3D_CTRL, 0x1);
+	else
+		hdmi_direct_write(md->base, HDMI_3D_CTRL, 0x0);
+	return 0;
+}
+
+static int hdmi_mmp_enable(struct hdmi_dev *dev, int enable)
+{
+	struct hdmi_mmp_dev *md = (struct hdmi_mmp_dev *)dev;
+	u32 v;
+
+	v = hdmi_direct_read(md->base, HDMI_CLOCK_CFG);
+	v = enable ? (v | (1<<4)) : (v & ~(1<<4));
+	hdmi_direct_write(md->base, HDMI_CLOCK_CFG, v);
+	hdmi_write(md->base, HDTX_AVMUTE_CTRL, 0x1);
+	hdmi_write(md->base, HDTX_GCP_CFG0, 1);
+
+	/* magic register */
+	hdmi_write(md->base, HDTX_TDATA3_1, 0x83);
+	hdmi_direct_write(md->base, HDMI_PHY_CFG_2, 0x3c10);
+	/*hdmi_direct_write(md->base,0x1c, 0xaa95); */
+	v = hdmi_read(md->base, HDTX_VIDEO_CTRL);
+	hdmi_write(md->base, HDTX_VIDEO_CTRL, v & (~0x40));
+	hdmi_write(md->base, HDTX_VIDEO_CTRL, v);
+	return 0;
+}
+
+void hdmi_init(struct fb_var_screeninfo *var, u32 id, u32 enable_3d)
+{
+	struct hdmi_mmp_dev *md = &mdev;
+	struct hdmi_dev *hd = (struct hdmi_dev *)md;
+
+#define DISPLAY_CONTROLLER_BASE                 0xD420B000
+	md->base = (void *)DISPLAY_CONTROLLER_BASE;
+	mdp = md;
+	hd->mode_3d = enable_3d;
+	//hd->mode_3d = 1;
+
+	hdmi_mmp_init_controller(hd);
+	hdmi_mmp_set_mode(hd, id);
+	hdmi_mmp_enable(hd, 1);
+	hdmi_base = md->base;
+}
diff --git a/drivers/video/hdmi-mmp.h b/drivers/video/hdmi-mmp.h
new file mode 100644
index 0000000000..b9fbb88d08
--- /dev/null
+++ b/drivers/video/hdmi-mmp.h
@@ -0,0 +1,2062 @@
+#define	HDMI_PHY_CFG_0	(0x0008)
+	/* 32 bit HDMI PHY Config 0 Register */
+#define	HDMI_PHY_CFG_1	(0x000C)
+	/* 32 bit HDMI PHY Config 1 Register */
+#define	HDMI_PHY_CFG_2	(0x0010)
+	/* 32 bit HDMI PHY Config 2 Register */
+#define	HDMI_PHY_CFG_3	(0x0014)
+	/* 32 bit HDMI PHY Config 3 Register */
+#define	HDMI_AUDIO_CFG	(0x0018)
+	/* 32 bit HDMI Audio Contror Register */
+#define	HDMI_CLOCK_CFG	(0x001C)
+	/* 32 bit HDMI Clock Control Register */
+#define	HDMI_PLL_CFG_0	(0x0020)
+	/* 32 bit HDMI PLL Control 0 Register */
+#define	HDMI_PLL_CFG_1	(0x0024)
+	/* 32 bit HDMI PLL Control 1 Register */
+#define	HDMI_PLL_CFG_2	(0x0028)	/* 32 bit HDMI PLL Control 2 Register */
+#define	HDMI_PLL_CFG_3	(0x002C)	/* 32 bit HDMI PLL Control 3 Register */
+#define	HDMI_3D_CTRL	(0x30)
+
+/*
+ *	THE BIT DEFINES
+ */
+/*	HDMI_PHY_CFG_0		0x0008	HDMI PHY Config 0 Register */
+#define	HDMI_PHY_CFG_0_CP_MSK	((0xff) << 24)	/* HDMI PHY CP Config */
+#define	HDMI_PHY_CFG_0_CP_BASE	24
+#define	HDMI_PHY_CFG_0_EAMP_MSK	((0xfff) << 12)	/* HDMI PHY EAMP Config */
+#define	HDMI_PHY_CFG_0_EAMP_BASE	12
+#define	HDMI_PHY_CFG_0_DAMP_MSK		(0xfff)/* HDMI PHY DAMP Config */
+#define	HDMI_PHY_CFG_0_DAMP_BASE	0
+/*	HDMI_PHY_CFG_1			0x000C	HDMI PHY Config 1 Register */
+#define	HDMI_PHY_CFG_1_AJ_D_MSK		((0xf) << 28)	/* HDMI PHY AJ_D Config */
+#define	HDMI_PHY_CFG_1_AJ_D_BASE	28
+#define	HDMI_PHY_CFG_1_SVTX_MSK		((0xfff) << 16)/* HDMI PHY SVTX Config */
+#define	HDMI_PHY_CFG_1_SVTX_BASE	16
+#define	HDMI_PHY_CFG_1_IDRV_MSK		(0xffff)	/* HDMI PHY IDRV Config */
+#define	HDMI_PHY_CFG_1_IDRV_BASE	0
+/*	HDMI_PHY_CFG_2		0x0010	HDMI PHY Config 2 Register */
+/* HDMI PHY TP_EN Config */
+#define	HDMI_PHY_CFG_2_TP_EN_MSK	((0xf) << 28)
+#define	HDMI_PHY_CFG_2_TP_EN_BASE	28
+/* HDMI PHY RESET_TX Config */
+#define	HDMI_PHY_CFG_2_RESET_TX		(1 << 27)
+/* HDMI PHY POLSWAP_TX Config */
+#define	HDMI_PHY_CFG_2_POLSWAP_TX_MSK	((0xf) << 23)
+#define	HDMI_PHY_CFG_2_POLSWAP_TX_BASE	23
+/* HDMI PHY PD_TX Config */
+#define	HDMI_PHY_CFG_2_PD_TX_MSK	((0xf) << 19)
+#define	HDMI_PHY_CFG_2_PD_TX_BASE	19
+/* HDMI PHY PD_IREF Config */
+#define	HDMI_PHY_CFG_2_PD_IREF		(1 << 18)
+/* HDMI PHY Loopback Config */
+#define	HDMI_PHY_CFG_2_LOOPBACK_MSK	((0xf) << 14)
+#define	HDMI_PHY_CFG_2_LOOPBACK_BASE	14
+/* HDMI PHY INV_CK20T Config */
+#define	HDMI_PHY_CFG_2_INV_CK20T_MSK	((0xf) << 10)
+#define	HDMI_PHY_CFG_2_INV_CK20T_BASE	10
+#define	HDMI_PHY_CFG_2_AUX_MSK		((0x3f)	<< 4)/* HDMI PHY AUS Config */
+#define	HDMI_PHY_CFG_2_AUX_BASE		4
+/* HDMI PHY AJ_EN Config */
+#define	HDMI_PHY_CFG_2_AJ_EN_MSK	(0xf)
+#define	HDMI_PHY_CFG_2_AJ_EN_BASE	0
+
+/*	HDMI_PHY_CFG_3	0x0014	HDMI PHY Config 3 Register */
+/*		Bit(s) HDMI_PHY_CFG_3_RSRV_31_11 reserved */
+/* HDMI Hot Plug Detection Status */
+#define	HDMI_PHY_CFG_3_HPD	(1 << 10)
+/* HDMI PHY TXDRVX2 Config */
+#define	HDMI_PHY_CFG_3_TXDRVX2_MSK	((0xf) << 6)
+#define	HDMI_PHY_CFG_3_TXDRVX2_BASE	6
+/* HDMI PHY TPC Config */
+#define	HDMI_PHY_CFG_3_TPC_MSK	((0x1f) << 1)
+#define	HDMI_PHY_CFG_3_TPC_BASE	1
+/* HDMI PHY SYNC Config */
+#define	HDMI_PHY_CFG_3_SYNC	1
+
+/*	HDMI_AUDIO_CFG			0x0018	HDMI Audio Control Register */
+/*		Bit(s) HDMI_AUDIO_CFG_RSRV_31_12 reserved */
+/* HDMI Audio I<super 2>S Config */
+#define	HDMI_AUDIO_CFG_I2S	(1 << 11)
+/* HDMI Audio wsp Config */
+#define	HDMI_AUDIO_CFG_WSP	(1 << 10)
+/* HDMI Audio fsp Config */
+#define	HDMI_AUDIO_CFG_FSP	(1 << 9)
+/* HDMI Audio clkp Config */
+#define	HDMI_AUDIO_CFG_CLKP	(1 << 8)
+/* HDMI Audio xdatdly Config */
+#define	HDMI_AUDIO_CFG_XDATDLY_MSK	((0x3) << 6)
+#define	HDMI_AUDIO_CFG_XDATDLY_BASE	6
+/* HDMI Audio xwdlen Config */
+#define	HDMI_AUDIO_CFG_XWDLEN_MSK	((0x7) << 3)
+#define	HDMI_AUDIO_CFG_XWDLEN_BASE	3
+/* HDMI Audio xfrlen Config */
+#define	HDMI_AUDIO_CFG_XFRLEN_MSK	(0x7)
+#define	HDMI_AUDIO_CFG_XFRLEN_BASE	0
+/*	HDMI_CLOCK_CFG			0x001C	HDMI Clock Control Register */
+/*		Bit(s) HDMI_CLOCK_CFG_RSRV_31_17 reserved */
+/* HDMI prclk Config */
+#define	HDMI_CLOCK_CFG_HDMI_PRCLK_DIV_MSK	((0xf) << 13)
+#define	HDMI_CLOCK_CFG_HDMI_PRCLK_DIV_BASE	13
+#define	HDMI_CLOCK_CFG_HDMI_TCLK_DIV_MSK	((0xf) << 9 )		/* HDMI tclk Config */
+#define	HDMI_CLOCK_CFG_HDMI_TCLK_DIV_BASE	9
+#define	HDMI_CLOCK_CFG_HDMI_MCLK_DIV_MSK	((0xf) << 5)/* HDMI mclk Config */
+#define	HDMI_CLOCK_CFG_HDMI_MCLK_DIV_BASE	5
+/* HDMI Enable Config */
+#define	HDMI_CLOCK_CFG_HDMI_EN	(1 << 4)
+#define	HDMI_CLOCK_CFG_RTC_MSK	((0x3) << 2)/* HDMI RTC Config */
+#define	HDMI_CLOCK_CFG_RTC_BASE	2
+#define	HDMI_CLOCK_CFG_WTC_MSK	(0x3)		/* HDMI WTC Config */
+#define	HDMI_CLOCK_CFG_WTC_BASE	0
+
+/*HDMI_PLL_CFG_0	0x0020	HDMI PLL Control 0 Register */
+#define HDMI_PLL_CFG_0_RESET_INTP_EXT_MSK ((0x1) << 31)
+#define HDMI_PLL_CFG_0_RESET_INTP_EXT_BASE 31
+/* HDMI PLL INTPI Config, INTPI [1_0] */
+#define	HDMI_PLL_CFG_0_INTPI_MSK	((0xf) << 27)
+#define	HDMI_PLL_CFG_0_INTPI_BASE	27
+/* HDMI PLL CLK_DET_EN Config */
+#define	HDMI_PLL_CFG_0_CLK_DET_EN	(1 << 26)
+/* HDMI PLL reset offset Config */
+#define	HDMI_PLL_CFG_0_RESET_OFFSET	(1 << 25)
+#define HDMI_PLL_CFG_0_KVCO_EXT_EN	(1 << 24)
+/* HDMI PLL KVCO Config */
+#define	HDMI_PLL_CFG_0_KVCO_MSK		((0xf) << 20)
+#define	HDMI_PLL_CFG_0_KVCO_BASE	20
+/* HDMI PLL CLKOUT TST ENABLE Config */
+#define	HDMI_PLL_CFG_0_CLKOUT_TST_EN	(1 << 19)
+/* HDMI PLL VREG IVREF config */
+#define HDMI_PLL_CFG_0_VREG_IVREF_MSK	((0x3) << 17)
+#define HDMI_PLL_CFG_0_VREG_IVREF_BASE	17
+/* HDMI PLL POSTDIV Config */
+#define	HDMI_PLL_CFG_0_POSTDIV_MSK	((0x7) << 14)
+#define	HDMI_PLL_CFG_0_POSTDIV_BASE	14
+#define	HDMI_PLL_CFG_0_ICP_MSK	((0xf) << 10)	/* HDMI PLL ICP Config */
+#define	HDMI_PLL_CFG_0_ICP_BASE	10
+/* HDMI PLL VDDL Config */
+#define	HDMI_PLL_CFG_0_VDDL_MSK	((0xf) << 6)
+#define	HDMI_PLL_CFG_0_VDDL_BASE	6
+/* HDMI PLL VDDM Config */
+#define	HDMI_PLL_CFG_0_VDDM_MSK	((0x3) << 4)
+#define	HDMI_PLL_CFG_0_VDDM_BASE	4
+/* HDMI PLL VPLL CAL START config */
+#define HDMI_PLL_CFG_0_VPLL_CAL_START	(1 << 3)
+/* HDMI PLL VPLL_CALCLK_DIV Config */
+#define	HDMI_PLL_CFG_0_VPLL_CALCLK_DIV_MSK	((0x3) << 1)
+#define	HDMI_PLL_CFG_0_VPLL_CALCLK_DIV_BASE	1
+
+/*HDMI_PLL_CFG_1 0x0024	HDMI PLL Control 1 Register */
+/*Bit(s) HDMI_PLL_CFG_1_RSRV_31 reserved */
+/* HDMI PLL VTH_VPLL_CA config */
+#define HDMI_PLL_CFG_1_VTH_VPLL_CA_MSK	((0x3) << 29)
+#define HDMI_PLL_CFG_1_VTH_VPLL_CA_BASE 29
+/* HDMI PLL TEST_MON Config */
+#define	HDMI_PLL_CFG_1_TEST_MON_MSK	((0xf) << 25)
+#define	HDMI_PLL_CFG_1_TEST_MON_BASE	25
+/* HDMI PLL EN_PANNEL Config */
+#define	HDMI_PLL_CFG_1_EN_PANNEL	(1 << 24)
+/* HDMI PLL EN_HDMI Config */
+#define	HDMI_PLL_CFG_1_EN_HDMI	(1 << 23)
+/* HDMI PLL FREQ_OFFSET_READY_ADJ Config */
+#define	HDMI_PLL_CFG_1_FREQ_OFFSET_READY_ADJ	(1 << 22)
+/* HDMI PLL FREQ_OFFSET_INNER Config */
+#define	HDMI_PLL_CFG_1_FREQ_OFFSET_INNER_MSK	((0x1ffff) << 4)
+#define	HDMI_PLL_CFG_1_FREQ_OFFSET_INNER_BASE	4
+/* HDMI PLL Mode Config, MODE [1_0] */
+#define	HDMI_PLL_CFG_1_MODE		(1 << 3)
+/* HDMI PLL CTUNE Config */
+#define	HDMI_PLL_CTUNE_MSK	0x7
+#define HDMI_PLL_CTUNE_BASE	0x0
+
+
+/*HDMI_PLL_CFG_2 0x0028	HDMI PLL Control 2 Register */
+/*Bit(s) HDMI_PLL_CFG_2_RSRV_31_17 reserved */
+/* HDMI PLL FREQ_OFFSET_ADJ Config */
+#define	HDMI_PLL_CFG_2_FREQ_OFFSET_ADJ_MSK	(0x1ffff)
+#define	HDMI_PLL_CFG_2_FREQ_OFFSET_ADJ_BASE	0
+
+/*HDMI_PLL_CFG_3 0x002C	HDMI PLL Control 3 Register */
+/*Bit(s) HDMI_PLL_CFG_3_RSRV_31_27 reserved */
+/* HDMI KVCO_RD Config */
+#define	HDMI_PLL_CFG_3_KVCO_RD_MSK	((0xf) << 23)
+#define	HDMI_PLL_CFG_3_KVCO_RD_BASE	23
+/* HDMI PLL_LOCK Config */
+#define	HDMI_PLL_CFG_3_PLL_LOCK		(1 << 22)
+/* HDMI CTUNE_RD Config */
+#define	HDMI_PLL_CFG_3_CTUNE_RD_MSK	((0x7) << 19)
+#define	HDMI_PLL_CFG_3_CTUNE_RD_BASE	19
+/* HDMI PLL VPLL_CAL_DONE config */
+#define HDMI_PLL_CFG_3_VPLL_CAL_DONE	(1 << 18)
+/* HDMI PLL VPLL_CAL_ENABLE config */
+#define HDMI_PLL_CFG_3_VPLL_CAL_ENABLE    (1 << 17)
+/* HDMI PLL hdmi_test_mode Config */
+#define	HDMI_PLL_CFG_3_HDMI_TEST_MODE (1 << 16)
+/* HDMI PLL hdmi_pll_fbdiv Config */
+#define	HDMI_PLL_CFG_3_HDMI_PLL_FBDIV_MSK	((0x1ff) << 7)
+#define	HDMI_PLL_CFG_3_HDMI_PLL_FBDIV_BASE	7
+/* HDMI PLL hdmi_pll_refdiv Config */
+#define	HDMI_PLL_CFG_3_HDMI_PLL_REFDIV_MSK	((0x1f) << 7)
+#define	HDMI_PLL_CFG_3_HDMI_PLL_REFDIV_BASE	2
+/* HDMI PLL hdmi_pll_rstb Config */
+#define	HDMI_PLL_CFG_3_HDMI_PLL_RSTB	(1 << 1)
+/* HDMI PLL hdmi_pll_on PU Config */
+#define	HDMI_PLL_CFG_3_HDMI_PLL_ON	1
+
+/*HDTX_ACR_N0	0x0000	ACR N Value Bits [7_0] Register */
+#define	HDTX_ACR_N0_ACR_N_7_0_MSK (0xff)	/* ACR_N[7_0] */
+#define	HDTX_ACR_N0_ACR_N_7_0_BASE 0
+/*HDTX_ACR_N1	0x0001	ACR N Value Bits [15_8] Register */
+#define	HDTX_ACR_N1_ACR_N_15_8_MSK (0xff)	/* ACR_N[15_8] */
+#define	HDTX_ACR_N1_ACR_N_15_8_BASE 0
+/*HDTX_ACR_N2	0x0002	ACR N Value Bits [19_16] Register */
+/*Bit(s) HDTX_ACR_N2_RSRV_7_4 reserved */
+#define	HDTX_ACR_N2_ACR_N_19_16_MSK (0xf)	/* ACR_N[19_16] */
+#define	HDTX_ACR_N2_ACR_N_19_16_BASE 0
+/*
+ *HDTX_ACR_CTS0 0x0004	Software-Calculated ACR CTS Value Bits [7_0] Register
+ */
+#define	HDTX_ACR_CTS0_ACR_CTS_7_0_MSK (0xff)	/* ACR_CTS[7_0] */
+#define	HDTX_ACR_CTS0_ACR_CTS_7_0_BASE 0
+/*
+ * HDTX_ACR_CTS1 0x0005	Software-Calculated ACR CTS Value Bits[15_8] Register
+ */
+#define	HDTX_ACR_CTS1_ACR_CTS_15_8_MSK (0xff)	/* ACR_CTS[15_8] */
+#define	HDTX_ACR_CTS1_ACR_CTS_15_8_BASE 0
+/*
+ *HDTX_ACR_CTS2	0x0006	Software-Calculated ACR CTS Value Bits[19_16] Register
+ */
+/*Bit(s) HDTX_ACR_CTS2_RSRV_7_4 reserved */
+#define	HDTX_ACR_CTS2_ACR_CTS_19_16_MSK (0xf)	/* ACR_CTS[19_16] */
+#define	HDTX_ACR_CTS2_ACR_CTS_19_16_BASE 0
+/*HDTX_ACR_CTRL	0x0007	ACR Control Register */
+/*Bit(s) HDTX_ACR_CTRL_RSRV_7_4 reserved */
+#define	HDTX_ACR_CTRL_MCLK_SEL_MSK	((0x3) << 2)	/* MCLK Select */
+#define	HDTX_ACR_CTRL_MCLK_SEL_BASE	2
+#define	HDTX_ACR_CTRL_CTS_SEL	(1 < 1)	/* CTS Select */
+#define	HDTX_ACR_CTRL_ACR_EN	1		/* ACR Enable */
+/*
+ * HDTX_ACR_STS0 0x0008	Hardware Computed ACR CTS Bits [7_0]Register
+ */
+#define	HDTX_ACR_STS0_ACR_CTS_VAL_7_0_MSK	(0xff)	/* ACR_CTS_VAL[7_0] */
+#define	HDTX_ACR_STS0_ACR_CTS_VAL_7_0_BASE	0
+
+/*	HDTX_ACR_STS1			0x0009	Hardware Computed ACR CTS Bits [15_8]
+ *									Register
+ */
+/* ACR_CTS_VAL[15_8] */
+#define	HDTX_ACR_STS1_ACR_CTS_VAL_15_8_MSK	(0xff)
+#define	HDTX_ACR_STS1_ACR_CTS_VAL_15_8_BASE	0
+
+/*	HDTX_ACR_STS2			0x000A	Hardware Computed ACR CTS Bits [19_16]
+ *									Register
+ */
+/*		Bit(s) HDTX_ACR_STS2_RSRV_7_4 reserved */
+/* ACR_CTS_VAL[19_16] */
+#define	HDTX_ACR_STS2_ACR_CTS_VAL_19_16_MSK	(0xf)
+#define	HDTX_ACR_STS2_ACR_CTS_VAL_19_16_BASE	0
+
+/*	HDTX_AUD_CTRL			0x000B	Audio Control Register */
+#define	HDTX_AUD_CTRL_VALIDITY	(1 << 7)		/* Validity */
+#define	HDTX_AUD_CTRL_I2S_DBG_EN	(1 << 6)		/* I<super 2>S Debug Enable */
+#define	HDTX_AUD_CTRL_I2S_MODE	(1 << 5)	/* I<super 2>S Mode */
+/* I<super 2>S Channel Enable */
+#define	HDTX_AUD_CTRL_I2S_CH_EN_MSK	((0xf) << 1)
+#define	HDTX_AUD_CTRL_I2S_CH_EN_BASE	1
+#define	HDTX_AUD_CTRL_AUD_EN	1		/* Audio Enable */
+
+/*	HDTX_I2S_CTRL			0x000C	I<super 2>S Control Register */
+/*		Bit(s) HDTX_I2S_CTRL_RSRV_7_5 reserved */
+#define	HDTX_I2S_CTRL_I2S_CTL_b4	(1 << 4) /* I<super 2>S Control [4] */
+#define	HDTX_I2S_CTRL_I2S_CTL_b3	(1 << 3) /* I<super 2>S Control [3] */
+#define	HDTX_I2S_CTRL_I2S_CTL_b2	(1 << 7) /* I<super 2>S Control [2] */
+#define	HDTX_I2S_CTRL_I2S_CTL_b1	(1 << 1)		/* I<super 2>S Control [1] */
+#define	HDTX_I2S_CTRL_I2S_CTL_b0	1		/* I<super 2>S Control [0] */
+
+/*	HDTX_I2S_DLEN			0x000D	I<super 2>S Valid Data Length Register */
+/*		Bit(s) HDTX_I2S_DLEN_RSRV_7_5 reserved */
+/* I<super 2>S Data Len [4_0] */
+#define	HDTX_I2S_DLEN_I2S_DATALEN_4_0_MSK	(0x1f)
+#define	HDTX_I2S_DLEN_I2S_DATALEN_4_0_BASE	0
+
+/*	HDTX_I2S_DBG_LFT0		0x0010	I<super 2>S Left Channel Debug Bits [7_0]
+ *									Register
+ */
+/* Left Debug [7_0] */
+#define	HDTX_I2S_DBG_LFT0_LEFT_DBG_7_0_MSK	(0xff)
+#define	HDTX_I2S_DBG_LFT0_LEFT_DBG_7_0_BASE	0
+
+/*	HDTX_I2S_DBG_LFT1		0x0011	I<super 2>S Left Channel Debug Bits [15_8]
+ *									Register
+ */
+/* Left Debug [15_8] */
+#define	HDTX_I2S_DBG_LFT1_LEFT_DBG_15_8_MSK	(0xff)
+#define	HDTX_I2S_DBG_LFT1_LEFT_DBG_15_8_BASE	0
+
+/*	HDTX_I2S_DBG_LFT2		0x0012	I<super 2>S Left Channel Debug Bits
+ *									[23_16] Register
+ */
+/* Left Debug [23_16] */
+#define	HDTX_I2S_DBG_LFT2_LEFT_DBG_23_16_MSK	(0xff)
+#define	HDTX_I2S_DBG_LFT2_LEFT_DBG_23_16_BASE	0
+
+/*	HDTX_I2S_DBG_LFT3		0x0013	I<super 2>S Left Channel Debug Bits
+ *									[31_24] Register
+ */
+/* Left Debug [31_24] */
+#define	HDTX_I2S_DBG_LFT3_LEFT_DBG_31_24_MSK	(0xff)
+#define	HDTX_I2S_DBG_LFT3_LEFT_DBG_31_24_BASE	0
+
+/*	HDTX_I2S_DBG_RIT0		0x0014	I<super 2>S Right Channel Debug Bits [7_0]
+ *									Register
+ */
+/* Right Debug [7_0] */
+#define	HDTX_I2S_DBG_RIT0_RIT_DBG_7_0_MSK	(0xff)
+#define	HDTX_I2S_DBG_RIT0_RIT_DBG_7_0_BASE	0
+
+/*	HDTX_I2S_DBG_RIT1		0x0015	I<super 2>S Right Channel Debug Bits
+ *									[15_8] Register
+ */
+/* Right Debug [15_8] */
+#define	HDTX_I2S_DBG_RIT1_RIT_DBG_15_8_MSK	(0xff)
+#define	HDTX_I2S_DBG_RIT1_RIT_DBG_15_8_BASE	0
+
+/*	HDTX_I2S_DBG_RIT2		0x0016	I<super 2>S Right Channel Debug Bits
+ *									[23_16] Register
+ */
+/* Right Debug [23_16] */
+#define	HDTX_I2S_DBG_RIT2_RIT_DBG_23_16_MSK	(0xff)
+#define	HDTX_I2S_DBG_RIT2_RIT_DBG_23_16_BASE	0
+
+/*	HDTX_I2S_DBG_RIT3		0x0017	I<super 2>S Right Channel Debug Bits
+ *									[31_24] Register
+ */
+/* Right Debug [31_24] */
+#define	HDTX_I2S_DBG_RIT3_RIT_DBG_31_24_MSK	(0xff)
+#define	HDTX_I2S_DBG_RIT3_RIT_DBG_31_24_BASE	0
+
+/*	HDTX_CHSTS_0			0x0018	Channel Status Bits [7_0] Register */
+#define	HDTX_CHSTS_0_CHSTS_7_0_MSK	(0xff)	/* Channel Status [7_0] */
+#define	HDTX_CHSTS_0_CHSTS_7_0_BASE	0
+
+/*	HDTX_CHSTS_1			0x0019	Channel Status Bits [15_8] Register */
+/* Channel Status [15_8] */
+#define	HDTX_CHSTS_1_CHSTS_15_8_MSK	(0xff)
+#define	HDTX_CHSTS_1_CHSTS_15_8_BASE	0
+
+/*	HDTX_CHSTS_2			0x001A	Channel Status Bits [23_16] Register */
+/* Channel Status [23_16] */
+#define	HDTX_CHSTS_2_CHSTS_23_16_MSK	(0xff)
+#define	HDTX_CHSTS_2_CHSTS_23_16_BASE	0
+
+/*	HDTX_CHSTS_3			0x001B	Channel Status Bits [31_24] Register */
+/* Channel Status [31_24] */
+#define	HDTX_CHSTS_3_CHSTS_31_24_MSK	(0xff)
+#define	HDTX_CHSTS_3_CHSTS_31_24_BASE	0
+
+/*	HDTX_CHSTS_4			0x001C	Channel Status Bits [39_32] Register */
+/* Channel Status [40_32] */
+#define	HDTX_CHSTS_4_CHSTS_40_32_MSK	(0xff)
+#define	HDTX_CHSTS_4_CHSTS_40_32_BASE	0
+
+/*	HDTX_FIFO_CTRL			0x001D	FIFO Control Register */
+/*		Bit(s) HDTX_FIFO_CTRL_RSRV_7_2 reserved */
+#define	HDTX_FIFO_CTRL_IRST	(1 << 1)			/* Internal FIFO Reset */
+#define	HDTX_FIFO_CTRL_FIFO_RST	1			/* FIFO Reset */
+
+/*	HDTX_MEMSIZE_L			0x001E	FIFO Memory Size Bits [7_0] Register */
+/* Memory Size [7_0] */
+#define	HDTX_MEMSIZE_L_MEMSIZE_7_0_MSK	(0xff)
+#define	HDTX_MEMSIZE_L_MEMSIZE_7_0_BASE	0
+
+/*	HDTX_MEMSIZE_H			0x001F	FIFO Memory Size Bit [8] Register */
+/*		Bit(s) HDTX_MEMSIZE_H_RSRV_7_1 reserved */
+#define	HDTX_MEMSIZE_H_MEMSIZE_b8			1			/* Memory Size [8] */
+
+/*	HDTX_GCP_CFG0			0x0020	GCP Packet Configure Register 0 */
+/*		Bit(s) HDTX_GCP_CFG0_RSRV_7_4 reserved */
+#define	HDTX_GCP_CFG0_PP_SW_VAL	(1 << 3)		/* PP Software Value */
+#define	HDTX_GCP_CFG0_DEF_PHASE	(1 << 2)		/* Default Phase */
+#define	HDTX_GCP_CFG0_AVMUTE	(1 << 1)		/* AV Mute */
+/* GCP Packet Transmission Enable */
+#define	HDTX_GCP_CFG0_GCP_EN	1
+
+/*	HDTX_GCP_CFG1			0x0021	GCP Packet Configure Register 1 */
+#define	HDTX_GCP_CFG1_COL_DEPTH_MSK	SHIFT4(0xf)	/* Color Depth */
+#define	HDTX_GCP_CFG1_COL_DEPTH_BASE	4
+#define	HDTX_GCP_CFG1_PP_3_0_MSK	(0xf)	/* Pixel Packing [3_0] */
+#define	HDTX_GCP_CFG1_PP_3_0_BASE	0
+
+/*HDTX_AUD_STS 0x0022	Audio Status Register */
+/*Bit(s) HDTX_AUD_STS_RSRV_7_4 reserved */
+#define	HDTX_AUD_STS_UNDERFLOW	(1 << 3)		/* Underflow */
+#define	HDTX_AUD_STS_OVERFLOW	(1 << 2)		/* Overflow */
+/*Bit(s) HDTX_AUD_STS_RSRV_1_0 reserved */
+/*HDTX_HTOT_L 0x0024	HTOTAL Bits [7_0] Register */
+/* Total Horizontal Pixels per Line [7_0] */
+#define	HDTX_HTOT_L_HTOT_7_0_MSK	(0xff)
+#define	HDTX_HTOT_L_HTOT_7_0_BASE	0
+
+/* HDTX_HTOT_H 0x0025	HTOTAL Bits [15_8] Register */
+/* Total Horizontal Pixels per Line [15_8] */
+#define	HDTX_HTOT_H_HTOT_15_8_MSK	(0xff)
+#define	HDTX_HTOT_H_HTOT_15_8_BASE	0
+
+/* HDTX_HBLANK_L 0x0026	HBLANK Bits [7_0] Register */
+/* Horizontal Blanking Period [7_0] */
+#define	HDTX_HBLANK_L_HBLANK_7_0_MSK	(0xff)
+#define	HDTX_HBLANK_L_HBLANK_7_0_BASE	0
+
+/* HDTX_HBLANK_H 0x0027	HBLANK Bits [15_8] Register */
+/* Horizontal Blanking Period [15_8] */
+#define	HDTX_HBLANK_H_HBLANK_15_8_MSK	(0xff)
+#define	HDTX_HBLANK_H_HBLANK_15_8_BASE		0
+
+/* HDTX_VTOT_L 0x0028	VTOTAL Bits [7_0] Register */
+/* Vertical Resolution [7_0] */
+#define	HDTX_VTOT_L_VTOT_7_0_MSK	(0xff)
+#define	HDTX_VTOT_L_VTOT_7_0_BASE	0
+
+/* HDTX_VTOT_H 0x0029	VTOTAL Bits [15_8] Register */
+/* Vertical Resolution [15_8] */
+#define	HDTX_VTOT_H_VTOT_15_8_MSK	(0xff)
+#define	HDTX_VTOT_H_VTOT_15_8_BASE	0
+
+/* HDTX_VRES_L 0x002A	VRES Bits [7_0] Register */
+/* Active Vertical Resolution [7_0] */
+#define	HDTX_VRES_L_VRES_7_0_MSK	(0xff)
+#define	HDTX_VRES_L_VRES_7_0_BASE	0
+
+/* HDTX_VRES_H 0x002B VRES Bits [15_8] Register */
+/* Active Vertical Resolution [15_8] */
+#define	HDTX_VRES_H_VRES_15_8_MSK	(0xff)
+#define	HDTX_VRES_H_VRES_15_8_BASE	0
+
+/* HDTX_VSTART_L 0x002C	VSTART Bits [7_0] Register */
+/* First Active Line of Frame [7_0] */
+#define	HDTX_VSTART_L_VSTART_7_0_MSK	(0xff)
+#define	HDTX_VSTART_L_VSTART_7_0_BASE	0
+
+/* HDTX_VSTART_H 0x002D	VSTART Bits [15_8] Register */
+/* First Active Line of Frame [15_8] */
+#define	HDTX_VSTART_H_VSTART15_8_MSK	(0xff)
+#define	HDTX_VSTART_H_VSTART15_8_BASE	0
+
+/* HDTX_HTOT_STS_L 0x002E HTOTAL Bits [7_0] Register */
+/* Total Horizontal Pixels per Line [7_0] */
+#define	HDTX_HTOT_STS_L_HTOT_VAL_7_0_MSK	(0xff)
+#define	HDTX_HTOT_STS_L_HTOT_VAL_7_0_BASE	0
+
+/* HDTX_HTOT_STS_H 0x002F	HTOTAL Bits [15_8] Register */
+/* Total Horizontal Pixels per Line [15_8] */
+#define	HDTX_HTOT_STS_H_HTOT_VAL_15_8_MSK	(0xff)
+#define	HDTX_HTOT_STS_H_HTOT_VAL_15_8_BASE	0
+
+/* HDTX_HBLANK_STS_L 0x0030 HBLANK Bits [7_0] Register */
+/* Horizontal Blanking Period [7_0] */
+#define	HDTX_HBLANK_STS_L_HBLANK_VAL_7_0_MSK	(0xff)
+#define	HDTX_HBLANK_STS_L_HBLANK_VAL_7_0_BASE	0
+
+/* HDTX_HBLANK_STS_H 0x0031 HBLANK Bits [15_8] Register */
+/* Horizontal Blanking Period [15_8] */
+#define	HDTX_HBLANK_STS_H_HBLANK_VAL_15_8_MSK	(0xff)
+#define	HDTX_HBLANK_STS_H_HBLANK_VAL_15_8_BASE	0
+
+/* HDTX_VTOT_STS_L 0x0032 VTOTAL Bits [7_0] Register */
+/* Vertical Resolution of Frame [7_0] */
+#define	HDTX_VTOT_STS_L_VTOT_VAL_7_0_MSK	(0xff)
+#define	HDTX_VTOT_STS_L_VTOT_VAL_7_0_BASE	0
+
+/* HDTX_VTOT_STS_H 0x0033 VTOTAL Bits [15_8] Register */
+/* Vertical Resolution of Frame [15_8] */
+#define	HDTX_VTOT_STS_H_VTOT_VAL_15_8_MSK	(0xff)
+#define	HDTX_VTOT_STS_H_VTOT_VAL_15_8_BASE	0
+
+/* HDTX_VRES_STS_L 0x0034 VRES Bits [7_0] Register */
+/* Active Vertical Resolution of Frame [7_0] */
+#define	HDTX_VRES_STS_L_VRES_VAL_7_0_MSK	(0xff)
+#define	HDTX_VRES_STS_L_VRES_VAL_7_0_BASE	0
+
+/* HDTX_VRES_STS_H 0x0035 VRES Bits [15_8] Register */
+/* Active Vertical Resolution of Frame [15_8] */
+#define	HDTX_VRES_STS_H_VRES_VAL_15_8_MSK	(0xff)
+#define	HDTX_VRES_STS_H_VRES_VAL_15_8_BASE	0
+
+/* HDTX_VSTART_STS_L 0x0036 VSTART Bits [7_0] Register */
+/* First Active Line of Frame [7_0] */
+#define	HDTX_VSTART_STS_L_VSTART_VAL_7_0_MSK	(0xff)
+#define	HDTX_VSTART_STS_L_VSTART_VAL_7_0_BASE	0
+
+/* HDTX_VSTART_STS_H 0x0037 VSTART Bits [15_8] Register */
+/* First Active Line of Frame [15_8] */
+#define	HDTX_VSTART_STS_H_VSTART_VAL_15_8_MSK	(0xff)
+#define	HDTX_VSTART_STS_H_VSTART_VAL_15_8_BASE	0
+
+/* HDTX_VIDEO_STS 0x0038 Video Status Register */
+/* Bit(s) HDTX_VIDEO_STS_RSRV_7_1 reserved */
+#define	HDTX_VIDEO_STS_INIT_OVER	1	/* Init Over */
+
+/* HDTX_VIDEO_CTRL 0x0039 Video Control Register */
+/* Bit(s) HDTX_VIDEO_CTRL_RSRV_7 reserved */
+/* Internal Logic Video Format Detect */
+#define	HDTX_VIDEO_CTRL_INT_FRM_SEL	(1 << 6)
+/* Bit(s) HDTX_VIDEO_CTRL_RSRV_5_4 reserved */
+#define	HDTX_VIDEO_CTRL_ACR_PRI_SEL_I	(1 << 3)		/* ACR priority selection */
+#define	HDTX_VIDEO_CTRL_DEBUG_CTRL	(1 << 2)		/* Debug control */
+#define	HDTX_VIDEO_CTRL_FLD_POL	(1 << 1)		/* Filed polarity */
+#define	HDTX_VIDEO_CTRL_IN_YC	1		/* Input Video YC */
+
+/* HDTX_HDMI_CTRL 0x003A HDMI Control Register */
+/* Bit(s) HDTX_HDMI_CTRL_RSRV_7 reserved */
+#define	HDTX_HDMI_CTRL_PIX_RPT_MSK	SHIFT4(0x7)	/* Pixel Repetition Values */
+#define	HDTX_HDMI_CTRL_PIX_RPT_BASE	4
+#define	HDTX_HDMI_CTRL_BCH_ROT	(1 << 2)		/* BCH Value */
+#define	HDTX_HDMI_CTRL_LAYOUT	(1 << 1)		/* Layout */
+#define	HDTX_HDMI_CTRL_HDMI_MODE	1		/* HDMI Mode */
+
+/* HDTX_PP_HW 0x0046 Hardware Computed Pixel Packing Value Register */
+/* Bit(s) HDTX_PP_HW_RSRV_7_4 reserved */
+#define	HDTX_PP_HW_PP_REG_MSK	(0xf)	/* Pixel Packing Phase */
+#define	HDTX_PP_HW_PP_REG_BASE	0
+
+/* HDTX_DC_FIFO_SFT_RST	0x0047	Deep Color FIFO Soft Reset Register */
+/* Bit(s) HDTX_DC_FIFO_SFT_RST_RSRV_7_1 reserved */
+/* FIFO Soft Reset */
+#define	HDTX_DC_FIFO_SFT_RST_FIFO_SFT_RST_REG	1
+
+/* HDTX_DC_FIFO_WR_PTR 0x0048 FIFO Write Pointer Register */
+/* Bit(s) HDTX_DC_FIFO_WR_PTR_RSRV_7_6 reserved */
+/* FIFO Write Pointer */
+#define	HDTX_DC_FIFO_WR_PTR_FIFO_WR_PTR__MSK	(0x3f)
+#define	HDTX_DC_FIFO_WR_PTR_FIFO_WR_PTR__BASE	0
+
+/* HDTX_DC_FIFO_RD_PTR 0x0049 FIFO Read Pointer Register */
+/* Bit(s) HDTX_DC_FIFO_RD_PTR_RSRV_7_6 reserved */
+/* FIFO Read Pointer */
+#define	HDTX_DC_FIFO_RD_PTR_FIFO_RD_PTR_REG_MSK	(0x3f)
+#define	HDTX_DC_FIFO_RD_PTR_FIFO_RD_PTR_REG_BASE	0
+
+/* HDTX_TDATA0_0 0x004C	Test Data [7_0] for TMDS Channel 0 Register */
+#define	HDTX_TDATA0_0_TDATA0_REG_7_0_MSK	(0xff)	/* TDATA0 [7_0] */
+#define	HDTX_TDATA0_0_TDATA0_REG_7_0_BASE	0
+
+/* HDTX_TDATA0_1 0x004D	Test Data [15_8] for TMDS Channel 0 Register */
+#define	HDTX_TDATA0_1_TDATA0_REG_15_8_MSK	(0xff)	/* TDATA0 [15_8] */
+#define	HDTX_TDATA0_1_TDATA0_REG_15_8_BASE	0
+
+/* HDTX_TDATA0_2 0x004E	Test Data [19_16] for TMDS Channel 0 Register */
+/* Bit(s) HDTX_TDATA0_2_RSRV_7_4 reserved */
+#define	HDTX_TDATA0_2_TDATA0_REG_19_16_MSK	(0xf)	/* TDATA0 [19_16] */
+#define	HDTX_TDATA0_2_TDATA0_REG_19_16_BASE	0
+
+/* HDTX_TDATA1_0 0x0050	Test Data [7_0] for TMDS Channel 1 Register */
+#define	HDTX_TDATA1_0_TDATA1_REG_7_0_MSK	(0xff)	/* TDATA1 [7_0] */
+#define	HDTX_TDATA1_0_TDATA1_REG_7_0_BASE	0
+
+/* HDTX_TDATA1_1 0x0051	Test Data [15_8] for TMDS Channel 1 Register */
+#define	HDTX_TDATA1_1_TDATA1_REG_15_8_MSK	(0xff)	/* TDATA1 [15_8] */
+#define	HDTX_TDATA1_1_TDATA1_REG_15_8_BASE	0
+
+/* HDTX_TDATA1_2 0x0052	Test Data [19_16] for TMDS Channel 1 Register */
+/* Bit(s) HDTX_TDATA1_2_RSRV_7_4 reserved */
+#define	HDTX_TDATA1_2_TDATA1_REG_19_16_MSK	(0xf)	/* TDATA1 [19_16] */
+#define	HDTX_TDATA1_2_TDATA1_REG_19_16_BASE	0
+
+/* HDTX_TDATA2_0 0x0054	Test Data [7_0] for TMDS Channel 2 Register */
+#define	HDTX_TDATA2_0_TDATA2_REG_7_0_MSK	(0xff)	/* TDATA2 [7_0] */
+#define	HDTX_TDATA2_0_TDATA2_REG_7_0_BASE	0
+
+/* HDTX_TDATA2_1 0x0055 Test Data [15_8] for TMDS Channel 2 Register */
+#define	HDTX_TDATA2_1_TDATA2_REG_15_8_MSK	(0xff)	/* TDATA2 [15_8] */
+#define	HDTX_TDATA2_1_TDATA2_REG_15_8_BASE	0
+
+/* HDTX_TDATA2_2 0x0056	Test Data [19_16] for TMDS Channel 2 Register */
+/* Bit(s) HDTX_TDATA2_2_RSRV_7_4 reserved */
+#define	HDTX_TDATA2_2_TDATA2_REG_19_16_MSK	(0xf)	/* TDATA2 [19_16] */
+#define	HDTX_TDATA2_2_TDATA2_REG_19_16_BASE	0
+
+/* HDTX_TDATA3_0 0x0058	Test Data [7_0] for TMDS Channel 3 Register */
+#define	HDTX_TDATA3_0_TDATA3_REG_7_0_MSK	(0xff)	/* TDATA3 [7_0] */
+#define	HDTX_TDATA3_0_TDATA3_REG_7_0_BASE	0
+
+/* HDTX_TDATA3_1 0x0059 Test Data [15_8] for TMDS Channel 3 Register */
+#define	HDTX_TDATA3_1_TDATA3_REG_15_8_MSK	(0xff)	/* TDATA3 [15_8] */
+#define	HDTX_TDATA3_1_TDATA3_REG_15_8_BASE	0
+
+/* HDTX_TDATA3_2 0x005A	Test Data [19_16] for TMDS Channel 3 Register */
+/* Bit(s) HDTX_TDATA3_2_RSRV_7_4 reserved */
+#define	HDTX_TDATA3_2_TDATA3_REG_19_16_MSK	(0xf)	/* TDATA3 [19_16] */
+#define	HDTX_TDATA3_2_TDATA3_REG_19_16_BASE	0
+
+/* HDTX_TDATA_SEL 0x005B Test Data Selection Control Register */
+/* Bit(s) HDTX_TDATA_SEL_RSRV_7 reserved */
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_b6	(1 << 6)		/* TDATA Select [6] */
+/* TDATA Select [5_4] */
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_5_4_MSK	((0x3) << 4)
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_5_4_BASE	4
+/* TDATA Select [3_2] */
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_3_2_MSK	((0x3) << 2)
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_3_2_BASE	2
+/* TDATA Select [1_0] */
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_1_0_MSK	(0x3)
+#define	HDTX_TDATA_SEL_TDATA_SEL_REG_1_0_BASE	0
+
+/* HDTX_SWAP_CTRL 0x005C	TMDS Data Swap Control Register */
+/* Bit(s) HDTX_SWAP_CTRL_RSRV_7_2 reserved */
+#define	HDTX_SWAP_CTRL_CHANNEL_SWAP	(1 << 1)			/* Channel Swap */
+#define	HDTX_SWAP_CTRL_BIT_SWAP	1			/* Bit Swap */
+
+/* HDTX_AVMUTE_CTRL 0x005D AVMUTE Control Register */
+/* Bit(s) HDTX_AVMUTE_CTRL_RSRV_7_2 reserved */
+#define	HDTX_AVMUTE_CTRL_AVMUTE_CTRL_REG_MSK	(0x3)		/* Audio Mute */
+#define	HDTX_AVMUTE_CTRL_AVMUTE_CTRL_REG_BASE	0
+
+/* HDTX_HOST_PKT_CTRL0 0x005E Host Packet Control Register 0 */
+/* Bit(s) HDTX_HOST_PKT_CTRL0_RSRV_7_6 reserved */
+#define	HDTX_HOST_PKT_CTRL0_PKT5_EN	(1 << 5)		/* Packet Type 5 Enable */
+#define	HDTX_HOST_PKT_CTRL0_PKT4_EN	(1 << 4)		/* Packet Type 4 Enable */
+#define	HDTX_HOST_PKT_CTRL0_PKT3_EN	(1 << 3)		/* Packet Type 3 Enable */
+#define	HDTX_HOST_PKT_CTRL0_PKT2_EN	(1 << 2)		/* Packet Type 2 Enable */
+#define	HDTX_HOST_PKT_CTRL0_PKT1_EN	(1 << 1)		/* Packet Type 1 Enable */
+#define	HDTX_HOST_PKT_CTRL0_PKT0_EN	1		/* Packet Type 0 Enable */
+
+/* HDTX_HOST_PKT_CTRL1 0x005F Host Packet Control Register 1 */
+/* Bit(s) HDTX_HOST_PKT_CTRL1_RSRV_7_6 reserved */
+/* Packet Type 5 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT5_TX_MODE	(1 << 5)
+/* Packet Type 4 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT4_TX_MODE	(1 << 4)
+/* Packet Type 3 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT3_TX_MODE	(1 << 3)
+/* Packet Type 2 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT2_TX_MODE	(1 << 2)
+/* Packet Type 1 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT1_TX_MODE	(1 << 1)
+/* Packet Type 0 Tx Mode */
+#define	HDTX_HOST_PKT_CTRL1_PKT0_TX_MODE	1
+
+/* HDTX_PKT0_BYTE0_30 0x0060 PKT0 Byte 0 to 30 Registers */
+#define	HDTX_PKT0_BYTE0_30_PKT0_255_0_MSK	(0xff)	/* PKT0 [255_0] */
+#define	HDTX_PKT0_BYTE0_30_PKT0_255_0_BASE	0
+
+/* HDTX_PKT1_BYTE0_30 0x0080	PKT1 Byte 0 to 30 Registers */
+#define	HDTX_PKT1_BYTE0_30_PKT1_255_0_MSK	(0xff)	/* PKT1 [255_0] */
+#define	HDTX_PKT1_BYTE0_30_PKT1_255_0_BASE	0
+
+/* HDTX_PKT2_BYTE0_30 0x00A0	PKT2 Byte 0 to 30 Registers */
+#define	HDTX_PKT2_BYTE0_30_PKT2_255_0_MSK	(0xff)	/* PKT2 [255_0] */
+#define	HDTX_PKT2_BYTE0_30_PKT2_255_0_BASE	0
+
+/* HDTX_PKT3_BYTE0_30 0x00C0 PKT3 Byte 0 to 30 Registers */
+#define	HDTX_PKT3_BYTE0_30_PKT3_255_0_MSK	(0xff)	/* PKT3 [255_0] */
+#define	HDTX_PKT3_BYTE0_30_PKT3_255_0_BASE	0
+
+/* HDTX_PKT4_BYTE0_30 0x00E0 PKT4 Byte 0 to 30 Registers */
+#define	HDTX_PKT4_BYTE0_30_PKT4_255_0_MSK	(0xff)	/* PKT4 [255_0] */
+#define	HDTX_PKT4_BYTE0_30_PKT4_255_0_BASE	0
+
+/* HDTX_PKT5_BYTE0_30 0x0100	PKT5 Byte 0 to 30 Registers */
+#define	HDTX_PKT5_BYTE0_30_PKT5_255_0_MSK	(0xff)	/* PKT5 [255_0] */
+#define	HDTX_PKT5_BYTE0_30_PKT5_255_0_BASE	0
+
+/* HDTX_UBITS_0 0x0120 User Data Bits of SPDIF Header Register 0 */
+/* User Data Bits of SPDIF Header [7_0] */
+#define	HDTX_UBITS_0_UBITS_7_0_MSK	(0xff)
+#define	HDTX_UBITS_0_UBITS_7_0_BASE	0
+
+/* HDTX_UBITS_1 0x0121 User Data Bits of SPDIF Header Register 1 */
+/* User Data Bits of SPDIF Header [15_8] */
+#define	HDTX_UBITS_1_UBITS_15_8_MSK	(0xff)
+#define	HDTX_UBITS_1_UBITS_15_8_BASE	0
+
+/* HDTX_UBITS_2	0x0122 User Data Bits of SPDIF Header Register 2 */
+/* User Data Bits of SPDIF Header [23_16] */
+#define	HDTX_UBITS_2_UBITS_23_16_MSK	(0xff)
+#define	HDTX_UBITS_2_UBITS_23_16_BASE	0
+
+/* HDTX_UBITS_3 0x0123 User Data Bits of SPDIF Header Register 3 */
+/* User Data Bits of SPDIF Header [31_24] */
+#define	HDTX_UBITS_3_UBITS_31_24_MSK	(0xff)
+#define	HDTX_UBITS_3_UBITS_31_24_BASE	0
+
+/* HDTX_UBITS_4	0x0124 User Data Bits of SPDIF Header Register 4 */
+/* User Data Bits of SPDIF Header [39_32] */
+#define	HDTX_UBITS_4_U_BITS_39_32_MSK	(0xff)
+#define	HDTX_UBITS_4_U_BITS_39_32_BASE	0
+
+/* HDTX_UBITS_5 0x0125 User Data Bits of SPDIF Header Register 5 */
+/* User Data Bits of SPDIF Header [47_40] */
+#define	HDTX_UBITS_5_UBITS_47_40_MSK	(0xff)
+#define	HDTX_UBITS_5_UBITS_47_40_BASE	0
+
+/* HDTX_UBITS_6	0x0126	User Data Bits of SPDIF Header Register 6 */
+/* User Data Bits of SPDIF Header [55_48] */
+#define	HDTX_UBITS_6_UBITS_55_48_MSK	(0xff)
+#define	HDTX_UBITS_6_UBITS_55_48_BASE	0
+
+/* HDTX_UBITS_7 0x0127 User Data Bits of SPDIF Header Register 7 */
+/* User Data Bits of SPDIF Header [63_56] */
+#define	HDTX_UBITS_7_UBITS_63_56_MSK	(0xff)
+#define	HDTX_UBITS_7_UBITS_63_56_BASE	0
+
+/* HDTX_UBITS_8	0x0128	User Data Bits of SPDIF Header Register 8 */
+/* User Data Bits of SPDIF Header [71_64] */
+#define	HDTX_UBITS_8_UBITS_71_64_MSK	(0xff)
+#define	HDTX_UBITS_8_UBITS_71_64_BASE	0
+
+/* HDTX_UBITS_9	0x0129 User Data Bits of SPDIF Header Register 9 */
+/* User Data Bits of SPDIF Header [79_72] */
+#define	HDTX_UBITS_9_UBITS_79_72_MSK	(0xff)
+#define	HDTX_UBITS_9_UBITS_79_72_BASE	0
+
+/* HDTX_UBITS_10 0x012A User Data Bits of SPDIF Header Register 10 */
+/* User Data Bits of SPDIF Header [87_80] */
+#define	HDTX_UBITS_10_UBITS_87_80_MSK	(0xff)
+#define	HDTX_UBITS_10_UBITS_87_80_BASE	0
+
+/* HDTX_UBITS_11 0x012B	User Data Bits of SPDIF Header Register 11 */
+/* User Data Bits of SPDIF Header [95_88] */
+#define	HDTX_UBITS_11_UBITS_95_88_MSK	(0xff)
+#define	HDTX_UBITS_11_UBITS_95_88_BASE	0
+
+/* HDTX_UBITS_12 0x012C User Data Bits of SPDIF Header Register 12 */
+/* User Data Bits of SPDIF Header [103_96] */
+#define	HDTX_UBITS_12_UBITS_103_96_MSK	(0xff)
+#define	HDTX_UBITS_12_UBITS_103_96_BASE	0
+
+/* HDTX_UBITS_13 0x012D	User Data Bits of SPDIF Header Register 13 */
+/* MSB 4 Bits [107_104] of SPDIF Header */
+#define	HDTX_UBITS_13_UBITS_107_104_MSK	(0xff)
+#define	HDTX_UBITS_13_UBITS_107_104_BASE	0
+
+/* HDTX_HBR_PKT 0x012E HBR Packet Transmission Control Register */
+/* Bit(s) HDTX_HBR_PKT_RSRV_7_1 reserved */
+/* Audio Sample/HBR Packet Transmission */
+#define	HDTX_HBR_PKT_HDTX_HBR_PKT	1
+
+/* HDTX_PHY_FIFO_SOFT_RST 0x013 HDMI Tx PHY FIFO Soft Reset Register */
+/* Bit(s) HDTX_PHY_FIFO_SOFT_RST_RSRV_7_1 reserved */
+/* PHY FIFO Soft Reset */
+#define	HDTX_PHY_FIFO_SOFT_RST_HDTX_PHY_FIFO_SOFT_RST	1
+
+/* HDTX_PHY_FIFO_PTRS 0x0131 HDMITX PHY FIFO Read and Write Pointers Register */
+/* LSB 4 Bits [7_4] for Putting Read Pointer */
+#define	HDTX_PHY_FIFO_PTRS_HDTX_PHY_FIFO_RD_PTRS_7_4_MSK	((0xf) << 4)
+#define	HDTX_PHY_FIFO_PTRS_HDTX_PHY_FIFO_RD_PTRS_7_4_BASE	4
+/* MSB 4 Bits [3_0] for Putting Write Pointer */
+#define	HDTX_PHY_FIFO_PTRS_HDTX_PHY_FIFO_WR_PTRS_3_0_MSK	(0xf)
+#define	HDTX_PHY_FIFO_PTRS_HDTX_PHY_FIFO_WR_PTRS_3_0_BASE	0
+
+/* HDTX_PRBS_CTRL0 0x0132 PRBS Control Register */
+/* Bit(s) HDTX_PRBS_CTRL0_RSRV_7_3 reserved */
+#define	HDTX_PRBS_CTRL0_PRBS_EN	(1 << 2)	/* PRBS Enable */
+#define	HDTX_PRBS_CTRL0_PRBS_TYPE_SEL_1_0_MSK	(0x3)	/* PRBS Control */
+#define	HDTX_PRBS_CTRL0_PRBS_TYPE_SEL_1_0_BASE	0
+
+/* HDTX_HST_PKT_CTRL2 0x0133 Host Packet Control Register 2 */
+/* Bit(s) HDTX_HST_PKT_CTRL2_RSRV_7_1 reserved */
+/* Host Packet Control 2 */
+#define	HDTX_HST_PKT_CTRL2_HOST_PKT_CTRL2	1
+
+/* HDTX_HST_PKT_START 0x0134 Host Packet Transmission Control During VBI Register */
+/* Bit(s) HDTX_HST_PKT_START_RSRV_7_1 reserved */
+/* Host Packet Start */
+#define	HDTX_HST_PKT_START_HOST_PKT_START	1
+
+/* HDTX_AUD_CH1_SEL 0x0137 Audio Channel 1 Select Register */
+/* Bit(s) HDTX_AUD_CH1_SEL_RSRV_7_3 reserved */
+/* Audio Channel1 select */
+#define	HDTX_AUD_CH1_SEL_AUD_CH1_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH1_SEL_AUD_CH1_SEL_BASE	0
+
+/* HDTX_AUD_CH2_SEL 0x0138 Audio Channel 2 Select Register */
+/* Bit(s) HDTX_AUD_CH2_SEL_RSRV_7_3 reserved */
+/* Audio Channel2 select */
+#define	HDTX_AUD_CH2_SEL_AUD_CH2_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH2_SEL_AUD_CH2_SEL_BASE	0
+
+/* HDTX_AUD_CH3_SEL 0x0139 Audio Channel 3 Select Register */
+/* Bit(s) HDTX_AUD_CH3_SEL_RSRV_7_3 reserved */
+/* Audio Channel3 select */
+#define	HDTX_AUD_CH3_SEL_AUD_CH3_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH3_SEL_AUD_CH3_SEL_BASE	0
+
+/* HDTX_AUD_CH4_SEL 0x013A Audio Channel 4 Select Register */
+/* Bit(s) HDTX_AUD_CH4_SEL_RSRV_7_3 reserved */
+/* Audio Channel4 select */
+#define	HDTX_AUD_CH4_SEL_AUD_CH4_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH4_SEL_AUD_CH4_SEL_BASE	0
+
+/* HDTX_AUD_CH5_SEL 0x013B Audio Channel 5 Select Register */
+/* Bit(s) HDTX_AUD_CH5_SEL_RSRV_7_3 reserved */
+/* Audio Channel5 select */
+#define	HDTX_AUD_CH5_SEL_AUD_CH5_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH5_SEL_AUD_CH5_SEL_BASE	0
+
+/* HDTX_AUD_CH6_SEL 0x013C Audio Channel 6 Select Register */
+/* Bit(s) HDTX_AUD_CH6_SEL_RSRV_7_3 reserved */
+/* Audio Channel6 select */
+#define	HDTX_AUD_CH6_SEL_AUD_CH6_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH6_SEL_AUD_CH6_SEL_BASE	0
+
+/* HDTX_AUD_CH7_SEL 0x013D Audio Channel 7 Select Register */
+/* Bit(s) HDTX_AUD_CH7_SEL_RSRV_7_3 reserved */
+/* Audio Channel7 select */
+#define	HDTX_AUD_CH7_SEL_AUD_CH7_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH7_SEL_AUD_CH7_SEL_BASE	0
+
+/* HDTX_AUD_CH8_SEL 0x013E Audio Channel 8 Select Register */
+/* Bit(s) HDTX_AUD_CH8_SEL_RSRV_7_3 reserved */
+/* Audio Channel8 select */
+#define	HDTX_AUD_CH8_SEL_AUD_CH8_SEL_MSK	(0x7)
+#define	HDTX_AUD_CH8_SEL_AUD_CH8_SEL_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_0 0x1200 AKEY0 [7_0] Register */
+#define	TX_HDCP_AKEY0_BYTE_0_AKEY0_7_0_MSK	(0xff)	/* AKEY0 [7_0] */
+#define	TX_HDCP_AKEY0_BYTE_0_AKEY0_7_0_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_1 0x1201 AKEY0 [15_8] Register */
+#define	TX_HDCP_AKEY0_BYTE_1_AKEY0_15_8_MSK	(0xff)	/* AKEY0 [15_8] */
+#define	TX_HDCP_AKEY0_BYTE_1_AKEY0_15_8_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_2	0x1202 AKEY0 [23_16] Register */
+/* AKEY0 [23_16] */
+#define	TX_HDCP_AKEY0_BYTE_2_AKEY0_23_16_MSK	(0xff)
+#define	TX_HDCP_AKEY0_BYTE_2_AKEY0_23_16_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_3	0x1203 AKEY0 [31_24] Register */
+/* AKEY0 [31_24] */
+#define	TX_HDCP_AKEY0_BYTE_3_AKEY0_31_24_MSK	(0xff)
+#define	TX_HDCP_AKEY0_BYTE_3_AKEY0_31_24_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_4	0x1204 AKEY0 [39_32] Register */
+/* AKEY0 [39_32] */
+#define	TX_HDCP_AKEY0_BYTE_4_AKEY0_39_32_MSK	(0xff)
+#define	TX_HDCP_AKEY0_BYTE_4_AKEY0_39_32_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_5	0x1205 AKEY0 [47_40] Register */
+/* AKEY0 [47_40] */
+#define	TX_HDCP_AKEY0_BYTE_5_AKEY0_47_40_MSK	(0xff)
+#define	TX_HDCP_AKEY0_BYTE_5_AKEY0_47_40_BASE	0
+
+/* TX_HDCP_AKEY0_BYTE_6	0x1206 AKEY0 [55_48] Register */
+/* AKEY0 [55_48] */
+#define	TX_HDCP_AKEY0_BYTE_6_AKEY0_55_48_MSK	(0xff)
+#define	TX_HDCP_AKEY0_BYTE_6_AKEY0_55_48_BASE	0
+
+/* TX_HDCP_AKSV_BYTE_0 0x1340 AKSV [7_0] Register */
+#define	TX_HDCP_AKSV_BYTE_0_AKSV0_7_0_MSK	(0xff)	/* AKSV0 [7_0] */
+#define	TX_HDCP_AKSV_BYTE_0_AKSV0_7_0_BASE	0
+
+/* TX_HDCP_AKSV_BYTE_1 0x1341 AKSV [15_8] Register */
+#define	TX_HDCP_AKSV_BYTE_1_AKSV0_15_8_MSK	(0xff)	/* AKSV0 [15_8] */
+#define	TX_HDCP_AKSV_BYTE_1_AKSV0_15_8_BASE	0
+
+/* TX_HDCP_AKSV_BYTE_2 0x1342 AKSV [23_16] Register */
+/* AKSV0 [23_16] */
+#define	TX_HDCP_AKSV_BYTE_2_AKSV0_23_16_MSK	(0xff)
+#define	TX_HDCP_AKSV_BYTE_2_AKSV0_23_16_BASE	0
+
+/* TX_HDCP_AKSV_BYTE_3 0x1343 AKSV [31_24] Register */
+/* AKSV0 [31_24] */
+#define	TX_HDCP_AKSV_BYTE_3_AKSV0_31_24_MSK	(0xff)
+#define	TX_HDCP_AKSV_BYTE_3_AKSV0_31_24_BASE	0
+
+/* TX_HDCP_AKSV_BYTE_4 0x1344 AKSV [39_32] Register */
+/* AKSV0 [39_32] */
+#define	TX_HDCP_AKSV_BYTE_4_AKSV0_39_32_MSK	(0xff)
+#define	TX_HDCP_AKSV_BYTE_4_AKSV0_39_32_BASE	0
+
+/* TX_HDCP_CONTROL 0x1350 HDCP Control Register */
+#define	TX_HDCP_CONTROL_HDMI_MODE	(1 << 7)	/* HDMI Mode */
+#define	TX_HDCP_CONTROL_EESS_EN	(1 << 6)	/* EESS Enable */
+#define	TX_HDCP_CONTROL_REPEATER	(1 << 5)	/* Repeater */
+#define	TX_HDCP_CONTROL_ADVANCE_CIPHER	(1 << 4)	/* Advance Cipher */
+/* Enhanced Link Verification */
+#define	TX_HDCP_CONTROL_ENH_LINK_VERIFICATION	(1 << 3)
+#define	TX_HDCP_CONTROL_CIPHER_EN	(1 << 2)	/* Cipher Enable */
+#define	TX_HDCP_CONTROL_READ_AKSV	(1 << 1)	/* Read AKSV */
+/* Bit(s) TX_HDCP_CONTROL_RSRV_0 reserved */
+
+/* TX_HDCP_STATUS_1 0x1351 HDCP Status Register 1 */
+#define	TX_HDCP_STATUS_1_BKSV_READY	(1 << 7)	/* BKSV Ready */
+/* R0 Authentication Passed */
+#define	TX_HDCP_STATUS_1_R0_AUTH_PASS	(1 << 6)
+/* KSV List Check Passed */
+#define	TX_HDCP_STATUS_1_KSV_LIST_CHECK_PASS	(1 << 5)
+#define	TX_HDCP_STATUS_1_ERR	(1 << 4)	/* Error */
+#define	TX_HDCP_STATUS_1_FW_ENC_EN	(1 << 3)	/* FW Encryption Enable */
+#define	TX_HDCP_STATUS_1_READY_KEYS	(1 << 2)	/* Ready Keys */
+#define	TX_HDCP_STATUS_1_AKSV_SENT	(1 << 1)	/* AKSV Sent */
+/* Bit(s) TX_HDCP_STATUS_1_RSRV_0 reserved */
+
+/* TX_HDCP_STATUS_2 0x1352 HDCP Status Register 2 */
+/* Video Mode [1_0] */
+#define	TX_HDCP_STATUS_2_VIDEO_MODE_1_0_MSK	((0x3) << 6)
+#define	TX_HDCP_STATUS_2_VIDEO_MODE_1_0_BASE	6
+/* Bit(s) TX_HDCP_STATUS_2_RSRV_5_0 reserved */
+
+/* TX_HDCP_INTR_0 0x1353 HDCP Interrupt Register */
+#define	TX_HDCP_INTR_0_AKSV_READY_STATUS	(1 << 7)		/* AKSV Ready Status */
+#define	TX_HDCP_INTR_0_TX_AN_READY_STATUS	(1 << 6)		/* Tx An Ready Status */
+#define	TX_HDCP_INTR_0_TX_R0_READY_STATUS	(1 << 5)		/* Tx R0 Ready Status */
+#define	TX_HDCP_INTR_0_TX_RI_READY_STATUS	(1 << 4)		/* Tx Ri Ready Status */
+#define	TX_HDCP_INTR_0_TX_PJ_READY_STATUS	(1 << 3)		/* Tx Pj Ready Status */
+/* Bit(s) TX_HDCP_INTR_0_RSRV_2_0 reserved */
+
+/* TX_HDCP_TX_AKSV_0 0x1354 TX KSV Byte 0 Register */
+/* TX_AKSV0 [7_0] */
+#define	TX_HDCP_TX_AKSV_0_TX_AKSV0_7_0_MSK	(0xff)
+#define	TX_HDCP_TX_AKSV_0_TX_AKSV0_7_0_BASE	0
+
+/* TX_HDCP_TX_AKSV_1 0x1355 TX KSV Byte 1 Register */
+/* TX_AKSV0 [15_8] */
+#define	TX_HDCP_TX_AKSV_1_TX_AKSV0_15_8_MSK	(0xff)
+#define	TX_HDCP_TX_AKSV_1_TX_AKSV0_15_8_BASE	0
+
+/* TX_HDCP_TX_AKSV_2 0x1356 TX KSV Byte 2 Register */
+/* TX_AKSV0 [23_16] */
+#define	TX_HDCP_TX_AKSV_2_TX_AKSV0_23_16_MSK	(0xff)
+#define	TX_HDCP_TX_AKSV_2_TX_AKSV0_23_16_BASE	0
+
+/* TX_HDCP_TX_AKSV_3 0x1357 TX KSV Byte 3 Register */
+/* TX_AKSV0 [31_24] */
+#define	TX_HDCP_TX_AKSV_3_TX_AKSV0_31_24_MSK	(0xff)
+#define	TX_HDCP_TX_AKSV_3_TX_AKSV0_31_24_BASE	0
+
+/* TX_HDCP_TX_AKSV_4 0x1358 TX KSV Byte 4 Register */
+/* TX_AKSV0 [39_32] */
+#define	TX_HDCP_TX_AKSV_4_TX_AKSV0_39_32_MSK	(0xff)
+#define	TX_HDCP_TX_AKSV_4_TX_AKSV0_39_32_BASE	0
+
+/* TX_HDCP_RX_BKSV_0 0x135C RX KSV Byte 0 Register */
+/* RX_BKSV0 [7_0] */
+#define	TX_HDCP_RX_BKSV_0_RX_BKSV0_7_0_MSK	(0xff)
+#define	TX_HDCP_RX_BKSV_0_RX_BKSV0_7_0_BASE	0
+
+/* TX_HDCP_RX_BKSV_1 0x135D RX KSV Byte 1 Register */
+/* RX_BKSV0 [15_8] */
+#define	TX_HDCP_RX_BKSV_1_RX_BKSV0_15_8_MSK	(0xff)
+#define	TX_HDCP_RX_BKSV_1_RX_BKSV0_15_8_BASE	0
+
+/* TX_HDCP_RX_BKSV_2 0x135E RX KSV Byte 2 Register */
+/* RX_BKSV0 [23_16] */
+#define	TX_HDCP_RX_BKSV_2_RX_BKSV0_23_16_MSK	(0xff)
+#define	TX_HDCP_RX_BKSV_2_RX_BKSV0_23_16_BASE	0
+
+/* TX_HDCP_RX_BKSV_3 0x135F RX KSV Byte 3 Register */
+/* RX_BKSV0 [31_24] */
+#define	TX_HDCP_RX_BKSV_3_RX_BKSV0_31_24_MSK	(0xff)
+#define	TX_HDCP_RX_BKSV_3_RX_BKSV0_31_24_BASE	0
+
+/* TX_HDCP_RX_BKSV_4 0x1360 RX KSV Byte 4 Register */
+/* RX_BKSV0 [39_32] */
+#define	TX_HDCP_RX_BKSV_4_RX_BKSV0_39_32_MSK	(0xff)
+#define	TX_HDCP_RX_BKSV_4_RX_BKSV0_39_32_BASE	0
+
+/* TX_HDCP_TX_AINFO 0x1361 Tx AINFO Register */
+#define	TX_HDCP_TX_AINFO_AINFO_7_2_MSK	((0x3f) << 2)	/* ainfo [7_2] */
+#define	TX_HDCP_TX_AINFO_AINFO_7_2_BASE	2
+/* ENABLE_1.1_FEATURES */
+#define	TX_HDCP_TX_AINFO_AINFO_b1	(1 << 1)
+#define	TX_HDCP_TX_AINFO_AINFO_b0	1			/* ainfo[0] */
+
+/* TX_HDCP_RX_BCAPS 0x1362 BCAPS Read from HDMI Rx Register */
+#define	TX_HDCP_RX_BCAPS_BCAPS_b7	(1 << 7)		/* bcaps[7] */
+/* REPEATER, HDCP Repeater Capability */
+#define	TX_HDCP_RX_BCAPS_BCAPS_b6	(1 << 6)
+/* READY, KSV FIFO Ready */
+#define	TX_HDCP_RX_BCAPS_BCAPS_b5	(1 << 5)
+#define	TX_HDCP_RX_BCAPS_BCAPS_b4	(1 << 4)		/* FAST */
+#define	TX_HDCP_RX_BCAPS_BCAPS_3_2_MSK	((0x3) << 2)	/* bcaps[3_2] */
+#define	TX_HDCP_RX_BCAPS_BCAPS_3_2_BASE	2
+#define	TX_HDCP_RX_BCAPS_BCAPS_b1	(1 << 1)		/* 1.1_FEATURES */
+/* FAST_REAUTHENTICATION */
+#define	TX_HDCP_RX_BCAPS_BCAPS_b0	1
+
+/* TX_HDCP_RX_BSTATUS_0	0x1364 BSTATUS MSB Byte Read from HDMI Rx Register */
+/* bstatus[15_14] */
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_15_14_MSK	((0x3) << 6)
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_15_14_BASE	6
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_b13	(1 << 5)		/* bstatus[13] */
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_b12	(1 << 4)		/* HDMI Mode */
+/* Topology Error Indicator */
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_b11	(1 << 3)
+/* Three-bit Repeater Cascade Depth */
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_10_8_MSK	(0x7)
+#define	TX_HDCP_RX_BSTATUS_0_BSTATUS_10_8_BASE	0
+
+/* TX_HDCP_RX_BSTATUS_1	0x1365 BSTATUS LSB Byte Read from HDMI Rx Register */
+/* Topology Error Indicator */
+#define	TX_HDCP_RX_BSTATUS_1_BSTATUS_b7	(1 << 7)
+/* Total Number of Attached Downstream Devices */
+#define	TX_HDCP_RX_BSTATUS_1_BSTATUS_6_0_MSK	(0x7f)
+#define	TX_HDCP_RX_BSTATUS_1_BSTATUS_6_0_BASE	0
+
+/* TX_HDCP_TX_AN_0 0x1368 HDCP Tx AN Value (Byte 0) Register */
+/* HDCP Tx AN Value [7_0] */
+#define	TX_HDCP_TX_AN_0_AN_7_0_MSK	(0xff)
+#define	TX_HDCP_TX_AN_0_AN_7_0_BASE	0
+
+/* TX_HDCP_TX_AN_1 0x1369 HDCP Tx AN Value (Byte 1) Register */
+/* HDCP Tx AN Value [15_8] */
+#define	TX_HDCP_TX_AN_1_AN_15_8_MSK	(0xff)
+#define	TX_HDCP_TX_AN_1_AN_15_8_BASE	0
+
+/* TX_HDCP_TX_AN_2 0x136A HDCP Tx AN Value (Byte 2) Register */
+/* HDCP Tx AN Value [23_16] */
+#define	TX_HDCP_TX_AN_2_AN_23_16_MSK	(0xff)
+#define	TX_HDCP_TX_AN_2_AN_23_16_BASE	0
+
+/* TX_HDCP_TX_AN_3 0x163B HDCP Tx AN Value (Byte 3) Register */
+/* HDCP Tx AN Value [31_24] */
+#define	TX_HDCP_TX_AN_3_AN_31_24_MSK	(0xff)
+#define	TX_HDCP_TX_AN_3_AN_31_24_BASE	0
+
+/* TX_HDCP_TX_AN_4 0x163C HDCP Tx AN Value (Byte 4) Register */
+/* HDCP Tx AN Value [39_32] */
+#define	TX_HDCP_TX_AN_4_AN_39_32_MSK	(0xff)
+#define	TX_HDCP_TX_AN_4_AN_39_32_BASE	0
+
+/* TX_HDCP_TX_AN_5 0x163D HDCP Tx AN Value (Byte 5) Register */
+/* HDCP Tx AN Value [47_40] */
+#define	TX_HDCP_TX_AN_5_AN_47_40_MSK	(0xff)
+#define	TX_HDCP_TX_AN_5_AN_47_40_BASE	0
+
+/* TX_HDCP_TX_AN_6 0x163E HDCP Tx AN Value (Byte 6) Register */
+/* HDCP Tx AN Value [55_48] */
+#define	TX_HDCP_TX_AN_6_AN_55_48_MSK	(0xff)
+#define	TX_HDCP_TX_AN_6_AN_55_48_BASE	0
+
+/* TX_HDCP_TX_AN_7 0x163F HDCP Tx AN Value (Byte 7) Register */
+/* HDCP Tx AN Value [63_56] */
+#define	TX_HDCP_TX_AN_7_AN_63_56_MSK	(0xff)
+#define	TX_HDCP_TX_AN_7_AN_63_56_BASE	0
+
+/* TX_HDCP_TX_M0_0 0x1370 HDCP Tx M0 Value (Byte 0) Register */
+/* HDCP Tx M0 Value [7_0] */
+#define	TX_HDCP_TX_M0_0_M0_7_0_MSK	(0xff)
+#define	TX_HDCP_TX_M0_0_M0_7_0_BASE	0
+
+/* TX_HDCP_TX_M0_1 0x1371 HDCP Tx M0 Value (Byte 1) Register */
+/* HDCP Tx M0 Value [15_8] */
+#define	TX_HDCP_TX_M0_1_M0_15_8_MSK	(0xff)
+#define	TX_HDCP_TX_M0_1_M0_15_8_BASE	0
+
+/* TX_HDCP_TX_M0_2 0x1372 HDCP Tx M0 Value (Byte 2) Register */
+/* HDCP Tx M0 Value [23_16] */
+#define	TX_HDCP_TX_M0_2_M0_23_16_MSK	(0xff)
+#define	TX_HDCP_TX_M0_2_M0_23_16_BASE	0
+
+/* TX_HDCP_TX_M0_3 0x1373 HDCP Tx M0 Value (Byte 3) Register */
+/* HDCP Tx M0 Value [31_24] */
+#define	TX_HDCP_TX_M0_3_M0_31_24_MSK	(0xff)
+#define	TX_HDCP_TX_M0_3_M0_31_24_BASE	0
+
+/* TX_HDCP_TX_M0_4 0x1374 HDCP Tx M0 Value (Byte 4) Register */
+/* HDCP Tx M0 Value [39_32] */
+#define	TX_HDCP_TX_M0_4_M0_39_32_MSK	(0xff)
+#define	TX_HDCP_TX_M0_4_M0_39_32_BASE	0
+
+/* TX_HDCP_TX_M0_5 0x1375 HDCP Tx M0 Value (Byte 5) Register */
+/* HDCP Tx M0 Value [47_40] */
+#define	TX_HDCP_TX_M0_5_M0_47_40_MSK	(0xff)
+#define	TX_HDCP_TX_M0_5_M0_47_40_BASE	0
+
+/* TX_HDCP_TX_M0_6 0x1376 HDCP Tx M0 Value (Byte 6) Register */
+/* HDCP Tx M0 Value [55_48] */
+#define	TX_HDCP_TX_M0_6_M0_55_48_MSK	(0xff)
+#define	TX_HDCP_TX_M0_6_M0_55_48_BASE	0
+
+/* TX_HDCP_TX_M0_7 0x1377 HDCP Tx M0 Value (Byte 7) Register */
+/* HDCP Tx M0 Value [63_56] */
+#define	TX_HDCP_TX_M0_7_M0_63_56_MSK	(0xff)
+#define	TX_HDCP_TX_M0_7_M0_63_56_BASE	0
+
+/* TX_HDCP_TX_R0_0 0x1378 Tx R0 (Byte 0) Register */
+#define	TX_HDCP_TX_R0_0_TX_R0_7_0_MSK	(0xff)	/* Tx R0 [7_0] */
+#define	TX_HDCP_TX_R0_0_TX_R0_7_0_BASE	0
+
+/* TX_HDCP_TX_R0_1 0x1379 Tx R0 (Byte 1) Register */
+#define	TX_HDCP_TX_R0_1_TX_R0_15_8_MSK	(0xff)	/* Tx R0 [15_8] */
+#define	TX_HDCP_TX_R0_1_TX_R0_15_8_BASE	0
+
+/* TX_HDCP_RX_R0_0 0x137A Rx R0 (Byte 0) Register */
+#define	TX_HDCP_RX_R0_0_RX_R0_7_0_MSK	(0xff)	/* Rx R0 [7_0] */
+#define	TX_HDCP_RX_R0_0_RX_R0_7_0_BASE	0
+
+/* TX_HDCP_RX_R0_1 0x137B Rx R0 (Byte 1) Register */
+#define	TX_HDCP_RX_R0_1_RX_R0_15_8_MSK	(0xff)	/* Rx R0 [15_8] */
+#define	TX_HDCP_RX_R0_1_RX_R0_15_8_BASE	0
+
+/* TX_HDCP_TX_RI_0 0x137C Tx RI (Byte 0) Register */
+#define	TX_HDCP_TX_RI_0_TX_RI_7_0_MSK	(0xff)	/* Tx RI [7_0] */
+#define	TX_HDCP_TX_RI_0_TX_RI_7_0_BASE	0
+
+/* TX_HDCP_TX_RI_1 0x137D Rx RI (Byte 1) Register */
+#define	TX_HDCP_TX_RI_1_TX_RI_15_8_MSK	(0xff)	/* Tx RI [15_8] */
+#define	TX_HDCP_TX_RI_1_TX_RI_15_8_BASE	0
+
+/* TX_HDCP_RX_RI_0 0x137E Rx RI (Byte 0) Register */
+#define	TX_HDCP_RX_RI_0_RX_RI_7_0_MSK	(0xff)	/* Rx RI [7_0] */
+#define	TX_HDCP_RX_RI_0_RX_RI_7_0_BASE	0
+
+/* TX_HDCP_RX_RI_1 0x137F Rx RI (Byte 1) Register */
+#define	TX_HDCP_RX_RI_1_RX_RI_15_8_MSK	(0xff)	/* Rx RI [15_8] */
+#define	TX_HDCP_RX_RI_1_RX_RI_15_8_BASE	0
+
+/* TX_HDCP_TX_PJ 0x1380	Tx PJ Register */
+#define	TX_HDCP_TX_PJ_TX_PJ_MSK	(0xff)	/* Tx PJ */
+#define	TX_HDCP_TX_PJ_TX_PJ_BASE	0
+
+/* TX_HDCP_RX_PJ 0x1381	Rx PJ Register */
+#define	TX_HDCP_RX_PJ_RX_PJ_MSK	(0xff)	/* Rx PJ */
+#define	TX_HDCP_RX_PJ_RX_PJ_BASE	0
+
+/* TX_HDCP_FIX_CLR_0 0x1384 Default Video Value (Byte 0) Register */
+/* Default Video Value [7_0] */
+#define	TX_HDCP_FIX_CLR_0_FIX_CLR_7_0_MSK	(0xff)
+#define	TX_HDCP_FIX_CLR_0_FIX_CLR_7_0_BASE	0
+
+/* TX_HDCP_FIX_CLR_1 0x1385 Default Video Value (Byte 1) Register */
+/* Default Video Value [15_8] */
+#define	TX_HDCP_FIX_CLR_1_FIX_CLR_15_8_MSK	(0xff)
+#define	TX_HDCP_FIX_CLR_1_FIX_CLR_15_8_BASE	0
+
+/* TX_HDCP_FIX_CLR_2 0x1386 Default Video Value (Byte 2) Register */
+/* Default Video Value [23_16] */
+#define	TX_HDCP_FIX_CLR_2_FIX_CLR_23_16_MSK	(0xff)
+#define	TX_HDCP_FIX_CLR_2_FIX_CLR_23_16_BASE	0
+
+/* TX_HDCP_KINIT_0 0x1388 KINIT (Byte 0) Register */
+#define	TX_HDCP_KINIT_0_KINIT_7_0_MSK	(0xff)	/* KINIT [7_0] */
+#define	TX_HDCP_KINIT_0_KINIT_7_0_BASE	0
+
+/* TX_HDCP_KINIT_1 0x1389 KINIT (Byte 1) Register */
+#define	TX_HDCP_KINIT_1_KINIT_15_8_MSK	(0xff)	/* KINIT [15_8] */
+#define	TX_HDCP_KINIT_1_KINIT_15_8_BASE	0
+
+/* TX_HDCP_KINIT_2 0x138A KINIT (Byte 2) Register */
+#define	TX_HDCP_KINIT_2_KINIT_23_16_MSK	(0xff)	/* KINIT [23_16] */
+#define	TX_HDCP_KINIT_2_KINIT_23_16_BASE	0
+
+/* TX_HDCP_KINIT_3 0x138B KINIT (Byte 3) Register */
+#define	TX_HDCP_KINIT_3_KINIT_31_24_MSK	(0xff)	/* KINIT [31_24] */
+#define	TX_HDCP_KINIT_3_KINIT_31_24_BASE	0
+
+/* TX_HDCP_KINIT_4 0x138C KINIT (Byte 4) Register */
+#define	TX_HDCP_KINIT_4_KINIT_39_32_MSK	(0xff)	/* KINIT [39_32] */
+#define	TX_HDCP_KINIT_4_KINIT_39_32_BASE	0
+/* TX_HDCP_KINIT_5 0x138D KINIT (Byte 5) Register */
+#define	TX_HDCP_KINIT_5_KINIT_47_40_MSK	(0xff)	/* KINIT [47_40] */
+#define	TX_HDCP_KINIT_5_KINIT_47_40_BASE	0
+/* TX_HDCP_KINIT_6 0x138E KINIT (Byte 6) Register */
+#define	TX_HDCP_KINIT_6_KINIT_55_48_MSK	(0xff)	/* KINIT [55_48] */
+#define	TX_HDCP_KINIT_6_KINIT_55_48_BASE	0
+
+/* TX_HDCP_BINIT_0 0x1390 BINIT (Byte 0) Register */
+#define	TX_HDCP_BINIT_0_BINIT_7_0_MSK		(0xff)	/* BINIT [7_0] */
+#define	TX_HDCP_BINIT_0_BINIT_7_0_BASE		0
+
+/* TX_HDCP_BINIT_1 0x1391 BINIT (Byte 1) Register */
+#define	TX_HDCP_BINIT_1_BINIT_15_8_MSK	(0xff)	/* BINIT[15_8] */
+#define	TX_HDCP_BINIT_1_BINIT_15_8_BASE	0
+
+/* TX_HDCP_BINIT_2 0x1392 BINIT (Byte 2) Register */
+#define	TX_HDCP_BINIT_2_BINIT_23_16_MSK	(0xff)	/* BINIT [23_16] */
+#define	TX_HDCP_BINIT_2_BINIT_23_16_BASE	0
+
+/* TX_HDCP_BINIT_3 0x1393 BINIT (Byte 3) Register */
+#define	TX_HDCP_BINIT_3_BINIT_31_24_MSK	(0xff)	/* BINIT[31_24] */
+#define	TX_HDCP_BINIT_3_BINIT_31_24_BASE	0
+
+/* TX_HDCP_BINIT_4 0x1394 BINIT (Byte 4) Register */
+#define	TX_HDCP_BINIT_4_BINIT_39_32_MSK	(0xff)	/* BINIT [39_32] */
+#define	TX_HDCP_BINIT_4_BINIT_39_32_BASE	0
+
+/* TX_HDCP_BINIT_5 0x1395 BINIT (Byte 5) Register */
+#define	TX_HDCP_BINIT_5_BINIT_47_40_MSK	(0xff)	/* BINIT [47_40] */
+#define	TX_HDCP_BINIT_5_BINIT_47_40_BASE	0
+
+/* TX_HDCP_BINIT_6 0x1396 BINIT (Byte 6) Register */
+#define	TX_HDCP_BINIT_6_BINIT_55_48_MSK	(0xff)	/* BINIT [55_48] */
+#define	TX_HDCP_BINIT_6_BINIT_55_48_BASE	0
+
+/* TX_HDCP_BINIT_7 0x1397 BINIT (Byte 7) Register */
+#define	TX_HDCP_BINIT_7_BINIT_63_56_MSK	(0xff)	/* BINIT [63_56] */
+#define	TX_HDCP_BINIT_7_BINIT_63_56_BASE	0
+
+/* TX_HDCP_INTR_CLR 0x1398 Interrupt Clear Register */
+#define	TX_HDCP_INTR_CLR_AKSV_READY_CLR		(1 << 7)	/* AKSV Ready Clear */
+#define	TX_HDCP_INTR_CLR_TX_AN_READY_CLR	(1 << 6)	/* Tx An Ready Clear */
+#define	TX_HDCP_INTR_CLR_TX_R0_READY_CLR	(1 << 5)	/* Tx R0 Ready Clear */
+#define	TX_HDCP_INTR_CLR_TX_RI_READY_CLR	(1 << 4)	/* Tx Ri Ready Clear */
+#define	TX_HDCP_INTR_CLR_TX_PJ_READY_CLR	(1 << 3)	/* Tx Pj Ready Clear */
+/* Bit(s) TX_HDCP_INTR_CLR_RSRV_2_0 reserved */
+
+/* TX_HDCP_INTR_MASK 0x1399 Interrupt Masking Register */
+#define	TX_HDCP_INTR_MASK_AKSV_READY_MASK	(1 << 7)	/* AKSV Ready Mask */
+#define	TX_HDCP_INTR_MASK_TX_AN_READY_MASK	(1 << 6)	/* Tx An Ready Mask */
+#define	TX_HDCP_INTR_MASK_TX_R0_READY_MASK	(1 << 5)	/* Tx R0 Ready Mask */
+#define	TX_HDCP_INTR_MASK_TX_RI_READY_MASK	(1 << 4)	/* Tx Ri Ready Mask */
+#define	TX_HDCP_INTR_MASK_TX_PJ_READY_MASK	(1 << 3)	/* Tx Pj Ready Mask */
+
+#define HDMI_PLL_FREQ_25MHz	25
+#define HDMI_PLL_FREQ_27MHz	27
+#define HDMI_PLL_FREQ_54MHz	54
+#define HDMI_PLL_FREQ_74MHz	74
+#define HDMI_PLL_FREQ_108MHz	108
+#define HDMI_PLL_FREQ_148MHz	148
+#define	HDMI_MODE	HDTX_HDMI_CTRL_HDMI_MODE
+#define BASE_OFFSET 0xc00
+#define HDMI_DATA 0x0
+#define HDMI_ADDR 0x4
+
+#define MAP_MEM_SIZE "/sys/class/uio/uio1/maps/map0/size"
+#define HDMI_UIO "/dev/uio1"
+extern unsigned *hdmi_base;
+// HDMI-TX registers
+//-----------AUDIO---------------
+#define HDTX_ACR_N0            0x0000 //FF
+#define HDTX_ACR_N1            0x0001 //FF
+#define HDTX_ACR_N2            0x0002 //0F
+#define HDTX_ACR_CTS0          0x0004 //FF
+#define HDTX_ACR_CTS1          0x0005 //FF
+#define HDTX_ACR_CTS2          0x0006 //0F
+#define HDTX_ACR_CTRL          0x0007 //0F
+#define HDTX_ACR_STS0          0x0008
+#define HDTX_ACR_STS1          0x0009
+#define HDTX_ACR_STS2          0x000A
+#define HDTX_AUD_CTRL          0x000B //FF
+#define HDTX_I2S_CTRL          0x000C //1F
+#define HDTX_I2S_DLEN          0x000D //1F
+#define HDTX_I2S_DBG_LFT0      0x0010 //FF
+#define HDTX_I2S_DBG_LFT1      0x0011 //FF
+#define HDTX_I2S_DBG_LFT2      0x0012 //FF
+#define HDTX_I2S_DBG_LFT3      0x0013 //FF
+#define HDTX_I2S_DBG_RIT0      0x0014 //FF
+#define HDTX_I2S_DBG_RIT1      0x0015 //FF
+#define HDTX_I2S_DBG_RIT2      0x0016 //FF
+#define HDTX_I2S_DBG_RIT3      0x0017 //FF
+#define HDTX_CHSTS_0           0x0018 //FF
+#define HDTX_CHSTS_1           0x0019 //FF
+#define HDTX_CHSTS_2           0x001A //FF
+#define HDTX_CHSTS_3           0x001B //FF
+#define HDTX_CHSTS_4           0x001C //FF
+#define HDTX_FIFO_CTRL         0x001D //03
+#define HDTX_MEMSIZE_L         0x001E //FF
+#define HDTX_MEMSIZE_H         0x001F //01
+#define HDTX_GCP_CFG0          0x0020 //0F
+#define HDTX_GCP_CFG1          0x0021 //FF
+#define HDTX_AUD_STS           0x0022
+//-----------VIDEO --------------
+#define HDTX_HTOT_L            0x0024 //FF
+#define HDTX_HTOT_H            0x0025 //FF
+#define HDTX_HBLANK_L          0x0026 //FF
+#define HDTX_HBLANK_H          0x0027 //FF
+#define HDTX_VTOT_L            0x0028 //FF
+#define HDTX_VTOT_H            0x0029 //FF
+#define HDTX_VRES_L            0x002A //FF
+#define HDTX_VRES_H            0x002B //FF
+#define HDTX_VSTART_L          0x002C //FF
+#define HDTX_VSTART_H          0x002D //FF
+#define HDTX_HTOT_STS_L        0x002E
+#define HDTX_HTOT_STS_H        0x002F
+#define HDTX_HBLANK_STS_L      0x0030
+#define HDTX_HBLANK_STS_H      0x0031
+#define HDTX_VTOT_STS_L        0x0032
+#define HDTX_VTOT_STS_H        0x0033
+#define HDTX_VRES_STS_L        0x0034
+#define HDTX_VRES_STS_H        0x0035
+#define HDTX_VSTART_STS_L      0x0036
+#define HDTX_VSTART_STS_H      0x0037
+#define HDTX_VIDEO_STS         0x0038
+#define HDTX_VIDEO_CTRL        0x0039 //7F
+#define HDTX_HDMI_CTRL         0x003A //FF
+//-----------------------------
+// DDC - NOT USED -CAN BE REMOVED
+//------_-----------------------
+//#define HDMI_EDDC_CTRL         0x103B //NOT NEEDED
+//#define HDMI_EDDC_DEV_ID       0x103C //NOT NEEDED
+//#define HDMI_EDDC_DEV_OFF      0x103D //NOT NEEDED
+//#define HDMI_EDDC_SEG_ADDR     0x103E //NOT NEEDED
+//#define HDMI_EDDC_CMD          0x103F //NOT NEEDED
+//#define HDMI_EDDC_RW_CNT_L     0x1040 //NOT NEEDED
+//#define HDMI_EDDC_RW_CNT_H     0x1041 //NOT NEEDED
+//#define HDMI_EDDC_PERIOD       0x1042 //NOT NEEDED
+//#define HDMI_EDDC_RW_DATA      0x1043 //NOT NEEDED
+//#define HDMI_EDDC_STATUS       0x1044 //NOT NEEDED
+//#define HDMI_EDDC_SEG_PTR      0x1045 //NOT NEEDED
+
+#define HDTX_PP_HW             0x0046
+
+//-----------------------------
+// DEEP COLOR
+//------_-----------------------
+#define HDTX_DC_FIFO_SFT_RST   0x0047 //01
+#define HDTX_DC_FIFO_WR_PTR    0x0048 //3F
+#define HDTX_DC_FIFO_RD_PTR    0x0049 //3F
+#define HDTX_DC_PP_CTRL        0x004A //01
+
+//-------------------------------
+// HDMI_TX PHY GLUE LOGIC
+//-------------------------------
+#define HDTX_TDATA0_0          0x004C //FF
+#define HDTX_TDATA0_1          0x004D //FF
+#define HDTX_TDATA0_2          0x004E //0F
+#define HDTX_TDATA1_0          0x0050 //FF
+#define HDTX_TDATA1_1          0x0051 //FF
+#define HDTX_TDATA1_2          0x0052 //0F
+#define HDTX_TDATA2_0          0x0054 //FF
+#define HDTX_TDATA2_1          0x0055 //FF
+#define HDTX_TDATA2_2          0x0056 //0F
+#define HDTX_TDATA3_0          0x0058 //FF
+#define HDTX_TDATA3_1          0x0059 //FF
+#define HDTX_TDATA3_2          0x005A //0F
+#define HDTX_TDATA_SEL         0x005B //7F
+#define HDTX_SWAP_CTRL         0x005C //03
+
+#define HDTX_AVMUTE_CTRL       0x005D //03
+
+#define HDTX_HST_PKT_CTRL0     0x005E //3F
+#define HDTX_HST_PKT_CTRL1     0x005F //3F
+//-----------------------------
+#define HDTX_PKT0_BYTE0        0x0060 //FF
+#define HDTX_PKT0_BYTE1        0x0061 //FF
+#define HDTX_PKT0_BYTE2        0x0062 //FF
+#define HDTX_PKT0_BYTE3        0x0063 //FF
+#define HDTX_PKT0_BYTE4        0x0064 //FF
+#define HDTX_PKT0_BYTE5        0x0065 //FF
+#define HDTX_PKT0_BYTE6        0x0066 //FF
+#define HDTX_PKT0_BYTE7        0x0067 //FF
+#define HDTX_PKT0_BYTE8        0x0068 //FF
+#define HDTX_PKT0_BYTE9        0x0069 //FF
+#define HDTX_PKT0_BYTE10       0x006A //FF
+#define HDTX_PKT0_BYTE11       0x006B //FF
+#define HDTX_PKT0_BYTE12       0x006C //FF
+#define HDTX_PKT0_BYTE13       0x006D //FF
+#define HDTX_PKT0_BYTE14       0x006E //FF
+#define HDTX_PKT0_BYTE15       0x006F //FF
+#define HDTX_PKT0_BYTE16       0x0070 //FF
+#define HDTX_PKT0_BYTE17       0x0071 //FF
+#define HDTX_PKT0_BYTE18       0x0072 //FF
+#define HDTX_PKT0_BYTE19       0x0073 //FF
+#define HDTX_PKT0_BYTE20       0x0074 //FF
+#define HDTX_PKT0_BYTE21       0x0075 //FF
+#define HDTX_PKT0_BYTE22       0x0076 //FF
+#define HDTX_PKT0_BYTE23       0x0077 //FF
+#define HDTX_PKT0_BYTE24       0x0078 //FF
+#define HDTX_PKT0_BYTE25       0x0079 //FF
+#define HDTX_PKT0_BYTE26       0x007A //FF
+#define HDTX_PKT0_BYTE27       0x007B //FF
+#define HDTX_PKT0_BYTE28       0x007C //FF
+#define HDTX_PKT0_BYTE29       0x007D //FF
+#define HDTX_PKT0_BYTE30       0x007E //FF
+//-----------------------------
+#define HDTX_PKT1_BYTE0        0x0080 //FF
+#define HDTX_PKT1_BYTE1        0x0081 //FF
+#define HDTX_PKT1_BYTE2        0x0082 //FF
+#define HDTX_PKT1_BYTE3        0x0083 //FF
+#define HDTX_PKT1_BYTE4        0x0084 //FF
+#define HDTX_PKT1_BYTE5        0x0085 //FF
+#define HDTX_PKT1_BYTE6        0x0086 //FF
+#define HDTX_PKT1_BYTE7        0x0087 //FF
+#define HDTX_PKT1_BYTE8        0x0088 //FF
+#define HDTX_PKT1_BYTE9        0x0089 //FF
+#define HDTX_PKT1_BYTE10       0x008A //FF
+#define HDTX_PKT1_BYTE11       0x008B //FF
+#define HDTX_PKT1_BYTE12       0x008C //FF
+#define HDTX_PKT1_BYTE13       0x008D //FF
+#define HDTX_PKT1_BYTE14       0x008E //FF
+#define HDTX_PKT1_BYTE15       0x008F //FF
+#define HDTX_PKT1_BYTE16       0x0090 //FF
+#define HDTX_PKT1_BYTE17       0x0091 //FF
+#define HDTX_PKT1_BYTE18       0x0092 //FF
+#define HDTX_PKT1_BYTE19       0x0093 //FF
+#define HDTX_PKT1_BYTE20       0x0094 //FF
+#define HDTX_PKT1_BYTE21       0x0095 //FF
+#define HDTX_PKT1_BYTE22       0x0096 //FF
+#define HDTX_PKT1_BYTE23       0x0097 //FF
+#define HDTX_PKT1_BYTE24       0x0098 //FF
+#define HDTX_PKT1_BYTE25       0x0099 //FF
+#define HDTX_PKT1_BYTE26       0x009A //FF
+#define HDTX_PKT1_BYTE27       0x009B //FF
+#define HDTX_PKT1_BYTE28       0x009C //FF
+#define HDTX_PKT1_BYTE29       0x009D //FF
+#define HDTX_PKT1_BYTE30       0x009E //FF
+//-----------------------------
+#define HDTX_PKT2_BYTE0        0x00A0 //FF
+#define HDTX_PKT2_BYTE1        0x00A1 //FF
+#define HDTX_PKT2_BYTE2        0x00A2 //FF
+#define HDTX_PKT2_BYTE3        0x00A3 //FF
+#define HDTX_PKT2_BYTE4        0x00A4 //FF
+#define HDTX_PKT2_BYTE5        0x00A5 //FF
+#define HDTX_PKT2_BYTE6        0x00A6 //FF
+#define HDTX_PKT2_BYTE7        0x00A7 //FF
+#define HDTX_PKT2_BYTE8        0x00A8 //FF
+#define HDTX_PKT2_BYTE9        0x00A9 //FF
+#define HDTX_PKT2_BYTE10       0x00AA //FF
+#define HDTX_PKT2_BYTE11       0x00AB //FF
+#define HDTX_PKT2_BYTE12       0x00AC //FF
+#define HDTX_PKT2_BYTE13       0x00AD //FF
+#define HDTX_PKT2_BYTE14       0x00AE //FF
+#define HDTX_PKT2_BYTE15       0x00AF //FF
+#define HDTX_PKT2_BYTE16       0x00B0 //FF
+#define HDTX_PKT2_BYTE17       0x00B1 //FF
+#define HDTX_PKT2_BYTE18       0x00B2 //FF
+#define HDTX_PKT2_BYTE19       0x00B3 //FF
+#define HDTX_PKT2_BYTE20       0x00B4 //FF
+#define HDTX_PKT2_BYTE21       0x00B5 //FF
+#define HDTX_PKT2_BYTE22       0x00B6 //FF
+#define HDTX_PKT2_BYTE23       0x00B7 //FF
+#define HDTX_PKT2_BYTE24       0x00B8 //FF
+#define HDTX_PKT2_BYTE25       0x00B9 //FF
+#define HDTX_PKT2_BYTE26       0x00BA //FF
+#define HDTX_PKT2_BYTE27       0x00BB //FF
+#define HDTX_PKT2_BYTE28       0x00BC //FF
+#define HDTX_PKT2_BYTE29       0x00BD //FF
+#define HDTX_PKT2_BYTE30       0x00BE //FF
+//-----------------------------
+#define HDTX_PKT3_BYTE0        0x00C0 //FF
+#define HDTX_PKT3_BYTE1        0x00C1 //FF
+#define HDTX_PKT3_BYTE2        0x00C2 //FF
+#define HDTX_PKT3_BYTE3        0x00C3 //FF
+#define HDTX_PKT3_BYTE4        0x00C4 //FF
+#define HDTX_PKT3_BYTE5        0x00C5 //FF
+#define HDTX_PKT3_BYTE6        0x00C6 //FF
+#define HDTX_PKT3_BYTE7        0x00C7 //FF
+#define HDTX_PKT3_BYTE8        0x00C8 //FF
+#define HDTX_PKT3_BYTE9        0x00C9 //FF
+#define HDTX_PKT3_BYTE10       0x00CA //FF
+#define HDTX_PKT3_BYTE11       0x00CB //FF
+#define HDTX_PKT3_BYTE12       0x00CC //FF
+#define HDTX_PKT3_BYTE13       0x00CD //FF
+#define HDTX_PKT3_BYTE14       0x00CE //FF
+#define HDTX_PKT3_BYTE15       0x00CF //FF
+#define HDTX_PKT3_BYTE16       0x00D0 //FF
+#define HDTX_PKT3_BYTE17       0x00D1 //FF
+#define HDTX_PKT3_BYTE18       0x00D2 //FF
+#define HDTX_PKT3_BYTE19       0x00D3 //FF
+#define HDTX_PKT3_BYTE20       0x00D4 //FF
+#define HDTX_PKT3_BYTE21       0x00D5 //FF
+#define HDTX_PKT3_BYTE22       0x00D6 //FF
+#define HDTX_PKT3_BYTE23       0x00D7 //FF
+#define HDTX_PKT3_BYTE24       0x00D8 //FF
+#define HDTX_PKT3_BYTE25       0x00D9 //FF
+#define HDTX_PKT3_BYTE26       0x00DA //FF
+#define HDTX_PKT3_BYTE27       0x00DB //FF
+#define HDTX_PKT3_BYTE28       0x00DC //FF
+#define HDTX_PKT3_BYTE29       0x00DD //FF
+#define HDTX_PKT3_BYTE30       0x00DE //FF
+
+//-----------------------------
+#define HDTX_PKT4_BYTE0        0x00E0 //FF
+#define HDTX_PKT4_BYTE1        0x00E1 //FF
+#define HDTX_PKT4_BYTE2        0x00E2 //FF
+#define HDTX_PKT4_BYTE3        0x00E3 //FF
+#define HDTX_PKT4_BYTE4        0x00E4 //FF
+#define HDTX_PKT4_BYTE5        0x00E5 //FF
+#define HDTX_PKT4_BYTE6        0x00E6 //FF
+#define HDTX_PKT4_BYTE7        0x00E7 //FF
+#define HDTX_PKT4_BYTE8        0x00E8 //FF
+#define HDTX_PKT4_BYTE9        0x00E9 //FF
+#define HDTX_PKT4_BYTE10       0x00EA //FF
+#define HDTX_PKT4_BYTE11       0x00EB //FF
+#define HDTX_PKT4_BYTE12       0x00EC //FF
+#define HDTX_PKT4_BYTE13       0x00ED //FF
+#define HDTX_PKT4_BYTE14       0x00EE //FF
+#define HDTX_PKT4_BYTE15       0x00EF //FF
+#define HDTX_PKT4_BYTE16       0x00F0 //FF
+#define HDTX_PKT4_BYTE17       0x00F1 //FF
+#define HDTX_PKT4_BYTE18       0x00F2 //FF
+#define HDTX_PKT4_BYTE19       0x00F3 //FF
+#define HDTX_PKT4_BYTE20       0x00F4 //FF
+#define HDTX_PKT4_BYTE21       0x00F5 //FF
+#define HDTX_PKT4_BYTE22       0x00F6 //FF
+#define HDTX_PKT4_BYTE23       0x00F7 //FF
+#define HDTX_PKT4_BYTE24       0x00F8 //FF
+#define HDTX_PKT4_BYTE25       0x00F9 //FF
+#define HDTX_PKT4_BYTE26       0x00FA //FF
+#define HDTX_PKT4_BYTE27       0x00FB //FF
+#define HDTX_PKT4_BYTE28       0x00FC //FF
+#define HDTX_PKT4_BYTE29       0x00FD //FF
+#define HDTX_PKT4_BYTE30       0x00FE //FF
+//-----------------------------
+
+#define HDTX_PKT5_BYTE0        0x0100 //FF
+#define HDTX_PKT5_BYTE1        0x0101 //FF
+#define HDTX_PKT5_BYTE2        0x0102 //FF
+#define HDTX_PKT5_BYTE3        0x0103 //FF
+#define HDTX_PKT5_BYTE4        0x0104 //FF
+#define HDTX_PKT5_BYTE5        0x0105 //FF
+#define HDTX_PKT5_BYTE6        0x0106 //FF
+#define HDTX_PKT5_BYTE7        0x0107 //FF
+#define HDTX_PKT5_BYTE8        0x0108 //FF
+#define HDTX_PKT5_BYTE9        0x0109 //FF
+#define HDTX_PKT5_BYTE10       0x010A //FF
+#define HDTX_PKT5_BYTE11       0x010B //FF
+#define HDTX_PKT5_BYTE12       0x010C //FF
+#define HDTX_PKT5_BYTE13       0x010D //FF
+#define HDTX_PKT5_BYTE14       0x010E //FF
+#define HDTX_PKT5_BYTE15       0x010F //FF
+#define HDTX_PKT5_BYTE16       0x0110 //FF
+#define HDTX_PKT5_BYTE17       0x0111 //FF
+#define HDTX_PKT5_BYTE18       0x0112 //FF
+#define HDTX_PKT5_BYTE19       0x0113 //FF
+#define HDTX_PKT5_BYTE20       0x0114 //FF
+#define HDTX_PKT5_BYTE21       0x0115 //FF
+#define HDTX_PKT5_BYTE22       0x0116 //FF
+#define HDTX_PKT5_BYTE23       0x0117 //FF
+#define HDTX_PKT5_BYTE24       0x0118 //FF
+#define HDTX_PKT5_BYTE25       0x0119 //FF
+#define HDTX_PKT5_BYTE26       0x011A //FF
+#define HDTX_PKT5_BYTE27       0x011B //FF
+#define HDTX_PKT5_BYTE28       0x011C //FF
+#define HDTX_PKT5_BYTE29       0x011D //FF
+#define HDTX_PKT5_BYTE30       0x011E //FF
+#define HDTX_RSVD              0x011F
+
+//-----------------------------
+// NEW HDMI-TX REGISTERS
+//-----------------------------
+#define HDTX_UBITS_0           0x0120 //FF
+#define HDTX_UBITS_1           0x0121 //FF
+#define HDTX_UBITS_2           0x0122 //FF
+#define HDTX_UBITS_3           0x0123 //FF
+#define HDTX_UBITS_4           0x0124 //FF
+#define HDTX_UBITS_5           0x0125 //FF
+#define HDTX_UBITS_6           0x0126 //FF
+#define HDTX_UBITS_7           0x0127 //FF
+#define HDTX_UBITS_8           0x0128 //FF
+#define HDTX_UBITS_9           0x0129 //FF
+#define HDTX_UBITS_10          0x012A //FF
+#define HDTX_UBITS_11          0x012B //FF
+#define HDTX_UBITS_12          0x012C //FF
+#define HDTX_UBITS_13          0x012D //0F
+#define HDTX_HBR_PKT           0x012E //01
+
+#define HDTX_PHY_FIFO_SOFT_RST 0x0130 //01
+#define HDTX_PHY_FIFO_PTRS     0x0131 //FF
+#define HDTX_PRBS_CTRL0        0x0132 //07
+#define HDTX_HST_PKT_CTRL2     0x0133 //01
+#define HDTX_HST_PKT_START     0x0134 //01
+#define TX_HDCP_FRM_CNT        0x0135
+#define TX_HDCP_HPD_STS        0x0136
+#define HDTX_AUD_CH1_SEL       0x0137 //07
+#define HDTX_AUD_CH2_SEL       0x0138 //07
+#define HDTX_AUD_CH3_SEL       0x0139 //07
+#define HDTX_AUD_CH4_SEL       0x013A //07
+#define HDTX_AUD_CH5_SEL       0x013B //07
+#define HDTX_AUD_CH6_SEL       0x013C //07
+#define HDTX_AUD_CH7_SEL       0x013D //07
+#define HDTX_AUD_CH8_SEL       0x013E //07
+#define TX_HDCP_HW_STATUS      0x013F
+#define TX_HDCP_HPD_SEL        0x0140 //01
+#define TX_HDCP_SW_HPD         0x0141 //01
+
+// --  CEC
+
+#define CEC_BASE 0x200
+
+#define CEC_TOGGLE_FOR_WRITE_REG_ADDR        CEC_BASE + 0x0000
+#define CEC_TOGGLE_FOR_READ_REG_ADDR         CEC_BASE + 0x0004
+#define CEC_RDY_ADDR                         CEC_BASE + 0x0008 //01
+#define CEC_RX_RDY_ADDR                      CEC_BASE + 0x000c //01
+#define CEC_TX_FIFO_RESET_ADDR               CEC_BASE + 0x0010 //03
+#define CEC_RX_FIFO_RESET_ADDR               CEC_BASE + 0x0014 //03
+#define CEC_PMODE_ADDR                       CEC_BASE + 0x0018 //01
+//#define CEC_TX_RDY_ADDR                      CEC_BASE + 0x001c //01
+#define CEC_TX_TYPE_ADDR                     CEC_BASE + 0x0020 //01
+//#define CEC_TX_RESP_TIME_0_ADDR              CEC_BASE + 0x0024 //FF
+//#define CEC_TX_RESP_TIME_1_ADDR              CEC_BASE + 0x0025 //FF
+//#define CEC_TX_RESP_TIME_2_ADDR              CEC_BASE + 0x0026 //FF
+//#define CEC_TX_RESP_TIME_3_ADDR              CEC_BASE + 0x0027 //FF
+#define CEC_SIGNAL_FREE_TIME_0_ADDR          CEC_BASE + 0x0028 //FF
+#define CEC_SIGNAL_FREE_TIME_1_ADDR          CEC_BASE + 0x0029 //FF
+#define CEC_SIGNAL_FREE_TIME_2_ADDR          CEC_BASE + 0x002a //FF
+#define CEC_SIGNAL_FREE_TIME_3_ADDR          CEC_BASE + 0x002b //FF
+#define CEC_START_BIT_LO_THRESH_0_ADDR       CEC_BASE + 0x002c //FF
+#define CEC_START_BIT_LO_THRESH_1_ADDR       CEC_BASE + 0x002d //FF
+#define CEC_START_BIT_LO_THRESH_2_ADDR       CEC_BASE + 0x002e //FF
+#define CEC_START_BIT_LO_THRESH_3_ADDR       CEC_BASE + 0x002f //FF
+#define CEC_START_BIT_HI_THRESH_0_ADDR       CEC_BASE + 0x0030 //FF
+#define CEC_START_BIT_HI_THRESH_1_ADDR       CEC_BASE + 0x0031 //FF
+#define CEC_START_BIT_HI_THRESH_2_ADDR       CEC_BASE + 0x0032 //FF
+#define CEC_START_BIT_HI_THRESH_3_ADDR       CEC_BASE + 0x0033 //FF
+#define CEC_DATA_BIT_0_LO_THRESH_0_ADDR      CEC_BASE + 0x0034 //FF
+#define CEC_DATA_BIT_0_LO_THRESH_1_ADDR      CEC_BASE + 0x0035 //FF
+#define CEC_DATA_BIT_0_LO_THRESH_2_ADDR      CEC_BASE + 0x0036 //FF
+#define CEC_DATA_BIT_0_LO_THRESH_3_ADDR      CEC_BASE + 0x0037 //FF
+#define CEC_DATA_BIT_1_LO_THRESH_0_ADDR      CEC_BASE + 0x0038 //FF
+#define CEC_DATA_BIT_1_LO_THRESH_1_ADDR      CEC_BASE + 0x0039 //FF
+#define CEC_DATA_BIT_1_LO_THRESH_2_ADDR      CEC_BASE + 0x003a //FF
+#define CEC_DATA_BIT_1_LO_THRESH_3_ADDR      CEC_BASE + 0x003b //FF
+#define CEC_DATA_BIT_0_HI_THRESH_0_ADDR      CEC_BASE + 0x003c //FF
+#define CEC_DATA_BIT_0_HI_THRESH_1_ADDR      CEC_BASE + 0x003d //FF
+#define CEC_DATA_BIT_0_HI_THRESH_2_ADDR      CEC_BASE + 0x003e //FF
+#define CEC_DATA_BIT_0_HI_THRESH_3_ADDR      CEC_BASE + 0x003f //FF
+#define CEC_DATA_BIT_1_HI_THRESH_0_ADDR      CEC_BASE + 0x0040 //FF
+#define CEC_DATA_BIT_1_HI_THRESH_1_ADDR      CEC_BASE + 0x0041 //FF
+#define CEC_DATA_BIT_1_HI_THRESH_2_ADDR      CEC_BASE + 0x0042 //FF
+#define CEC_DATA_BIT_1_HI_THRESH_3_ADDR      CEC_BASE + 0x0043 //FF
+#define CEC_SSP_ACK_TIME_0_ADDR              CEC_BASE + 0x0044 //FF
+#define CEC_SSP_ACK_TIME_1_ADDR              CEC_BASE + 0x0045 //FF
+#define CEC_SSP_ACK_TIME_2_ADDR              CEC_BASE + 0x0046 //FF
+#define CEC_SSP_ACK_TIME_3_ADDR              CEC_BASE + 0x0047 //FF
+#define CEC_INTR_ENABLE_REG_ADDR             CEC_BASE + 0x0048 //FF
+#define CEC_INTR_ENABLE1_REG_ADDR            CEC_BASE + 0x0049 //FF
+#define CEC_DATA_REG_ADDR                    CEC_BASE + 0x004c //FF
+#define CEC_EOM_REG_ADDR                     CEC_BASE + 0x0050 //01
+#define CEC_FIFO_STATUS_REG_ADDR             CEC_BASE + 0x0054
+#define CEC_INTR_STATUS_REG_ADDR             CEC_BASE + 0x0058
+#define CEC_NOMINAL_SAMPLE_TIME_0_ADDR       CEC_BASE + 0x005c //FF
+#define CEC_NOMINAL_SAMPLE_TIME_1_ADDR       CEC_BASE + 0x005d //FF
+#define CEC_NOMINAL_SAMPLE_TIME_2_ADDR       CEC_BASE + 0x005e //FF
+#define CEC_NOMINAL_SAMPLE_TIME_3_ADDR       CEC_BASE + 0x005f //FF
+#define CEC_HYST_TIME_0_ADDR                 CEC_BASE + 0x0060 //FF
+#define CEC_HYST_TIME_1_ADDR                 CEC_BASE + 0x0061 //FF
+#define CEC_HYST_TIME_2_ADDR                 CEC_BASE + 0x0062 //FF
+#define CEC_HYST_TIME_3_ADDR                 CEC_BASE + 0x0063 //FF
+#define CEC_FOLLOWER_ACK_TIME_0_ADDR         CEC_BASE + 0x0064 //FF
+#define CEC_FOLLOWER_ACK_TIME_1_ADDR         CEC_BASE + 0x0065 //FF
+#define CEC_FOLLOWER_ACK_TIME_2_ADDR         CEC_BASE + 0x0066 //FF
+#define CEC_FOLLOWER_ACK_TIME_3_ADDR         CEC_BASE + 0x0067 //FF
+#define CEC_RX_BUF_READ_REG_ADDR             CEC_BASE + 0x0068
+#define CEC_RX_EOM_READ_REG_ADDR             CEC_BASE + 0x0069
+#define CEC_LOGICAL_ADDR0_REG_ADDR           CEC_BASE + 0x006a //1F
+#define CEC_LOGICAL_ADDR1_REG_ADDR           CEC_BASE + 0x006b //1F
+#define CEC_LOGICAL_ADDR2_REG_ADDR           CEC_BASE + 0x006c //1F
+#define CEC_LOGICAL_ADDR3_REG_ADDR           CEC_BASE + 0x006d //1F
+#define CEC_LOGICAL_ADDR4_REG_ADDR           CEC_BASE + 0x006e //1F
+#define CEC_JITTER_CNT_0_ADDR                CEC_BASE + 0x0070 //FF
+#define CEC_JITTER_CNT_1_ADDR                CEC_BASE + 0x0071 //FF
+#define CEC_JITTER_CNT_2_ADDR                CEC_BASE + 0x0072 //FF
+#define CEC_JITTER_CNT_3_ADDR                CEC_BASE + 0x0073 //FF
+#define CEC_FAIL_INTR_STATUS_ADDR            CEC_BASE + 0x0074
+#define CEC_TX_PRESENT_STATE_REG_ADDR        CEC_BASE + 0x0078
+#define CEC_RX_PRESENT_STATE_REG_ADDR        CEC_BASE + 0x0079
+#define CEC_COLL_CTRL_REG_ADDR               CEC_BASE + 0x007a //03
+//#define CEC_GLITCH_FILTER_STAGES_ADDR        CEC_BASE + 0x007b //07
+#define CEC_COLL_WINDOW_TIME_REG_0_ADDR      CEC_BASE + 0x007c //FF
+#define CEC_COLL_WINDOW_TIME_REG_1_ADDR      CEC_BASE + 0x007d //FF
+#define CEC_COLL_WINDOW_TIME_REG_2_ADDR      CEC_BASE + 0x007e //FF
+#define CEC_COLL_WINDOW_TIME_REG_3_ADDR      CEC_BASE + 0x007f //FF
+#define CEC_TX_FIFO_FULL_THRESH              CEC_BASE + 0x0080 //0F
+#define CEC_TX_FIFO_WPTR                     CEC_BASE + 0x0081
+#define CEC_TX_FIFO_RPTR                     CEC_BASE + 0x0082
+#define CEC_TX_FIFO_DPTR                     CEC_BASE + 0x0083
+#define CEC_RX_FIFO_FULL_THRESH              CEC_BASE + 0x0084 //0F
+#define CEC_RX_FIFO_WPTR                     CEC_BASE + 0x0085
+#define CEC_RX_FIFO_RPTR                     CEC_BASE + 0x0086
+#define CEC_RX_FIFO_DPTR                     CEC_BASE + 0x0087
+#define CEC_JITTER_CNT_SB_0                  CEC_BASE + 0x0088 //FF
+#define CEC_JITTER_CNT_SB_1                  CEC_BASE + 0x0089 //FF
+#define CEC_JITTER_CNT_SB_2                  CEC_BASE + 0x008a //FF
+#define CEC_JITTER_CNT_SB_3                  CEC_BASE + 0x008b //FF
+#define CEC_ERR_NOTIF_TIME_0                 CEC_BASE + 0x008c //FF
+#define CEC_ERR_NOTIF_TIME_1                 CEC_BASE + 0x008d //FF
+#define CEC_ERR_NOTIF_TIME_2                 CEC_BASE + 0x008e //FF
+#define CEC_ERR_NOTIF_TIME_3                 CEC_BASE + 0x008f //FF
+#define CEC_GLITCH_FILT_W_L                  CEC_BASE + 0x0090 //FF
+#define CEC_GLITCH_FILT_W_H                  CEC_BASE + 0x0091 //FF
+
+//--------------------------------
+//HDCP
+//--------------------------------
+
+//ADDRESS OF AKEYS
+#define TX_HDCP_AKEY0_BYTE_0     0x1200 //00
+#define TX_HDCP_AKEY0_BYTE_1     0x1201 //00
+#define TX_HDCP_AKEY0_BYTE_2     0x1202 //00
+#define TX_HDCP_AKEY0_BYTE_3     0x1203 //00
+#define TX_HDCP_AKEY0_BYTE_4     0x1204 //00
+#define TX_HDCP_AKEY0_BYTE_5     0x1205 //00
+#define TX_HDCP_AKEY0_BYTE_6     0x1206 //00
+
+#define TX_HDCP_AKEY1_BYTE_0     0x1208 //00
+#define TX_HDCP_AKEY1_BYTE_1     0x1209 //00
+#define TX_HDCP_AKEY1_BYTE_2     0x120A //00
+#define TX_HDCP_AKEY1_BYTE_3     0x120B //00
+#define TX_HDCP_AKEY1_BYTE_4     0x120C //00
+#define TX_HDCP_AKEY1_BYTE_5     0x120D //00
+#define TX_HDCP_AKEY1_BYTE_6     0x120E //00
+
+#define TX_HDCP_AKEY2_BYTE_0     0x1210 //00
+#define TX_HDCP_AKEY2_BYTE_1     0x1211 //00
+#define TX_HDCP_AKEY2_BYTE_2     0x1212 //00
+#define TX_HDCP_AKEY2_BYTE_3     0x1213 //00
+#define TX_HDCP_AKEY2_BYTE_4     0x1214 //00
+#define TX_HDCP_AKEY2_BYTE_5     0x1215 //00
+#define TX_HDCP_AKEY2_BYTE_6     0x1216 //00
+
+#define TX_HDCP_AKEY3_BYTE_0     0x1218 //00
+#define TX_HDCP_AKEY3_BYTE_1     0x1219 //00
+#define TX_HDCP_AKEY3_BYTE_2     0x121A //00
+#define TX_HDCP_AKEY3_BYTE_3     0x121B //00
+#define TX_HDCP_AKEY3_BYTE_4     0x121C //00
+#define TX_HDCP_AKEY3_BYTE_5     0x121D //00
+#define TX_HDCP_AKEY3_BYTE_6     0x121E //00
+
+#define TX_HDCP_AKEY4_BYTE_0     0x1220 //00
+#define TX_HDCP_AKEY4_BYTE_1     0x1221 //00
+#define TX_HDCP_AKEY4_BYTE_2     0x1222 //00
+#define TX_HDCP_AKEY4_BYTE_3     0x1223 //00
+#define TX_HDCP_AKEY4_BYTE_4     0x1224 //00
+#define TX_HDCP_AKEY4_BYTE_5     0x1225 //00
+#define TX_HDCP_AKEY4_BYTE_6     0x1226 //00
+
+#define TX_HDCP_AKEY5_BYTE_0     0x1228 //00
+#define TX_HDCP_AKEY5_BYTE_1     0x1229 //00
+#define TX_HDCP_AKEY5_BYTE_2     0x122A //00
+#define TX_HDCP_AKEY5_BYTE_3     0x122B //00
+#define TX_HDCP_AKEY5_BYTE_4     0x122C //00
+#define TX_HDCP_AKEY5_BYTE_5     0x122D //00
+#define TX_HDCP_AKEY5_BYTE_6     0x122E //00
+
+#define TX_HDCP_AKEY6_BYTE_0     0x1230 //00
+#define TX_HDCP_AKEY6_BYTE_1     0x1231 //00
+#define TX_HDCP_AKEY6_BYTE_2     0x1232 //00
+#define TX_HDCP_AKEY6_BYTE_3     0x1233 //00
+#define TX_HDCP_AKEY6_BYTE_4     0x1234 //00
+#define TX_HDCP_AKEY6_BYTE_5     0x1235 //00
+#define TX_HDCP_AKEY6_BYTE_6     0x1236 //00
+
+#define TX_HDCP_AKEY7_BYTE_0     0x1238 //00
+#define TX_HDCP_AKEY7_BYTE_1     0x1239 //00
+#define TX_HDCP_AKEY7_BYTE_2     0x123A //00
+#define TX_HDCP_AKEY7_BYTE_3     0x123B //00
+#define TX_HDCP_AKEY7_BYTE_4     0x123C //00
+#define TX_HDCP_AKEY7_BYTE_5     0x123D //00
+#define TX_HDCP_AKEY7_BYTE_6     0x123E //00
+
+#define TX_HDCP_AKEY8_BYTE_0     0x1240 //00
+#define TX_HDCP_AKEY8_BYTE_1     0x1241 //00
+#define TX_HDCP_AKEY8_BYTE_2     0x1242 //00
+#define TX_HDCP_AKEY8_BYTE_3     0x1243 //00
+#define TX_HDCP_AKEY8_BYTE_4     0x1244 //00
+#define TX_HDCP_AKEY8_BYTE_5     0x1245 //00
+#define TX_HDCP_AKEY8_BYTE_6     0x1246 //00
+
+#define TX_HDCP_AKEY9_BYTE_0     0x1248 //00
+#define TX_HDCP_AKEY9_BYTE_1     0x1249 //00
+#define TX_HDCP_AKEY9_BYTE_2     0x124A //00
+#define TX_HDCP_AKEY9_BYTE_3     0x124B //00
+#define TX_HDCP_AKEY9_BYTE_4     0x124C //00
+#define TX_HDCP_AKEY9_BYTE_5     0x124D //00
+#define TX_HDCP_AKEY9_BYTE_6     0x124E //00
+
+#define TX_HDCP_AKEY10_BYTE_0    0x1250 //00
+#define TX_HDCP_AKEY10_BYTE_1    0x1251 //00
+#define TX_HDCP_AKEY10_BYTE_2    0x1252 //00
+#define TX_HDCP_AKEY10_BYTE_3    0x1253 //00
+#define TX_HDCP_AKEY10_BYTE_4    0x1254 //00
+#define TX_HDCP_AKEY10_BYTE_5    0x1255 //00
+#define TX_HDCP_AKEY10_BYTE_6    0x1256 //00
+
+#define TX_HDCP_AKEY11_BYTE_0    0x1258 //00
+#define TX_HDCP_AKEY11_BYTE_1    0x1259 //00
+#define TX_HDCP_AKEY11_BYTE_2    0x125A //00
+#define TX_HDCP_AKEY11_BYTE_3    0x125B //00
+#define TX_HDCP_AKEY11_BYTE_4    0x125C //00
+#define TX_HDCP_AKEY11_BYTE_5    0x125D //00
+#define TX_HDCP_AKEY11_BYTE_6    0x125E //00
+
+#define TX_HDCP_AKEY12_BYTE_0    0x1260 //00
+#define TX_HDCP_AKEY12_BYTE_1    0x1261 //00
+#define TX_HDCP_AKEY12_BYTE_2    0x1262 //00
+#define TX_HDCP_AKEY12_BYTE_3    0x1263 //00
+#define TX_HDCP_AKEY12_BYTE_4    0x1264 //00
+#define TX_HDCP_AKEY12_BYTE_5    0x1265 //00
+#define TX_HDCP_AKEY12_BYTE_6    0x1266 //00
+
+#define TX_HDCP_AKEY13_BYTE_0    0x1268 //00
+#define TX_HDCP_AKEY13_BYTE_1    0x1269 //00
+#define TX_HDCP_AKEY13_BYTE_2    0x126A //00
+#define TX_HDCP_AKEY13_BYTE_3    0x126B //00
+#define TX_HDCP_AKEY13_BYTE_4    0x126C //00
+#define TX_HDCP_AKEY13_BYTE_5    0x126D //00
+#define TX_HDCP_AKEY13_BYTE_6    0x126E //00
+
+#define TX_HDCP_AKEY14_BYTE_0    0x1270 //00
+#define TX_HDCP_AKEY14_BYTE_1    0x1271 //00
+#define TX_HDCP_AKEY14_BYTE_2    0x1272 //00
+#define TX_HDCP_AKEY14_BYTE_3    0x1273 //00
+#define TX_HDCP_AKEY14_BYTE_4    0x1274 //00
+#define TX_HDCP_AKEY14_BYTE_5    0x1275 //00
+#define TX_HDCP_AKEY14_BYTE_6    0x1276 //00
+
+#define TX_HDCP_AKEY15_BYTE_0    0x1278 //00
+#define TX_HDCP_AKEY15_BYTE_1    0x1279 //00
+#define TX_HDCP_AKEY15_BYTE_2    0x127A //00
+#define TX_HDCP_AKEY15_BYTE_3    0x127B //00
+#define TX_HDCP_AKEY15_BYTE_4    0x127C //00
+#define TX_HDCP_AKEY15_BYTE_5    0x127D //00
+#define TX_HDCP_AKEY15_BYTE_6    0x127E //00
+
+#define TX_HDCP_AKEY16_BYTE_0    0x1280 //00
+#define TX_HDCP_AKEY16_BYTE_1    0x1281 //00
+#define TX_HDCP_AKEY16_BYTE_2    0x1282 //00
+#define TX_HDCP_AKEY16_BYTE_3    0x1283 //00
+#define TX_HDCP_AKEY16_BYTE_4    0x1284 //00
+#define TX_HDCP_AKEY16_BYTE_5    0x1285 //00
+#define TX_HDCP_AKEY16_BYTE_6    0x1286 //00
+
+#define TX_HDCP_AKEY17_BYTE_0    0x1288 //00
+#define TX_HDCP_AKEY17_BYTE_1    0x1289 //00
+#define TX_HDCP_AKEY17_BYTE_2    0x128A //00
+#define TX_HDCP_AKEY17_BYTE_3    0x128B //00
+#define TX_HDCP_AKEY17_BYTE_4    0x128C //00
+#define TX_HDCP_AKEY17_BYTE_5    0x128D //00
+#define TX_HDCP_AKEY17_BYTE_6    0x128E //00
+
+#define TX_HDCP_AKEY18_BYTE_0    0x1290 //00
+#define TX_HDCP_AKEY18_BYTE_1    0x1291 //00
+#define TX_HDCP_AKEY18_BYTE_2    0x1292 //00
+#define TX_HDCP_AKEY18_BYTE_3    0x1293 //00
+#define TX_HDCP_AKEY18_BYTE_4    0x1294 //00
+#define TX_HDCP_AKEY18_BYTE_5    0x1295 //00
+#define TX_HDCP_AKEY18_BYTE_6    0x1296 //00
+
+#define TX_HDCP_AKEY19_BYTE_0    0x1298 //00
+#define TX_HDCP_AKEY19_BYTE_1    0x1299 //00
+#define TX_HDCP_AKEY19_BYTE_2    0x129A //00
+#define TX_HDCP_AKEY19_BYTE_3    0x129B //00
+#define TX_HDCP_AKEY19_BYTE_4    0x129C //00
+#define TX_HDCP_AKEY19_BYTE_5    0x129D //00
+#define TX_HDCP_AKEY19_BYTE_6    0x129E //00
+
+#define TX_HDCP_AKEY20_BYTE_0    0x12A0 //00
+#define TX_HDCP_AKEY20_BYTE_1    0x12A1 //00
+#define TX_HDCP_AKEY20_BYTE_2    0x12A2 //00
+#define TX_HDCP_AKEY20_BYTE_3    0x12A3 //00
+#define TX_HDCP_AKEY20_BYTE_4    0x12A4 //00
+#define TX_HDCP_AKEY20_BYTE_5    0x12A5 //00
+#define TX_HDCP_AKEY20_BYTE_6    0x12A6 //00
+
+#define TX_HDCP_AKEY21_BYTE_0    0x12A8 //00
+#define TX_HDCP_AKEY21_BYTE_1    0x12A9 //00
+#define TX_HDCP_AKEY21_BYTE_2    0x12AA //00
+#define TX_HDCP_AKEY21_BYTE_3    0x12AB //00
+#define TX_HDCP_AKEY21_BYTE_4    0x12AC //00
+#define TX_HDCP_AKEY21_BYTE_5    0x12AD //00
+#define TX_HDCP_AKEY21_BYTE_6    0x12AE //00
+
+#define TX_HDCP_AKEY22_BYTE_0    0x12B0 //00
+#define TX_HDCP_AKEY22_BYTE_1    0x12B1 //00
+#define TX_HDCP_AKEY22_BYTE_2    0x12B2 //00
+#define TX_HDCP_AKEY22_BYTE_3    0x12B3 //00
+#define TX_HDCP_AKEY22_BYTE_4    0x12B4 //00
+#define TX_HDCP_AKEY22_BYTE_5    0x12B5 //00
+#define TX_HDCP_AKEY22_BYTE_6    0x12B6 //00
+
+#define TX_HDCP_AKEY23_BYTE_0    0x12B8 //00
+#define TX_HDCP_AKEY23_BYTE_1    0x12B9 //00
+#define TX_HDCP_AKEY23_BYTE_2    0x12BA //00
+#define TX_HDCP_AKEY23_BYTE_3    0x12BB //00
+#define TX_HDCP_AKEY23_BYTE_4    0x12BC //00
+#define TX_HDCP_AKEY23_BYTE_5    0x12BD //00
+#define TX_HDCP_AKEY23_BYTE_6    0x12BE //00
+
+#define TX_HDCP_AKEY24_BYTE_0    0x12C0 //00
+#define TX_HDCP_AKEY24_BYTE_1    0x12C1 //00
+#define TX_HDCP_AKEY24_BYTE_2    0x12C2 //00
+#define TX_HDCP_AKEY24_BYTE_3    0x12C3 //00
+#define TX_HDCP_AKEY24_BYTE_4    0x12C4 //00
+#define TX_HDCP_AKEY24_BYTE_5    0x12C5 //00
+#define TX_HDCP_AKEY24_BYTE_6    0x12C6 //00
+
+#define TX_HDCP_AKEY25_BYTE_0    0x12C8 //00
+#define TX_HDCP_AKEY25_BYTE_1    0x12C9 //00
+#define TX_HDCP_AKEY25_BYTE_2    0x12CA //00
+#define TX_HDCP_AKEY25_BYTE_3    0x12CB //00
+#define TX_HDCP_AKEY25_BYTE_4    0x12CC //00
+#define TX_HDCP_AKEY25_BYTE_5    0x12CD //00
+#define TX_HDCP_AKEY25_BYTE_6    0x12CE //00
+
+#define TX_HDCP_AKEY26_BYTE_0    0x12D0 //00
+#define TX_HDCP_AKEY26_BYTE_1    0x12D1 //00
+#define TX_HDCP_AKEY26_BYTE_2    0x12D2 //00
+#define TX_HDCP_AKEY26_BYTE_3    0x12D3 //00
+#define TX_HDCP_AKEY26_BYTE_4    0x12D4 //00
+#define TX_HDCP_AKEY26_BYTE_5    0x12D5 //00
+#define TX_HDCP_AKEY26_BYTE_6    0x12D6 //00
+
+#define TX_HDCP_AKEY27_BYTE_0    0x12D8 //00
+#define TX_HDCP_AKEY27_BYTE_1    0x12D9 //00
+#define TX_HDCP_AKEY27_BYTE_2    0x12DA //00
+#define TX_HDCP_AKEY27_BYTE_3    0x12DB //00
+#define TX_HDCP_AKEY27_BYTE_4    0x12DC //00
+#define TX_HDCP_AKEY27_BYTE_5    0x12DD //00
+#define TX_HDCP_AKEY27_BYTE_6    0x12DE //00
+
+#define TX_HDCP_AKEY28_BYTE_0    0x12E0 //00
+#define TX_HDCP_AKEY28_BYTE_1    0x12E1 //00
+#define TX_HDCP_AKEY28_BYTE_2    0x12E2 //00
+#define TX_HDCP_AKEY28_BYTE_3    0x12E3 //00
+#define TX_HDCP_AKEY28_BYTE_4    0x12E4 //00
+#define TX_HDCP_AKEY28_BYTE_5    0x12E5 //00
+#define TX_HDCP_AKEY28_BYTE_6    0x12E6 //00
+
+#define TX_HDCP_AKEY29_BYTE_0    0x12E8 //00
+#define TX_HDCP_AKEY29_BYTE_1    0x12E9 //00
+#define TX_HDCP_AKEY29_BYTE_2    0x12EA //00
+#define TX_HDCP_AKEY29_BYTE_3    0x12EB //00
+#define TX_HDCP_AKEY29_BYTE_4    0x12EC //00
+#define TX_HDCP_AKEY29_BYTE_5    0x12ED //00
+#define TX_HDCP_AKEY29_BYTE_6    0x12EE //00
+
+#define TX_HDCP_AKEY30_BYTE_0    0x12F0 //00
+#define TX_HDCP_AKEY30_BYTE_1    0x12F1 //00
+#define TX_HDCP_AKEY30_BYTE_2    0x12F2 //00
+#define TX_HDCP_AKEY30_BYTE_3    0x12F3 //00
+#define TX_HDCP_AKEY30_BYTE_4    0x12F4 //00
+#define TX_HDCP_AKEY30_BYTE_5    0x12F5 //00
+#define TX_HDCP_AKEY30_BYTE_6    0x12F6 //00
+
+#define TX_HDCP_AKEY31_BYTE_0    0x12F8 //00
+#define TX_HDCP_AKEY31_BYTE_1    0x12F9 //00
+#define TX_HDCP_AKEY31_BYTE_2    0x12FA //00
+#define TX_HDCP_AKEY31_BYTE_3    0x12FB //00
+#define TX_HDCP_AKEY31_BYTE_4    0x12FC //00
+#define TX_HDCP_AKEY31_BYTE_5    0x12FD //00
+#define TX_HDCP_AKEY31_BYTE_6    0x12FE //00
+
+#define TX_HDCP_AKEY32_BYTE_0    0x1300 //00
+#define TX_HDCP_AKEY32_BYTE_1    0x1301 //00
+#define TX_HDCP_AKEY32_BYTE_2    0x1302 //00
+#define TX_HDCP_AKEY32_BYTE_3    0x1303 //00
+#define TX_HDCP_AKEY32_BYTE_4    0x1304 //00
+#define TX_HDCP_AKEY32_BYTE_5    0x1305 //00
+#define TX_HDCP_AKEY32_BYTE_6    0x1306 //00
+
+#define TX_HDCP_AKEY33_BYTE_0    0x1308 //00
+#define TX_HDCP_AKEY33_BYTE_1    0x1309 //00
+#define TX_HDCP_AKEY33_BYTE_2    0x130A //00
+#define TX_HDCP_AKEY33_BYTE_3    0x130B //00
+#define TX_HDCP_AKEY33_BYTE_4    0x130C //00
+#define TX_HDCP_AKEY33_BYTE_5    0x130D //00
+#define TX_HDCP_AKEY33_BYTE_6    0x130E //00
+
+#define TX_HDCP_AKEY34_BYTE_0    0x1310 //00
+#define TX_HDCP_AKEY34_BYTE_1    0x1311 //00
+#define TX_HDCP_AKEY34_BYTE_2    0x1312 //00
+#define TX_HDCP_AKEY34_BYTE_3    0x1313 //00
+#define TX_HDCP_AKEY34_BYTE_4    0x1314 //00
+#define TX_HDCP_AKEY34_BYTE_5    0x1315 //00
+#define TX_HDCP_AKEY34_BYTE_6    0x1316 //00
+
+#define TX_HDCP_AKEY35_BYTE_0    0x1318 //00
+#define TX_HDCP_AKEY35_BYTE_1    0x1319 //00
+#define TX_HDCP_AKEY35_BYTE_2    0x131A //00
+#define TX_HDCP_AKEY35_BYTE_3    0x131B //00
+#define TX_HDCP_AKEY35_BYTE_4    0x131C //00
+#define TX_HDCP_AKEY35_BYTE_5    0x131D //00
+#define TX_HDCP_AKEY35_BYTE_6    0x131E //00
+
+#define TX_HDCP_AKEY36_BYTE_0    0x1320 //00
+#define TX_HDCP_AKEY36_BYTE_1    0x1321 //00
+#define TX_HDCP_AKEY36_BYTE_2    0x1322 //00
+#define TX_HDCP_AKEY36_BYTE_3    0x1323 //00
+#define TX_HDCP_AKEY36_BYTE_4    0x1324 //00
+#define TX_HDCP_AKEY36_BYTE_5    0x1325 //00
+#define TX_HDCP_AKEY36_BYTE_6    0x1326 //00
+
+#define TX_HDCP_AKEY37_BYTE_0    0x1328 //00
+#define TX_HDCP_AKEY37_BYTE_1    0x1329 //00
+#define TX_HDCP_AKEY37_BYTE_2    0x132A //00
+#define TX_HDCP_AKEY37_BYTE_3    0x132B //00
+#define TX_HDCP_AKEY37_BYTE_4    0x132C //00
+#define TX_HDCP_AKEY37_BYTE_5    0x132D //00
+#define TX_HDCP_AKEY37_BYTE_6    0x132E //00
+
+#define TX_HDCP_AKEY38_BYTE_0    0x1330 //00
+#define TX_HDCP_AKEY38_BYTE_1    0x1331 //00
+#define TX_HDCP_AKEY38_BYTE_2    0x1332 //00
+#define TX_HDCP_AKEY38_BYTE_3    0x1333 //00
+#define TX_HDCP_AKEY38_BYTE_4    0x1334 //00
+#define TX_HDCP_AKEY38_BYTE_5    0x1335 //00
+#define TX_HDCP_AKEY38_BYTE_6    0x1336 //00
+
+#define TX_HDCP_AKEY39_BYTE_0    0x1338 //00
+#define TX_HDCP_AKEY39_BYTE_1    0x1339 //00
+#define TX_HDCP_AKEY39_BYTE_2    0x133A //00
+#define TX_HDCP_AKEY39_BYTE_3    0x133B //00
+#define TX_HDCP_AKEY39_BYTE_4    0x133C //00
+#define TX_HDCP_AKEY39_BYTE_5    0x133D //00
+#define TX_HDCP_AKEY39_BYTE_6    0x133E //00
+
+
+#define TX_HDCP_AKSV_BYTE_0      0x1340
+#define TX_HDCP_AKSV_BYTE_1      0x1341
+#define TX_HDCP_AKSV_BYTE_2      0x1342
+#define TX_HDCP_AKSV_BYTE_3      0x1343
+#define TX_HDCP_AKSV_BYTE_4      0x1344
+
+// HDCP REGS
+#define TX_HDCP_CTRL             0x1350 //FE
+#define TX_HDCP_STATUS_1         0x1351 //FE
+#define TX_HDCP_STATUS_2         0x1352
+#define TX_HDCP_INTR_0           0x1353
+#define TX_HDCP_TX_AKSV_0        0x1354
+#define TX_HDCP_TX_AKSV_1        0x1355
+#define TX_HDCP_TX_AKSV_2        0x1356
+#define TX_HDCP_TX_AKSV_3        0x1357
+#define TX_HDCP_TX_AKSV_4        0x1358
+#define TX_HDCP_RX_BKSV_0        0x135C //FF
+#define TX_HDCP_RX_BKSV_1        0x135D //FF
+#define TX_HDCP_RX_BKSV_2        0x135E //FF
+#define TX_HDCP_RX_BKSV_3        0x135F //FF
+#define TX_HDCP_RX_BKSV_4        0x1360 //FF
+#define TX_HDCP_TX_AINFO         0x1361 //FF
+#define TX_HDCP_RX_BCAPS         0x1362 //FF
+#define TX_HDCP_RX_BSTATUS_0     0x1364 //FF
+#define TX_HDCP_RX_BSTATUS_1     0x1365 //FF
+#define TX_HDCP_TX_AN_0          0x1368
+#define TX_HDCP_TX_AN_1          0x1369
+#define TX_HDCP_TX_AN_2          0x136A
+#define TX_HDCP_TX_AN_3          0x136B
+#define TX_HDCP_TX_AN_4          0x136C
+#define TX_HDCP_TX_AN_5          0x136D
+#define TX_HDCP_TX_AN_6          0x136E
+#define TX_HDCP_TX_AN_7          0x136F
+#define TX_HDCP_TX_M0_0          0x1370 //M0 shouldn't be accessable by FW
+#define TX_HDCP_TX_M0_1          0x1371
+#define TX_HDCP_TX_M0_2          0x1372
+#define TX_HDCP_TX_M0_3          0x1373
+#define TX_HDCP_TX_M0_4          0x1374
+#define TX_HDCP_TX_M0_5          0x1375
+#define TX_HDCP_TX_M0_6          0x1376
+#define TX_HDCP_TX_M0_7          0x1377
+#define TX_HDCP_TX_R0_0          0x1378
+#define TX_HDCP_TX_R0_1          0x1379
+#define TX_HDCP_RX_R0_0          0x137A //FF
+#define TX_HDCP_RX_R0_1          0x137B //FF
+#define TX_HDCP_TX_RI_0          0x137C
+#define TX_HDCP_TX_RI_1          0x137D
+#define TX_HDCP_RX_RI_0          0x137E //FF
+#define TX_HDCP_RX_RI_1          0x137F //FF
+#define TX_HDCP_TX_PJ            0x1380
+#define TX_HDCP_RX_PJ            0x1381 //FF
+#define TX_HDCP_FIX_CLR_0        0x1384 //FF
+#define TX_HDCP_FIX_CLR_1        0x1385 //FF
+#define TX_HDCP_FIX_CLR_2        0x1386 //FF
+#define TX_HDCP_KINIT_0          0x1388 //FF
+#define TX_HDCP_KINIT_1          0x1389 //FF
+#define TX_HDCP_KINIT_2          0x138A //FF
+#define TX_HDCP_KINIT_3          0x138B //FF
+#define TX_HDCP_KINIT_4          0x138C //FF
+#define TX_HDCP_KINIT_5          0x138D //FF
+#define TX_HDCP_KINIT_6          0x138E //FF
+#define TX_HDCP_BINIT_0          0x1390 //FF
+#define TX_HDCP_BINIT_1          0x1391 //FF
+#define TX_HDCP_BINIT_2          0x1392 //FF
+#define TX_HDCP_BINIT_3          0x1393 //FF
+#define TX_HDCP_BINIT_4          0x1394 //FF
+#define TX_HDCP_BINIT_5          0x1395 //FF
+#define TX_HDCP_BINIT_6          0x1396 //FF
+#define TX_HDCP_BINIT_7          0x1397 //FF
+#define TX_HDCP_INTR_CLR         0x1398 //F8
+#define TX_HDCP_INTR_MASK        0x1399 //F8
+
+
+
+#define VPP_BE_HDMITX_MAX_PKT_INDEX 6
diff --git a/drivers/video/hdmi.c b/drivers/video/hdmi.c
new file mode 100644
index 0000000000..dd41fc360d
--- /dev/null
+++ b/drivers/video/hdmi.c
@@ -0,0 +1,216 @@
+/*
+ * HDMI Control Abstraction
+ *
+ * This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation version 2 of the License.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ */
+
+#include <hdmi.h>
+
+#define HDMI_DEBUG
+static int hdmi_core_debug = 5;
+#define hdmi_dprintk(level, fmt, arg...)	if (hdmi_core_debug >= level) \
+	printf("%s: " fmt , __func__, ## arg)
+
+const struct fb_videomode cea_modes[65] = {
+	/* #1: 640x480p@59.94/60Hz */
+	[1] = {
+		NULL, 60, 640, 480, 39722, 48, 16, 33, 10, 96, 2, 0,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #2: 720x480p@59.94/60Hz ratio 4:3 */
+	/* #3: 720x480p@59.94/60Hz */
+	[3] = {
+		NULL, 60, 720, 480, 37037, 60, 16, 30, 9, 62, 6, 0,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #4: 1280x720p@59.94/60Hz */
+	[4] = {
+		NULL, 60, 1280, 720, 13468, 220, 110, 20, 5, 40, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #5: 1920x1080i@59.94/60Hz */
+	[5] = {
+		NULL, 60, 1920, 1080, 13763, 148, 88, 15, 2, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_INTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #6: 720(1440)x480iH@59.94/60Hz ratio 4:3 */
+	/* #7: 720(1440)x480iH@59.94/60Hz */
+	[7] = {
+		NULL, 60, 1440, 480, 18554/*37108*/, 114, 38, 15, 4, 124, 3, 0,
+		FB_VMODE_INTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #8: 720(1440)x240pH@59.94/60Hz ratio 4:3 */
+	/* #9: 720(1440)x240pH@59.94/60Hz */
+	[9] = {
+		NULL, 60, 1440, 240, 18554, 114, 38, 15, 4, 124, 3, 0,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #16: 1920x1080p@59.94/60Hz */
+	[16] = {
+		NULL, 60, 1920, 1080, 6734, 148, 88, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #17: 720x576pH@50Hz ratio 4:3 */
+	/* #18: 720x576pH@50Hz */
+	[18] = {
+		NULL, 50, 720, 576, 37037, 68, 12, 39, 5, 64, 5, 0,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #19: 1280x720p@50Hz */
+	[19] = {
+		NULL, 50, 1280, 720, 13468, 220, 440, 20, 5, 40, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #20: 1920x1080i@50Hz */
+	[20] = {
+		NULL, 50, 1920, 1080, 13480, 148, 528, 15, 5, 528, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_INTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #21: 720x576i@50Hz ratio 4:3 */
+	/* #22: 720x576i@50Hz */
+	[22] = {
+		NULL, 50, 720, 576, 37037, 138, 24, 19, 2, 24, 3, 0,
+		FB_VMODE_INTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #31: 1920x1080p@50Hz */
+	[31] = {
+		NULL, 50, 1920, 1080, 6734, 148, 528, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #32: 1920x1080p@23.98/24Hz */
+	[32] = {
+		NULL, 24, 1920, 1080, 13480, 148, 638, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #33: 1920x1080p@25Hz */
+	[33] = {
+		NULL, 25, 1920, 1080, 13480, 148, 638, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #34: 1920x1080p@30Hz */
+	[34] = {
+		NULL, 30, 1920, 1080, 13480, 148, 88, 36, 4, 44, 5,
+		FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+	/* #35: (2880)x480p4x@59.94/60Hz */
+	[35] = {
+		NULL, 60, 2880, 480, 9250, 240, 64, 30, 9, 248, 6, 0,
+		FB_VMODE_NONINTERLACED, FB_MODE_IS_CEA,
+	},
+};
+/* ==================== info frame utility ===================== */
+
+int hdmi_vender_info_frame (struct hdmi_dev *hd, char buf[])
+{
+	int count;
+	char check_sum = 0;
+
+	buf[0] = 0x81;
+	buf[1] = 0x1;
+	buf[2] = 0x5;
+	buf[3] = 0;
+	buf[4] = 0x3;
+	buf[5] = 0xc;
+	buf[6] = 0x0;
+	if (hd->mode_3d)
+		buf[7] = 0x40;
+	else
+		buf[7] = 0x0;
+	buf[8] = 0x0; /* only support frame packing currently */
+
+	for (count = 0; count < 14; count++)
+		check_sum += buf[count];
+	buf[3] = 0x100 - check_sum;
+	return 0;
+}
+
+int hdmi_avi_info_frame (struct hdmi_dev *hd, char buf[])
+{
+	int count;
+	char check_sum = 0;
+
+	hdmi_dprintk(3, "pack avi infoframe\n");
+	/* packet header for AVI Packet in pkt1 */
+	/* Fix me. we should set bits according to format */
+	buf[0] = 0x82; /* InfoFrame Type, AVI frame */
+	buf[1] = 0x2;  /* Version = 02 */
+	buf[2] = 0xd;  /* Length = 13 */
+	buf[3] = 0x0;  /* checksum */
+	buf[4] = 0x0; /* Fix to RGB format currently */
+	/*
+	buf[4] = 0x10; // RGB, Active Format(r0,r1,r2,r3) valid, no bar, no scan
+	buf[4] = 0x30; // HDMI_YUV422, Active Format(r0,r1,r2,r3) valid, no bar, no scan
+	buf[4] = 0x50; // HDMI_YUV444, Active Format(r0,r1,r2,r3) valid, no bar, no scan
+	*/
+
+	buf[5] = 0xa8;  /* ITU-R 709, 16:9 */
+	buf[6] = 0x20;
+	/* buf[6] = 0x0;   // No IT content, xvYCC601, no scaling */
+	buf[7] = hd->mode_id;
+	/* limited YCC range, graphics, no repeat  Pixel repitition factor */
+	buf[8] = hd->pixel_rept;
+
+	buf[9] = 0x0;
+	buf[10] = 0x0;
+	buf[11] = 0x0;
+	buf[12] = 0x0;
+	buf[13] = 0x0;
+
+	for (count = 0; count < 14; count++)
+		check_sum += buf[count];
+	buf[3] = 0x100 - check_sum;
+	return 0;
+}
+
+int hdmi_get_freq (struct hdmi_dev *hd, u32 *need_freq)
+{
+	int freq;
+
+	/* Calc divider according to pclk in pico second */
+	freq = 1000000000000LL / cea_modes[hd->mode_id].pixclock;
+
+	hdmi_dprintk(3, "get base pclk %d\n", freq);
+
+	if (FB_VMODE_INTERLACED & cea_modes[hd->mode_id].vmode)
+		freq >>= 1;
+
+	/* We only support repeat=2/4 currently. Add more later */
+	if (!(hd->pixel_rept == 0 || hd->pixel_rept == 1
+				|| hd->pixel_rept == 3)) {
+		hdmi_dprintk(3, "Not support pix repeat %d\n", hd->pixel_rept);
+		return -1;
+	}
+
+	if (1 == hd->pixel_rept)
+	{
+		if (!(FB_VMODE_INTERLACED & cea_modes[hd->mode_id].vmode))
+			freq <<= 1;
+	} else if (3 == hd->pixel_rept) {
+		if (!(FB_VMODE_INTERLACED & cea_modes[hd->mode_id].vmode))
+			freq <<= 2;
+		else
+			freq <<= 1;
+	}
+	if (hd->mode_3d)
+			freq <<= 1;
+
+	hdmi_dprintk(3, "get hdmi pclk %d\n", freq);
+	*need_freq = freq;
+	return 0;
+}
diff --git a/drivers/video/pxa168fb.c b/drivers/video/pxa168fb.c
new file mode 100644
index 0000000000..0deac9d5f1
--- /dev/null
+++ b/drivers/video/pxa168fb.c
@@ -0,0 +1,1418 @@
+/*
+ * linux/drivers/video/pxa168fb.c -- Marvell PXA168 LCD Controller
+ *
+ *  Copyright (C) 2008 Marvell International Ltd.
+ *  All rights reserved.
+ *
+ *  2009-02-16  adapted from original version for PXA168
+ *		Green Wan <gwan@marvell.com>
+ *              Jun Nie <njun@marvell.com>
+ *		Kevin Liu <kliu5@marvell.com>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <malloc.h>
+#include <linux/types.h>
+#include <hdmi.h>
+#include <asm/io.h>
+#include <common.h>
+#include <i2c.h>
+#include <asm/gpio.h>
+#include "tc35876x.h"
+#include <pxa168fb.h>
+#include "pxa168fb.h"
+
+#define tc_read16(reg, pval)	i2c_read(0xf, (unsigned int)reg,\
+		2, (void *)pval, 2)
+#define tc_read32(reg, pval)	i2c_read(0xf, (unsigned int)reg,\
+		2, (void *)pval, 4)
+#define tc_write32(reg, val)	do { u32 _val; _val = val; \
+			i2c_write(0xf, reg, 2, (u8 *)&_val, 4); } while (0)
+
+#define dsi_ex_pixel_cnt                0
+#define dsi_hex_en                      0
+/* (Unit: Mhz) */
+#define dsi_lpclk                       3
+
+#define to_dsi_bcnt(timing, bpp)        (((timing) * (bpp)) >> 3)
+
+struct pxa168fb_info *pxa168_fbi[3];
+static unsigned int dsi_lane[5] = {0, 0x1, 0x3, 0x7, 0xf};
+
+void dsi_cclk_set(struct dsi_info *di, int en)
+{
+	struct dsi_regs *dsi = (struct dsi_regs *)di->regs;
+
+	if (en)
+		writel(0x1, &dsi->phy_ctrl1);
+	else
+		writel(0x0, &dsi->phy_ctrl1);
+
+	udelay(100000);
+}
+
+/* dsi phy timing */
+static struct dsi_phy phy = {
+	.hs_prep_constant       = 60,    /* Unit: ns. */
+	.hs_prep_ui             = 5,
+	.hs_zero_constant       = 85,
+	.hs_zero_ui             = 5,
+	.hs_trail_constant      = 0,
+	.hs_trail_ui            = 64,
+	.hs_exit_constant       = 100,
+	.hs_exit_ui             = 0,
+	.ck_zero_constant       = 300,
+	.ck_zero_ui             = 0,
+	.ck_trail_constant      = 60,
+	.ck_trail_ui            = 0,
+	.req_ready              = 0x3c,
+};
+void dsi_set_dphy(struct pxa168fb_info *fbi)
+{
+	struct pxa168fb_mach_info *mi = fbi->mi;
+	struct dsi_info *di = (struct dsi_info *)mi->phy_info;
+	struct dsi_regs *dsi = (struct dsi_regs *)di->regs;
+	u32 ui, lpx_clk, lpx_time, ta_get, ta_go, wakeup, reg;
+	u32 hs_prep, hs_zero, hs_trail, hs_exit, ck_zero, ck_trail, ck_exit;
+
+	/* in kernel: ui = 1000/dsi_hsclk + 1 */
+	ui = 1000 / (mi->sclk_src / 1000000) + 1;
+	lpx_clk = (DSI_ESC_CLK / dsi_lpclk / 2) - 1;
+	lpx_time = (lpx_clk + 1) * DSI_ESC_CLK_T;
+	/* Below is for NT35451 */
+	ta_get = ((lpx_time * 10 + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+	ta_go  = ((lpx_time * 4 + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+	wakeup = 0xfff0;
+
+	hs_prep = phy.hs_prep_constant + phy.hs_prep_ui * ui;
+	hs_prep = ((hs_prep + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+
+	/* Our hardware added 3-byte clk automatically.
+	 * 3-byte 3 * 8 * ui.
+	 */
+	hs_zero = phy.hs_zero_constant + phy.hs_zero_ui * ui;
+	if (hs_zero > (24 * ui))
+		hs_zero -= (24 * ui);
+	else
+		hs_zero = DSI_ESC_CLK_T;
+
+	if (hs_zero > (DSI_ESC_CLK_T * 2))
+		hs_zero = ((hs_zero + (DSI_ESC_CLK_T >> 1)) \
+				/ DSI_ESC_CLK_T) - 1;
+	else
+		hs_zero = 1;
+
+	hs_trail = phy.hs_trail_constant + phy.hs_trail_ui * ui;
+	hs_trail = ((hs_trail + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+
+	hs_exit = phy.hs_exit_constant + phy.hs_exit_ui * ui;
+	hs_exit = ((hs_exit + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+
+	ck_zero = phy.ck_zero_constant + phy.ck_zero_ui * ui;
+	ck_zero = ((ck_zero + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+
+	ck_trail = phy.ck_trail_constant + phy.ck_trail_ui * ui;
+	ck_trail = ((ck_trail + (DSI_ESC_CLK_T >> 1)) / DSI_ESC_CLK_T) - 1;
+
+	ck_exit = hs_exit;
+
+	/* bandgap ref enable */
+	reg = readl(&dsi->phy_rcomp0);
+	reg |= (1<<9);
+	writel(reg, &dsi->phy_rcomp0);
+	/* timing_0 */
+	reg = (hs_exit << DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT)
+		| (hs_trail << DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT)
+		| (hs_zero << DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT)
+		| (hs_prep);
+
+	writel(reg, &dsi->phy_timing0);
+	reg = (ta_get << DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT)
+		| (ta_go << DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT)
+		| wakeup;
+	writel(reg, &dsi->phy_timing1);
+	reg = (ck_exit << DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT)
+		| (ck_trail << DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT)
+		| (ck_zero << DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT)
+		| lpx_clk;
+	writel(reg, &dsi->phy_timing2);
+
+	reg = (lpx_clk << DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT) | \
+	      phy.req_ready;
+	writel(reg, &dsi->phy_timing3);
+	/* calculated timing on brownstone:
+	 * DSI_PHY_TIME_0 0x06080204
+	 * DSI_PHY_TIME_1 0x6d2bfff0
+	 * DSI_PHY_TIME_2 0x603130a
+	 * DSI_PHY_TIME_3 0xa3c
+	 */
+}
+
+void dsi_reset(struct dsi_info *di, int hold)
+{
+	struct dsi_regs *dsi = (struct dsi_regs *)di->regs;
+	unsigned int reg;
+
+	writel(0x0, &dsi->ctrl0);
+	reg = readl(&dsi->ctrl0);
+	reg |= DSI_CTRL_0_CFG_SOFT_RST | DSI_CTRL_0_CFG_SOFT_RST_REG;
+
+	if (!hold) {
+		writel(reg, &dsi->ctrl0);
+		reg &= ~(DSI_CTRL_0_CFG_SOFT_RST | DSI_CTRL_0_CFG_SOFT_RST_REG);
+		udelay(1000);
+	}
+	writel(reg, &dsi->ctrl0);
+}
+
+#if defined(DEBUG_PXA168FB)
+#define DSIW(x, y)  do {writel(x, y); printf("address %x, \
+		value %x\n", y, x); } while (0)
+#else
+#define DSIW(x, y)  do {writel(x, y); } while (0)
+#endif
+void dsi_set_controller(struct pxa168fb_info *fbi)
+{
+	struct fb_var_screeninfo *var = fbi->var;
+	struct pxa168fb_mach_info *mi = fbi->mi;
+	struct dsi_info *di = (struct dsi_info *)mi->phy_info;
+	struct dsi_regs *dsi = (struct dsi_regs *)di->regs;
+	struct dsi_lcd_regs *dsi_lcd = &dsi->lcd1;
+	unsigned hsync_b, hbp_b, hact_b, hex_b, hfp_b, httl_b;
+	unsigned hsync, hbp, hact, hfp, httl, h_total, v_total;
+	unsigned hsa_wc, hbp_wc, hact_wc, hex_wc, hfp_wc, hlp_wc;
+	int bpp = di->bpp, hss_bcnt = 4, hse_bct = 4, lgp_over_head = 6, reg;
+
+	if (di->id & 2)
+		dsi_lcd = &dsi->lcd2;
+
+	h_total = var->xres + var->left_margin + var->right_margin
+		+ var->hsync_len;
+	v_total = var->yres + var->upper_margin + var->lower_margin
+		+ var->vsync_len;
+
+	hact_b = to_dsi_bcnt(var->xres, bpp);
+	hfp_b = to_dsi_bcnt(var->right_margin, bpp);
+	hbp_b = to_dsi_bcnt(var->left_margin, bpp);
+	hsync_b = to_dsi_bcnt(var->hsync_len, bpp);
+	hex_b = to_dsi_bcnt(dsi_ex_pixel_cnt, bpp);
+	httl_b = hact_b + hsync_b + hfp_b + hbp_b + hex_b;
+
+	hact = hact_b / di->lanes;
+	hfp = hfp_b / di->lanes;
+	hbp = hbp_b / di->lanes;
+	hsync = hsync_b / di->lanes;
+	httl = hact + hfp + hbp + hsync;
+	/* word count in the unit of byte */
+	hsa_wc = (di->burst_mode == DSI_BURST_MODE_SYNC_PULSE) ? \
+		(hsync_b - hss_bcnt - lgp_over_head) : 0;
+
+	/* Hse is with backporch */
+	hbp_wc = (di->burst_mode == DSI_BURST_MODE_SYNC_PULSE) ? \
+		(hbp_b - hse_bct - lgp_over_head) \
+		: (hsync_b + hbp_b - hss_bcnt - lgp_over_head);
+
+	hfp_wc = ((di->burst_mode == DSI_BURST_MODE_BURST) \
+			&& (dsi_hex_en == 0)) ? \
+		(hfp_b + hex_b - lgp_over_head - lgp_over_head) : \
+		(hfp_b - lgp_over_head - lgp_over_head);
+
+	hact_wc =  ((var->xres) * bpp) >> 3;
+
+	/* disable Hex currently */
+	hex_wc = 0;
+
+	/*  There is no hlp with active data segment.  */
+	hlp_wc = (di->burst_mode == DSI_BURST_MODE_SYNC_PULSE) ? \
+		(httl_b - hsync_b - hse_bct - lgp_over_head) : \
+		(httl_b - hss_bcnt - lgp_over_head);
+
+	/* FIXME - need to double check the (*3) is bytes_per_pixel
+	 * from input data or output to panel
+	 */
+	/* dsi_lane_enable - Set according to specified DSI lane count */
+	DSIW(dsi_lane[di->lanes] << DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT, \
+			&dsi->phy_ctrl2);
+	DSIW(dsi_lane[di->lanes] << DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT, \
+			&dsi->cmd1);
+
+	/* SET UP LCD1 TIMING REGISTERS FOR DSI BUS */
+	/* NOTE: Some register values were obtained by trial and error */
+	DSIW((hact << 16) | httl, &dsi_lcd->timing0);
+	DSIW((hsync << 16) | hbp, &dsi_lcd->timing1);
+	/*
+	 * For now the active size is set really low (we'll use 10) to allow
+	 * the hardware to attain V Sync. Once the DSI bus is up and running,
+	 * the final value will be put in place for the active size (this is
+	 * done below). In a later stepping of the processor this workaround
+	 * will not be required.
+	 */
+	DSIW(((var->yres)<<16) | (v_total), &dsi_lcd->timing2);
+
+	DSIW(((var->vsync_len) << 16) | (var->upper_margin), \
+			&dsi_lcd->timing3);
+	/* SET UP LCD1 WORD COUNT REGISTERS FOR DSI BUS */
+	/* Set up for word(byte) count register 0 */
+	DSIW((hbp_wc << 16) | hsa_wc, &dsi_lcd->wc0);
+	DSIW((hfp_wc << 16) | hact_wc, &dsi_lcd->wc1);
+	DSIW((hex_wc << 16) | hlp_wc, &dsi_lcd->wc2);
+	/* calculated value on brownstone:
+	 * WC0: 0x1a0000
+	 * WC1: 0x1500f00
+	 * WC2: 0x1076 */
+
+	/* Configure LCD control register 1 FOR DSI BUS */
+	reg = ((di->rgb_mode << DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT)
+		| (di->burst_mode << DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT)
+		| (di->lpm_line_en ? DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN : 0)
+		| (di->lpm_frame_en ? DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN : 0)
+		| (di->last_line_turn ? DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN \
+			: 0)
+		| (di->hex_slot_en ? 0 : 0)   /* disable Hex slot */
+		| (di->all_slot_en ? 0 : 0)   /* disable all slots */
+		| (di->hbp_en ? DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN : 0)
+		| (di->hact_en ? DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN : 0)
+		| (di->hfp_en ? DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN : 0)
+		| (di->hex_en ? 0 : 0)      /* Hex packet is disabled */
+		| (di->hlp_en ? DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN : 0));
+
+	reg |= (di->burst_mode == DSI_BURST_MODE_SYNC_PULSE) ? \
+		(((di->hsa_en) ? DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN : 0)
+		| (DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN))  /* Hse is always
+							    eabled */
+		:
+		(((di->hsa_en) ? 0 : 0)   /* Hsa packet is disabled */
+		| ((di->hse_en) ? 0 : 0));     /* Hse packet is disabled */
+
+	reg |=  DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN;
+	DSIW(reg, &dsi_lcd->ctrl1);
+	/*Start the transfer of LCD data over the DSI bus*/
+	/* DSI_CTRL_1 */
+	reg = readl(&dsi->ctrl1);
+	reg &= ~(DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK \
+			| DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK);
+	reg |= 0x1 << ((di->id & 1) ? DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT \
+			: DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT);
+
+	reg &= ~(DSI_CTRL_1_CFG_EOTP);
+	if (di->eotp_en)
+		reg |= DSI_CTRL_1_CFG_EOTP;	/* EOTP */
+
+	DSIW(reg, &dsi->ctrl1);
+	/* DSI_CTRL_0 */
+	reg = DSI_CTRL_0_CFG_LCD1_SLV | DSI_CTRL_0_CFG_LCD1_TX_EN \
+	      | DSI_CTRL_0_CFG_LCD1_EN;
+	if (di->id & 2)
+		reg = reg << 1;
+	DSIW(reg, &dsi->ctrl0);
+	udelay(100000);
+
+	/* FIXME - second part of the workaround */
+	DSIW(((var->yres)<<16) | (v_total), &dsi_lcd->timing2);
+}
+
+static int tc358765_reset(void)
+{
+	gpio_set_value(LCD_RST_GPIO, 0);
+	udelay(100000);
+
+	gpio_set_value(LCD_RST_GPIO, 1);
+	udelay(100000);
+
+	return 0;
+}
+
+#define TC358765_CHIPID_REG	0x0580
+#define TC358765_CHIPID		0x6500
+static int dsi_dump_tc358765(void)
+{
+#if 0
+	u32 val;
+
+	tc_read32(PPI_TX_RX_TA, &val);
+	printf("tc35876x - PPI_TX_RX_TA = 0x%x\n", val);
+	tc_read32(PPI_LPTXTIMECNT, &val);
+	printf("tc35876x - PPI_LPTXTIMECNT = 0x%x\n", val);
+	tc_read32(PPI_D0S_CLRSIPOCOUNT, &val);
+	printf("tc35876x - PPI_D0S_CLRSIPOCOUNT = 0x%x\n", val);
+	tc_read32(PPI_D1S_CLRSIPOCOUNT, &val);
+	printf("tc35876x - PPI_D1S_CLRSIPOCOUNT = 0x%x\n", val);
+
+	tc_read32(PPI_D2S_CLRSIPOCOUNT, &val);
+	printf("tc35876x - PPI_D2S_CLRSIPOCOUNT = 0x%x\n", val);
+	tc_read32(PPI_D3S_CLRSIPOCOUNT, &val);
+	printf("tc35876x - PPI_D3S_CLRSIPOCOUNT = 0x%x\n", val);
+
+	tc_read32(PPI_LANEENABLE, &val);
+	printf("tc35876x - PPI_LANEENABLE = 0x%x\n", val);
+	tc_read32(DSI_LANEENABLE, &val);
+	printf("tc35876x - DSI_LANEENABLE = 0x%x\n", val);
+	tc_read32(PPI_STARTPPI, &val);
+	printf("tc35876x - PPI_STARTPPI = 0x%x\n", val);
+	tc_read32(DSI_STARTDSI, &val);
+	printf("tc35876x - DSI_STARTDSI = 0x%x\n", val);
+
+	tc_read32(VPCTRL, &val);
+	printf("tc35876x - VPCTRL = 0x%x\n", val);
+	tc_read32(HTIM1, &val);
+	printf("tc35876x - HTIM1 = 0x%x\n", val);
+	tc_read32(HTIM2, &val);
+	printf("tc35876x - HTIM2 = 0x%x\n", val);
+	tc_read32(VTIM1, &val);
+	printf("tc35876x - VTIM1 = 0x%x\n", val);
+	tc_read32(VTIM2, &val);
+	printf("tc35876x - VTIM2 = 0x%x\n", val);
+	tc_read32(VFUEN, &val);
+	printf("tc35876x - VFUEN = 0x%x\n", val);
+	tc_read32(LVCFG, &val);
+	printf("tc35876x - LVCFG = 0x%x\n", val);
+
+	tc_read32(DSI_INTSTAUS, &val);
+	printf("!! - DSI_INTSTAUS= 0x%x BEFORE\n", val);
+	tc_write32(DSI_INTCLR, 0xFFFFFFFF);
+	tc_read32(DSI_INTSTAUS, &val);
+	printf("!! - DSI_INTSTAUS= 0x%x AFTER\n", val);
+
+	tc_read32(DSI_LANESTATUS0, &val);
+	printf("tc35876x - DSI_LANESTATUS0= 0x%x\n", val);
+	tc_read32(DSIERRCNT, &val);
+	printf("tc35876x - DSIERRCNT= 0x%x\n", val);
+	tc_read32(DSIERRCNT, &val);
+	printf("tc35876x - DSIERRCNT= 0x%x AGAIN\n", val);
+	tc_read32(SYSSTAT, &val);
+	printf("tc35876x - SYSSTAT= 0x%x\n", val);
+#endif
+	return 0;
+}
+
+static int dsi_set_tc358765(struct dsi_info *di, unsigned int twsi_id)
+{
+	unsigned int cur_bus = i2c_get_bus_num();
+	u16 chip_id = 0;
+	int status;
+
+	/* Switch to TWSIx bus */
+	i2c_set_bus_num(twsi_id);
+	status = tc_read16(TC358765_CHIPID_REG, &chip_id);
+	if ((status < 0) || (chip_id != TC358765_CHIPID)) {
+		printf("tc358765 chip ID is 0x%x\n", chip_id);
+		i2c_set_bus_num(cur_bus);
+		return -1;
+	}
+
+	/* REG 0x13C,DAT 0x000C000F */
+	tc_write32(PPI_TX_RX_TA, 0x00040004);
+	/* REG 0x114,DAT 0x0000000A */
+	tc_write32(PPI_LPTXTIMECNT, 0x00000004);
+
+	/* get middle value of mim-max value
+	 * 0-0x13 for 2lanes-rgb888, 0-0x26 for 4lanes-rgb888
+	 * 0-0x21 for 2lanes-rgb565, 0-0x25 for 4lanes-rgb565
+	 */
+	if (di->lanes == 4)
+		status = 0x13;
+	else if (di->bpp == 24)
+		status = 0xa;
+	else
+		status = 0x11;
+	/* REG 0x164,DAT 0x00000005 */
+	tc_write32(PPI_D0S_CLRSIPOCOUNT, status);
+	/* REG 0x168,DAT 0x00000005 */
+	tc_write32(PPI_D1S_CLRSIPOCOUNT, status);
+	if (di->lanes == 4) {
+		/* REG 0x16C,DAT 0x00000005 */
+		tc_write32(PPI_D2S_CLRSIPOCOUNT, status);
+		/* REG 0x170,DAT 0x00000005 */
+		tc_write32(PPI_D3S_CLRSIPOCOUNT, status);
+	}
+
+	/* REG 0x134,DAT 0x00000007 */
+	tc_write32(PPI_LANEENABLE, (di->lanes == 4) ? 0x1f : 0x7);
+	/* REG 0x210,DAT 0x00000007 */
+	tc_write32(DSI_LANEENABLE, (di->lanes == 4) ? 0x1f : 0x7);
+
+	/* REG 0x104,DAT 0x00000001 */
+	tc_write32(PPI_STARTPPI, 0x0000001);
+	/* REG 0x204,DAT 0x00000001 */
+	tc_write32(DSI_STARTDSI, 0x0000001);
+
+	/* REG 0x450,DAT 0x00012020, VSDELAY = 8 pixels */
+	tc_write32(VPCTRL, 0x00800020);
+
+	/* REG 0x454,DAT 0x00200008*/
+	tc_write32(HTIM1, 0x00200008);
+
+	/* REG 0x45C,DAT 0x00040004*/
+	tc_write32(VTIM1, 0x00040004);
+
+        /* Test TSB */
+        tc_write32(0x0464, 0x00000001); /* VFUEN */
+        tc_write32(0x04A0, 0x00448006); /* LVPHY0 */
+        /* Wait is needed heare */
+        tc_write32(0x04A0, 0x00048006); /* LVPHY0*/
+        tc_write32(0x0504, 0x00000004); /* SYSRST */
+
+        tc_write32(0x0520, 0x0000001F); /* GPIOC */
+        tc_write32(0x0524, 0x00000000); /* GPIOO */
+
+	/* REG 0x49C,DAT 0x00000201 */
+	tc_write32(LVCFG, 0x00000001);
+
+	dsi_dump_tc358765();
+	i2c_set_bus_num(cur_bus);
+
+	return 0;
+}
+
+static int brownstone_dsi_init(struct pxa168fb_info *fbi)
+{
+	struct pxa168fb_mach_info *mi = fbi->mi;
+	struct dsi_info *di = (struct dsi_info *)mi->phy_info;
+	int ret = 0;
+
+	/* reset DSI controller */
+	dsi_reset(di, 1);
+	udelay(1000);
+
+	/* disable continuous clock */
+	dsi_cclk_set(di, 0);
+
+	/*  reset the bridge */
+	tc358765_reset();
+
+	/* dsi out of reset */
+	dsi_reset(di, 0);
+
+	/* set dphy */
+	dsi_set_dphy(fbi);
+
+	/* set dsi controller */
+	dsi_set_controller(fbi);
+
+	/* turn on DSI continuous clock */
+	dsi_cclk_set(di, 1);
+
+	/* set dsi to dpi conversion chip */
+	if (mi->phy_type == DSI2DPI) {
+		ret = dsi_set_tc358765(di, mi->twsi_id);
+		if (ret < 0)
+			printf("dsi2dpi_set error!\n");
+	}
+
+	return 0;
+}
+
+struct lcd_regs *get_regs(struct pxa168fb_info *fbi)
+{
+	struct lcd_regs *regs = (struct lcd_regs *)((unsigned)fbi->reg_base);
+
+	if (fbi->id == 0)
+		regs = (struct lcd_regs *)((unsigned)fbi->reg_base + 0xc0);
+	if (fbi->id == 2)
+		regs = (struct lcd_regs *)((unsigned)fbi->reg_base + 0x200);
+
+	return regs;
+}
+
+u32 dma_ctrl_read(struct pxa168fb_info *fbi, int ctrl1)
+{
+	u32 reg = (u32)fbi->reg_base + dma_ctrl(ctrl1, fbi->id);
+	return __raw_readl(reg);
+}
+
+void dma_ctrl_write(struct pxa168fb_info *fbi, int ctrl1, u32 value)
+{
+	u32 reg = (u32)fbi->reg_base + dma_ctrl(ctrl1, fbi->id);
+	__raw_writel(value, reg);
+}
+
+void dma_ctrl_set(struct pxa168fb_info *fbi, int ctrl1, u32 mask, u32 value)
+{
+	u32 reg = (u32)fbi->reg_base + dma_ctrl(ctrl1, fbi->id);
+	u32 tmp1, tmp2;
+
+	tmp1 = tmp2 = __raw_readl(reg); tmp2 &= ~mask; tmp2 |= value;
+	if (tmp1 != tmp2)
+		__raw_writel(tmp2, reg);
+}
+
+static void set_pix_fmt(struct fb_var_screeninfo *var, int pix_fmt)
+{
+	switch (pix_fmt) {
+	case PIX_FMT_RGB565:
+		var->bits_per_pixel = 16;
+		var->red.offset = 11;    var->red.length = 5;
+		var->green.offset = 5;   var->green.length = 6;
+		var->blue.offset = 0;    var->blue.length = 5;
+		var->transp.offset = 0;  var->transp.length = 0;
+		var->nonstd &= ~0xff0fffff;
+		break;
+	case PIX_FMT_BGR565:
+		var->bits_per_pixel = 16;
+		var->red.offset = 0;     var->red.length = 5;
+		var->green.offset = 5;   var->green.length = 6;
+		var->blue.offset = 11;   var->blue.length = 5;
+		var->transp.offset = 0;  var->transp.length = 0;
+		var->nonstd &= ~0xff0fffff;
+		break;
+	case PIX_FMT_RGB1555:
+		var->bits_per_pixel = 16;
+		var->red.offset = 10;    var->red.length = 5;
+		var->green.offset = 5;   var->green.length = 5;
+		var->blue.offset = 0;    var->blue.length = 5;
+		var->transp.offset = 15; var->transp.length = 1;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 5 << 20;
+		break;
+	case PIX_FMT_BGR1555:
+		var->bits_per_pixel = 16;
+		var->red.offset = 0;     var->red.length = 5;
+		var->green.offset = 5;   var->green.length = 5;
+		var->blue.offset = 10;   var->blue.length = 5;
+		var->transp.offset = 15; var->transp.length = 1;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 5 << 20;
+		break;
+	case PIX_FMT_RGB888PACK:
+		var->bits_per_pixel = 24;
+		var->red.offset = 16;    var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 0;    var->blue.length = 8;
+		var->transp.offset = 0;  var->transp.length = 0;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 6 << 20;
+		break;
+	case PIX_FMT_BGR888PACK:
+		var->bits_per_pixel = 24;
+		var->red.offset = 0;     var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 16;   var->blue.length = 8;
+		var->transp.offset = 0;  var->transp.length = 0;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 6 << 20;
+		break;
+	case PIX_FMT_RGB888UNPACK:
+		var->bits_per_pixel = 32;
+		var->red.offset = 16;    var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 0;    var->blue.length = 8;
+		var->transp.offset = 0;  var->transp.length = 8;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 7 << 20;
+		break;
+	case PIX_FMT_BGR888UNPACK:
+		var->bits_per_pixel = 32;
+		var->red.offset = 0;     var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 16;   var->blue.length = 8;
+		var->transp.offset = 0;  var->transp.length = 8;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 7 << 20;
+		break;
+	case PIX_FMT_RGBA888:
+		var->bits_per_pixel = 32;
+		var->red.offset = 16;    var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 0;    var->blue.length = 8;
+		var->transp.offset = 24; var->transp.length = 8;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 8 << 20;
+		break;
+	case PIX_FMT_BGRA888:
+		var->bits_per_pixel = 32;
+		var->red.offset = 0;     var->red.length = 8;
+		var->green.offset = 8;   var->green.length = 8;
+		var->blue.offset = 16;   var->blue.length = 8;
+		var->transp.offset = 24; var->transp.length = 8;
+		var->nonstd &= ~0xff0fffff;
+		var->nonstd |= 8 << 20;
+		break;
+	}
+}
+
+/*
+ * The hardware clock divider has an integer and a fractional
+ * stage:
+ *
+ *	clk2 = clk_in / integer_divider
+ *	clk_out = clk2 * (1 - (fractional_divider >> 12))
+ *
+ * Calculate integer and fractional divider for given clk_in
+ * and clk_out.
+ */
+static void set_clock_divider(struct pxa168fb_info *fbi)
+{
+	struct pxa168fb_mach_info *mi = fbi->mi;
+
+	if (! fbi->id) {
+		writel(mi->sclk_div, fbi->reg_base + clk_div(fbi->id));
+		if (mi->phy_type & LVDS)
+			writel(mi->sclk_div, fbi->reg_base + LCD_LVDS_SCLK_DIV_WR);
+	} else
+		writel(0x60010005, fbi->reg_base + clk_div(fbi->id));
+}
+
+static u32 dma_ctrl0_update(int active, struct pxa168fb_mach_info *mi,
+		u32 x, u32 pix_fmt)
+{
+	if (active)
+		x |= 0x00000100;
+	else
+		x &= ~0x00000100;
+
+	/* If we are in a pseudo-color mode, we need to enable
+	 * palette lookup  */
+	if (pix_fmt == PIX_FMT_PSEUDOCOLOR)
+		x |= 0x10000000;
+
+	/* Configure hardware pixel format */
+	x &= ~(0xF << 16);
+	x |= (pix_fmt >> 1) << 16;
+
+	/* Check YUV422PACK */
+	x &= ~((1 << 9) | (1 << 11) | (1 << 10) | (1 << 12));
+	if (((pix_fmt >> 1) == 5) || (pix_fmt & 0x1000)) {
+		x |= 1 << 9;
+		x |= (mi->panel_rbswap) << 12;
+		if (pix_fmt == 11)
+			x |= 1 << 11;
+		if (pix_fmt & 0x1000)
+			x |= 1 << 10;
+	} else {
+		/* Check red and blue pixel swap.
+		 * 1. source data swap. BGR[M:L] rather than RGB[M:L] is
+		 * stored in memeory as source format.
+		 * 2. panel output data swap
+		 */
+		x |= (((pix_fmt & 1) ^ 1) ^ (mi->panel_rbswap)) << 12;
+	}
+	/* enable horizontal smooth filter for both graphic and video layers */
+	x |= CFG_GRA_HSMOOTH(1) | CFG_DMA_HSMOOTH(1);
+
+	return x;
+}
+
+static void set_dma_control0(struct pxa168fb_info *fbi)
+{
+	struct pxa168fb_mach_info *mi;
+	u32 x = 0, active, pix_fmt = fbi->pix_fmt;
+
+	/* Set bit to enable graphics DMA */
+	if (fbi->id != 1)
+		dma_ctrl_set(fbi, 0, CFG_ARBFAST_ENA(1), CFG_ARBFAST_ENA(1));
+
+	mi = fbi->mi;
+	active = fbi->active;
+	x = dma_ctrl_read(fbi, 0);
+	active = 1;
+	x = dma_ctrl0_update(active, mi, x, pix_fmt);
+	dma_ctrl_write(fbi, 0, x);
+	/* enable multiple burst request in DMA AXI bus arbiter for
+	 * faster read
+	 */
+	x = readl(fbi->reg_base + LCD_SPU_DMA_CTRL0);
+	x |= CFG_ARBFAST_ENA(1);
+	writel(x, fbi->reg_base + LCD_SPU_DMA_CTRL0);
+}
+
+static void set_dma_control1(struct pxa168fb_info *fbi, int sync)
+{
+	u32 x;
+
+	/* Configure default bits: vsync triggers DMA, gated clock
+	 * enable, power save enable, configure alpha registers to
+	 * display 100% graphics, and set pixel command.
+	 */
+	x = dma_ctrl_read(fbi, 1);
+	/* We trigger DMA on the falling edge of vsync if vsync is
+	 * active low, or on the rising edge if vsync is active high.
+	 */
+	if (!(sync & FB_SYNC_VERT_HIGH_ACT))
+		x |= 0x08000000;
+	else
+		x &= ~0x08000000;
+	dma_ctrl_write(fbi, 1, x);
+}
+
+static void set_graphics_start(struct pxa168fb_info *fb, int xoffset,
+		int yoffset)
+{
+	struct pxa168fb_info *fbi = fb;
+	struct fb_var_screeninfo *var = fb->var;
+	int pixel_offset;
+	unsigned long addr;
+	static int debugcount;
+	struct lcd_regs *regs;
+
+	if (debugcount < 10)
+		debugcount++;
+
+	pixel_offset = (yoffset * var->xres_virtual) + xoffset;
+	addr = fbi->fb_start_dma + (pixel_offset * (var->bits_per_pixel >> 3));
+
+	regs = get_regs(fbi);
+	writel(addr, &regs->g_0);
+}
+
+static void set_screen(struct pxa168fb_info *fbi, struct pxa168fb_mach_info *mi)
+{
+	struct fb_var_screeninfo *var = fbi->var;
+	struct lcd_regs *regs = get_regs(fbi);
+	struct dsi_info *di = NULL;
+	u32 x, h_porch, vsync_ctrl, vec = 10;
+	u32 xres = var->xres, yres = var->yres;
+	u32 xres_z = var->xres, yres_z = var->yres;
+	u32 xres_virtual = var->xres_virtual;
+	u32 bits_per_pixel = var->bits_per_pixel;
+
+	if (mi->phy_type & (DSI2DPI | DSI)) {
+		di = (struct dsi_info *)mi->phy_info;
+		vec = ((di->lanes <= 2) ? 1 : 2) * 10 * di->bpp / 8 / di->lanes;
+	}
+	/* resolution, active */
+	writel((var->yres << 16) | var->xres, &regs->screen_active);
+	/* pitch, pixels per line */
+	x = readl(&regs->g_pitch);
+	if (mi->index)
+		x = (x & ~0xFFFF) | ((pxa168_fbi[0]->var->xres_virtual * bits_per_pixel) >> 3);
+	else
+		x = (x & ~0xFFFF) | ((xres_virtual * bits_per_pixel) >> 3);
+	writel(x, &regs->g_pitch);
+
+	/* resolution, src size */
+	if (mi->index) {
+		/* share same content on pn0 and tv path */
+		writel((pxa168_fbi[0]->var->yres << 16) | pxa168_fbi[0]->var->xres,
+				&regs->g_size);
+	} else {
+		writel((yres << 16) | xres, &regs->g_size);
+	}
+	/* resolution, dst size */
+	writel((yres_z << 16) | xres_z, &regs->g_size_z);
+
+	/* h porch, left/right margin */
+	if (mi->phy_type & (DSI2DPI | DSI)) {
+		h_porch = (var->xres + var->right_margin) * vec / 10
+			- var->xres;
+		h_porch = (var->left_margin * vec / 10) << 16 | h_porch;
+	} else
+		h_porch = (var->left_margin) << 16 | var->right_margin;
+	writel(h_porch, &regs->screen_h_porch);
+	/* v porch, upper/lower margin */
+	writel((var->upper_margin << 16) | var->lower_margin,
+		&regs->screen_v_porch);
+
+	/* vsync ctrl */
+	if (mi->phy_type & (DSI2DPI | DSI))
+		vsync_ctrl = 0x01330133;
+	else {
+		if ((fbi->id == 0) || (fbi->id == 2))
+			vsync_ctrl = ((var->width + var->left_margin) << 16)
+				| (var->width + var->left_margin);
+		else
+			vsync_ctrl = ((var->xres + var->right_margin) << 16)
+				| (var->xres + var->right_margin);
+	}
+	writel(vsync_ctrl, &regs->vsync_ctrl);  /* FIXME */
+
+	/* blank color */
+	writel(0x00000000, &regs->blank_color);
+}
+
+static void set_dumb_panel_control(struct pxa168fb_info *fbi,
+		struct pxa168fb_mach_info *mi)
+{
+	u32 x;
+
+	x = readl(fbi->reg_base + intf_ctrl(fbi->id)) & 0x00000001;
+	x |= (fbi->is_blanked ? 0x7 : mi->dumb_mode) << 28;
+	x |= (fbi->var->sync & 2) ? 0 : 0x00000008;
+	x |= (fbi->var->sync & 1) ? 0 : 0x00000004;
+	x |= (fbi->var->sync & 8) ? 0 : 0x00000020;
+	if (fbi->id == 1) {
+		/* enable AXI urgent flag */
+		x |= (1 << 12) | (0xff << 16);
+		writel(x, fbi->reg_base + intf_ctrl(fbi->id));  /* FIXME */
+		return;
+	} else {
+		x |= mi->gpio_output_data << 20;
+		x |= mi->gpio_output_mask << 12;
+	}
+	x |= mi->panel_rgb_reverse_lanes ? 0x00000080 : 0;
+	x |= mi->invert_composite_blank ? 0x00000040 : 0;
+	x |= mi->invert_pix_val_ena ? 0x00000010 : 0;
+	x |= mi->invert_pixclock ? 0x00000002 : 0;
+
+	writel(x, fbi->reg_base + intf_ctrl(fbi->id));  /* FIXME */
+}
+
+static void set_dumb_screen_dimensions(struct pxa168fb_info *fbi,
+		struct pxa168fb_mach_info *mi)
+{
+	struct lcd_regs *regs = get_regs(fbi);
+	struct fb_var_screeninfo *v = fbi->var;
+	struct dsi_info *di = NULL;
+	int x;
+	int y;
+	int vec = 10;
+
+	/* FIXME - need to double check (*3) and (*2) */
+	if (mi->phy_type & (DSI2DPI | DSI)) {
+		di = (struct dsi_info *)mi->phy_info;
+		vec = ((di->lanes <= 2) ? 1 : 2) * 10 * di->bpp / 8 / di->lanes;
+	}
+
+	x = v->xres + v->right_margin + v->hsync_len + v->left_margin;
+	x = x * vec / 10;
+	y = v->yres + v->lower_margin + v->vsync_len + v->upper_margin;
+
+	writel((y << 16) | x, &regs->screen_size);
+}
+
+static int pxa168fb_set_par(struct pxa168fb_info *fb,
+		struct pxa168fb_mach_info *mi)
+{
+	struct pxa168fb_info *fbi = fb;
+	struct fb_var_screeninfo *var = fb->var;
+	int pix_fmt;
+	u32 x;
+
+	/* Determine which pixel format we're going to use */
+	pix_fmt = mi->pix_fmt;    /* choose one */
+
+	if (pix_fmt < 0)
+		return pix_fmt;
+	fbi->pix_fmt = pix_fmt;
+
+	/* Set additional mode info */
+	if (pix_fmt == PIX_FMT_PSEUDOCOLOR)
+		fb->fix->visual = FB_VISUAL_PSEUDOCOLOR;
+	else
+		fb->fix->visual = FB_VISUAL_TRUECOLOR;
+
+	/* convet var to video mode */
+	set_pix_fmt(var, pix_fmt);
+	if (!var->xres_virtual)
+		var->xres_virtual = var->xres;
+	if (!var->yres_virtual)
+		var->yres_virtual = var->yres * 2;
+	/* Calculate clock divisor. */
+	set_clock_divider(fbi);
+	/* Configure dma ctrl regs. */
+	set_dma_control1(fbi, fb->var->sync);
+
+	/* Configure graphics DMA parameters.
+	 * Configure global panel parameters.
+	 */
+	set_screen(fbi, mi);
+	/* Configure dumb panel ctrl regs & timings */
+	set_dumb_panel_control(fbi, mi);
+	set_dumb_screen_dimensions(fbi, mi);
+	x = readl(fbi->reg_base + intf_ctrl(fbi->id));
+	if ((x & 1) == 0)
+		writel(x | 1, fbi->reg_base + intf_ctrl(fbi->id));
+
+	set_graphics_start(fbi, fbi->var->xoffset, fbi->var->yoffset);
+	set_dma_control0(fbi);
+	return 0;
+}
+
+static void pxa168fb_init_mode(struct pxa168fb_info *fbi,
+			      struct pxa168fb_mach_info *mi)
+{
+	struct fb_var_screeninfo *var = fbi->var;
+
+	/* Init mode */
+	var->xres = mi->modes->xres;
+	var->yres = mi->modes->yres;
+	var->xres_virtual = mi->modes->xres;
+	var->yres_virtual = mi->modes->yres;
+	var->xoffset = 0;
+	var->yoffset = 0;
+	var->pixclock = mi->modes->pixclock;
+	var->left_margin = mi->modes->left_margin;
+	var->right_margin = mi->modes->right_margin;
+	var->upper_margin = mi->modes->upper_margin;
+	var->lower_margin = mi->modes->lower_margin;
+	var->hsync_len = mi->modes->hsync_len;
+	var->vsync_len = mi->modes->vsync_len;
+	var->sync = mi->modes->sync;
+
+	/* Init settings. */
+	var->xres_virtual = var->xres;
+	var->yres_virtual = var->yres * 2;
+}
+
+static void pxa168fb_set_default(struct pxa168fb_info *fbi,
+		struct pxa168fb_mach_info *mi)
+{
+	struct lcd_regs *regs = get_regs(fbi);
+	u32 dma_ctrl1 = 0x2012ff81;
+	u32 burst_length = (mi->burst_len == 16) ?
+		CFG_CYC_BURST_LEN16 : CFG_CYC_BURST_LEN8;
+	/* Configure default register values */
+	writel(mi->io_pin_allocation_mode | burst_length,
+			fbi->reg_base + SPU_IOPAD_CONTROL);
+	/* enable 16 cycle burst length to get better formance */
+	writel(0x00000000, &regs->blank_color);
+	writel(0x00000000, &regs->g_1);
+	writel(0x00000000, &regs->g_start);
+
+	/* Configure default bits: vsync triggers DMA,
+	 * power save enable, configure alpha registers to
+	 * display 100% graphics, and set pixel command.
+	 */
+	if (fbi->id == 1) {
+		writel(0x60010005, fbi->reg_base + LCD_TCLK_DIV);
+
+		if (mi->phy_type & (DSI2DPI | DSI))
+			dma_ctrl1 = 0xa03eff00;
+		else
+			dma_ctrl1 = 0x203eff00;	/* FIXME */
+	}
+	dma_ctrl_write(fbi, 1, dma_ctrl1);
+}
+
+static void rect_fill(unsigned short *addr, int left, int up, int right,
+		      int down, int width, unsigned short color)
+{
+	int i, j;
+	for (j = up; j < down; j++)
+		for (i = left; i < right; i++)
+			*(addr + j * width + i) = color;
+}
+
+void test_panel(int xres, int yres)
+{
+	int w = xres, h = yres;
+	int x = w / 8, y = h / 8;
+
+	printf("panel test: white background, test RGB color\r\n");
+	memset((unsigned short *) DEFAULT_FB_BASE, 0xff,
+	       w * h * 2);
+	udelay(50 * 1000);
+	rect_fill((unsigned short *) DEFAULT_FB_BASE, x, y, w - x,
+		  h - y, w, 0x1f);
+	udelay(50 * 1000);
+	rect_fill((unsigned short *) DEFAULT_FB_BASE, x * 2, y * 2,
+		  w - x * 2, h - y * 2, w, 0x7e0);
+	udelay(50 * 1000);
+	rect_fill((unsigned short *) DEFAULT_FB_BASE, x * 3, y * 3,
+		  w - x * 3, h - y * 3, w, 0xf800);
+	udelay(50 * 1000);
+}
+
+void test_vid(int xres, int yres)
+{
+	u32 length = xres*yres*3 >> 1;
+	int x, y;
+	char *px;
+
+	memset((void *)DEFAULT_VID_BASE, 0, length);
+	memset((void *)DEFAULT_VID_BASE2, 0xf0, length);
+
+	for(y = 0; y < yres; y++) {
+		px = (char *)(DEFAULT_VID_BASE2 + y * xres+ xres - 50);
+		for(x = 0; x < 50; x++)
+			*px++ = 0xcf;
+	}
+	//green
+	for(y = 0; y < yres; y++) {
+		px = (char *)(DEFAULT_VID_BASE + y * xres);
+		for(x = 0; x < 50; x++)
+			*px++ = 0xcf;
+	}
+}
+
+/* select LVDS_PHY_CTL_EXTx */
+#define lvds_ext_select(ext, tmp, reg) do {				\
+	reg = DISPLAY_CONTROLLER_BASE + LVDS_PHY_CTL;		\
+	if (ext) {							\
+		/* select LVDS_PHY_CTL_EXTx */				\
+		tmp = readl(reg) & (~LVDS_PHY_EXT_MASK);		\
+		writel(tmp | (ext - 1) << LVDS_PHY_EXT_SHIFT, reg);	\
+		/* switch to LVDS_PHY_CTL_EXTx */			\
+		reg -= LVDS_PHY_CTL; reg += LVDS_PHY_CTL_EXT;		\
+	}								\
+} while (0)
+
+static u32 lvds_get(int ext)
+{
+	u32 reg, tmp;
+
+	lvds_ext_select(ext, tmp, reg);
+
+	return readl(reg);
+}
+
+static int lvds_set(int ext, u32 mask, u32 val)
+{
+	u32 reg, tmp, tmp2;
+
+	lvds_ext_select(ext, tmp, reg);
+
+	tmp = tmp2 = readl(reg);
+	tmp2 &= ~mask; tmp2 |= val;
+	if (tmp != tmp2)
+		writel(tmp2, reg);
+
+	return 0;
+}
+
+static void lvds_dump(struct lvds_info *lvds)
+{
+	u32 reg = DISPLAY_CONTROLLER_BASE + LCD_2ND_BLD_CTL;
+	char *str;
+
+	switch (lvds->src) {
+	case LVDS_SRC_PN:
+		str = "PN";
+		break;
+	case LVDS_SRC_CMU:
+		str = "CMU";
+		break;
+	case LVDS_SRC_PN2:
+		str = "PN2";
+		break;
+	case LVDS_SRC_TV:
+		str = "TV";
+		break;
+	default:
+		str = "?";
+		break;
+	};
+
+	printf("lvds_info: src %s fmt %s\n", str,
+		(lvds->fmt & LVDS_FMT_18BIT) ? "18bit" : "24bit");
+	printf("LCD_2ND_BLD_CTL(0x%x): 0x%x\n\n", reg & 0xfff, readl(reg));
+
+	printf("LVDS_PHY_CTL: 0x%x\n", lvds_get(0));
+	printf("        EXT1: 0x%x\n", lvds_get(1));
+	printf("        EXT2: 0x%x\n", lvds_get(2));
+	printf("        EXT3: 0x%x\n", lvds_get(3));
+	printf("        EXT4: 0x%x\n", lvds_get(4));
+	printf("        EXT5: 0x%x\n", lvds_get(5));
+}
+
+static int pxa688_lvds_config(struct lvds_info *lvds)
+{
+	u32 reg = DISPLAY_CONTROLLER_BASE + LCD_2ND_BLD_CTL;
+	u32 val = readl(reg) & ~(LVDS_SRC_MASK | LVDS_FMT_MASK);
+
+	val |= (lvds->src << LVDS_SRC_SHIFT) | (lvds->fmt << LVDS_FMT_SHIFT);
+	writel(val, reg);
+
+	return 0;
+}
+
+static int pxa688_lvds_init(struct lvds_info *lvds)
+{
+	u32 mask, val;
+	int count = 100000;
+
+	/* configure lvds src and fmt */
+	pxa688_lvds_config(lvds);
+
+	/* release LVDS PHY from reset */
+	lvds_set(0, LVDS_RST, 0);
+	udelay(100);
+
+	/* disable LVDS channel 0-5 power-down */
+	lvds_set(0, LVDS_PD_CH_MASK, 0);
+
+	/* select LVDS_PCLK instead of REFCLK as LVDS PHY clock */
+	lvds_set(0, LVDS_CLK_SEL, LVDS_CLK_SEL_LVDS_PCLK);
+
+	/* power up IP */
+	lvds_set(0, LVDS_PU_IVREF, LVDS_PU_IVREF);
+
+	/* REFDIV = 0x3, reference clock divider
+	 * FBDIV = 0xa, feedback clock divider
+	 * KVCO = 0x4, 1.7G - 1.9G */
+	mask = LVDS_REFDIV_MASK | LVDS_FBDIV_MASK | LVDS_REFDIV_MASK
+		| LVDS_CTUNE_MASK | LVDS_VREG_IVREF_MASK
+		| LVDS_VDDL_MASK | LVDS_VDDM_MASK;
+	val = (0x6 << LVDS_REFDIV_SHIFT) | (0x1 << LVDS_FBDIV_SHIFT)
+		| (0x4 << LVDS_KVCO_SHIFT | (0x2 << LVDS_CTUNE_SHIFT)
+		| (0x2 << LVDS_VREG_IVREF_SHIFT) | (0x9 << LVDS_VDDL_SHIFT)
+		| (0x1 << LVDS_VDDM_SHIFT));
+	lvds_set(3, mask, val);
+
+	/* VCO_VRNG = 0x3, LVDS PLL V to I gain control, for KVCO[3:0] = 0x4 */
+	mask = LVDS_VCO_VRNG_MASK | LVDS_ICP_MASK | LVDS_PI_EN
+		| LVDS_VCODIV_SEL_SE_MASK | LVDS_INTPI_MASK;
+	val = (0x3 << LVDS_VCO_VRNG_SHIFT) | (0x1 << LVDS_ICP_SHIFT)
+		| LVDS_PI_EN | (0xd << LVDS_VCODIV_SEL_SE_SHIFT)
+		| (0x3 << LVDS_INTPI_SHIFT);
+	lvds_set(4, mask, val);
+
+	/* enable PUPLL/PUTX to power up rest of PLL and TX */
+	lvds_set(0, LVDS_PU_TX | LVDS_PU_PLL, LVDS_PU_TX | LVDS_PU_PLL);
+
+	/* poll on lock bit until LVDS PLL locks */
+	while (!(lvds_get(0) & LVDS_PLL_LOCK) && count--);
+	if (count <= 0) {
+		printf("lvds init failed\n");
+		lvds_dump(lvds);
+	}
+
+	/* enable common mode feedback circuit */
+	mask = LVDS_SELLV_OP9_MASK | LVDS_SELLV_OP7_MASK | LVDS_SELLV_OP6_MASK
+		| LVDS_SELLV_TXDATA_MASK | LVDS_SELLV_TXCLK_MASK | LVDS_TX_DIF_CM_MASK
+		| LVDS_TX_DIF_AMP_MASK | LVDS_TX_TERM_EN | LVDS_TX_CMFB_EN;
+	val = (0x1 << LVDS_SELLV_OP9_SHIFT) | (0x1 << LVDS_SELLV_OP7_SHIFT)
+		| (0x1 << LVDS_SELLV_OP6_SHIFT) | (0xa << LVDS_SELLV_TXDATA_SHIFT)
+		| (0xa << LVDS_SELLV_TXCLK_SHIFT) | (0x3 << LVDS_TX_DIF_CM_SHIFT)
+		| (0x8 << LVDS_TX_DIF_AMP_SHIFT) | LVDS_TX_CMFB_EN;
+	lvds_set(2, mask, val);
+
+	/* Flip all the N\P pins in order to get correct display,
+	 * the pins might be inverted in the chip */
+	lvds_set(1, LVDS_POL_SWAP_MASK, 0x3f << LVDS_POL_SWAP_SHIFT);
+
+	return 0;
+}
+
+void *pxa168fb_init(struct pxa168fb_mach_info *mi)
+{
+	struct pxa168fb_info *fbi = malloc(sizeof(struct pxa168fb_info));
+	struct dsi_info *di = NULL;
+	struct lvds_info *lvds = NULL;
+	u32 dma0, i;
+	u32 cea_id = 4; /* 720p60 */
+	u32 enable_3d = 0;
+
+	memset(fbi, 0, sizeof(struct pxa168fb_info));
+	/* Initialize private data */
+	fbi->panel_rbswap = mi->panel_rbswap;
+	fbi->id = mi->index;
+	pxa168_fbi[mi->index] = fbi;
+	fbi->mi = mi;
+	fbi->var = malloc(sizeof(struct fb_var_screeninfo));
+	fbi->fix = malloc(sizeof(struct fb_fix_screeninfo));
+
+	memset(fbi->var, 0, sizeof(struct fb_var_screeninfo));
+	memset(fbi->fix, 0, sizeof(struct fb_fix_screeninfo));
+	fbi->is_blanked = 0;
+	fbi->debug = 0;
+	fbi->active = mi->active;
+
+	/* Map LCD controller registers */
+	fbi->reg_base = (void *)DISPLAY_CONTROLLER_BASE;
+	if (!fbi->id) {
+		if (mi->phy_type & (DSI2DPI | DSI)) {
+			di = (struct dsi_info *)mi->phy_info;
+			di->regs = DSI1_REG_BASE;     /* DSI 1 */
+		} else if (mi->phy_type & LVDS)
+			lvds = (struct lvds_info *)mi->phy_info;
+#ifdef CONFIG_HDMI
+	} else {
+		mi->modes = &cea_modes[cea_id];
+#endif
+	}
+
+	/*
+	 * Allocate framebuffer memory
+	 */
+	fbi->fb_size = DEFAULT_FB_SIZE;
+	fbi->fb_start = (unsigned int *) DEFAULT_FB_BASE;
+	fbi->fb_start_dma = DEFAULT_FB_BASE;
+	memset(fbi->fb_start, 0x0, fbi->fb_size);
+
+	/*
+	 * init video mode data
+	 */
+	pxa168fb_init_mode(fbi, mi);
+
+	/* LCD_TOP_CTRL control reg */
+	if (! fbi->id)
+		writel(VDMA_ENABLE, fbi->reg_base + LCD_TOP_CTRL);
+
+	/*
+	 * Fill in sane defaults
+	 */
+	pxa168fb_set_default(fbi, mi);	/* FIXME */
+	pxa168fb_set_par(fbi, mi);
+
+
+	dma0 = dma_ctrl_read(fbi, 0);
+	/* toggle left/right for 3d */
+	if (enable_3d && 1 == fbi->id)
+		dma0 |= 1 << 7;
+	else
+		dma0 &= ~(1 << 7);
+	dma_ctrl_write(fbi, 0, dma0);
+
+	if(!fbi->id) {
+		if (mi->phy_type & (DSI2DPI | DSI))
+			/* phy interface init */
+			brownstone_dsi_init(fbi);
+		else if (mi->phy_type & LVDS)
+			pxa688_lvds_init(lvds);
+	}
+#ifdef CONFIG_HDMI
+	else
+		hdmi_init(fbi->var, cea_id, enable_3d); /* 4: 720P60 32:1920@24 */
+#endif
+	/* dump all lcd and dsi registers for debug purpose */
+#if defined(DEBUG_PXA168FB)
+	printf("lcd regs:\n");
+	for (i = 0; i < 0x300; i += 4) {
+		if (!(i % 16) && i)
+			printf("\n0x%3x: ", i);
+		printf(" %8x", readl(fbi->reg_base + i));
+	}
+	if (mi->phy_type & (DSI2DPI | DSI)) {
+		printf("\n dsi regs:");
+		for (i = 0x0; i < 0x200; i += 4) {
+			if (!(i % 16))
+				printf("\n0x%3x: ", i);
+			printf(" %8x", readl(di->regs + i));
+		}
+	}
+	printf("\n");
+	test_panel(mi->modes->xres, mi->modes->yres);
+#endif
+
+	return (void *)fbi;
+}
+
+#ifdef CONFIG_HDMI
+extern void hdmi_3d_sync_view(void);
+#endif
+void pxa168fb_vid(u32 enable, u32 xres, u32 yres)
+{
+	struct pxa168fb_info *fbi = pxa168_fbi[1];
+	struct lcd_regs *regs = get_regs(fbi);
+	u32 v, dma0, dma1, len = xres*yres;
+
+	if (! enable) {
+		dma0 = dma_ctrl_read(fbi, 0);
+		dma0 &= ~0x1;
+		dma_ctrl_write(fbi, 0, dma0);
+		return;
+	}
+
+	printf("video xres %d yres %d\n", xres, yres);
+	test_vid(xres, yres);
+
+	writel(DEFAULT_VID_BASE, &regs->v_y0);
+	writel(DEFAULT_VID_BASE2, &regs->v_y1);
+	writel(DEFAULT_VID_BASE + len, &regs->v_u0);
+	writel(DEFAULT_VID_BASE + len + (len >> 2), &regs->v_v0);
+	writel(DEFAULT_VID_BASE2 + len, &regs->v_u1);
+	writel(DEFAULT_VID_BASE2 + len + (len >> 2), &regs->v_v1);
+	/* start address on screen */
+	writel((80 << 16) | 80, &regs->v_start);
+	//writel((top << 16) | left, &regs->v_start);
+	/* pitch, pixels per line */
+	writel(xres & 0xFFFF, &regs->v_pitch_yc);
+	writel((xres/4) << 16 | (xres/4), &regs->v_pitch_uv);
+	/* resolution, src size */
+	writel((yres << 16) | xres, &regs->v_size);
+	/* resolution, dst size */
+	writel((yres << 16) | xres, &regs->v_size_z);
+
+	dma1 = dma_ctrl_read(fbi, 1);
+	dma1 |= CFG_ALPHA_MODE(2) | CFG_ALPHA(0xff);
+	dma_ctrl_write(fbi, 1, dma1);
+
+	dma0 = dma_ctrl_read(fbi, 0);
+	/* vid dma, 420p and yuv2rgb */
+	dma0 |= 0x1 | 0x2 | (7 << 20);
+	v = readl(fbi->reg_base + TV_FRAMEDONE_ENA_MASK);
+	writel(0, fbi->reg_base + SPU_IRQ_ISR);
+	/* enable video layer in vblank period */
+	while (! (TV_FRAMEDONE_ENA_MASK & readl(fbi->reg_base + SPU_IRQ_ISR)));
+#ifdef CONFIG_HDMI
+	hdmi_3d_sync_view();
+#endif
+	dma_ctrl_write(fbi, 0, dma0);
+}
+
+void pxa168fb_vid_sync(void)
+{
+	struct pxa168fb_info *fbi = pxa168_fbi[1];
+	u32 dma0;
+
+	dma0 = dma_ctrl_read(fbi, 0);
+	/* we only sync if vid dma is on */
+	if (!(dma0 & 0x1))
+		return;
+
+	writel(0, fbi->reg_base + SPU_IRQ_ISR);
+	/* wait for vid layer frame 1 eof */
+	while (! (TV_DMA_FRAME_IRQ1_ENA_MASK & readl(fbi->reg_base + SPU_IRQ_ISR)));
+	writel(0, fbi->reg_base + SPU_IRQ_ISR);
+	/* load after eof of this frame */
+	/* TVSYNC_IRQ_ENA_MASK */
+	while (! (TV_FRAMEDONE_ENA_MASK & readl(fbi->reg_base + SPU_IRQ_ISR)));
+#ifdef CONFIG_HDMI
+	hdmi_3d_sync_view();
+#endif
+}
+
+u32 lcd_read(u32 addr)
+{
+	return readl(pxa168_fbi[0]->reg_base + addr);
+}
+
+void lcd_write(u32 addr, u32 v)
+{
+	writel(v, pxa168_fbi[0]->reg_base + addr);
+}
+
+#ifdef CONFIG_HDMI
+void *pxa168fb_hdmi_set_mode(u32 cea_id, u32 enable_3d)
+{
+	struct pxa168fb_info *fbi = pxa168_fbi[1];
+	struct pxa168fb_mach_info *mi = fbi->mi;
+	u32 dma0;
+
+	mi->modes = &cea_modes[cea_id];
+	/*
+	 * init video mode data
+	 */
+	pxa168fb_init_mode(fbi, mi);
+
+	/*
+	 * Fill in sane defaults
+	 */
+	pxa168fb_set_default(fbi, mi);	/* FIXME */
+	pxa168fb_set_par(fbi, mi);
+
+	dma0 = dma_ctrl_read(fbi, 0);
+	/* toggle */
+	if (enable_3d)
+		dma0 |= 1 << 7;
+	else
+		dma0 &= ~(1 << 7);
+	dma_ctrl_write(fbi, 0, dma0);
+
+	hdmi_init(fbi->var, cea_id, enable_3d);
+
+	/* dump all lcd and dsi registers for debug purpose */
+#if defined(DEBUG_PXA168FB)
+	printf("lcd regs:\n");
+	for (i = 0; i < 0x300; i += 4) {
+		if (!(i % 16) && i)
+			printf("\n0x%3x: ", i);
+		printf(" %8x", readl(fbi->reg_base + i));
+	}
+	printf("\n dsi regs:");
+	for (i = 0x0; i < 0x200; i += 4) {
+		if (!(i % 16))
+			printf("\n0x%3x: ", i);
+		printf(" %8x", readl(di->regs + i));
+	}
+	printf("\n");
+	//test_panel(mi->modes->xres, mi->modes->yres);
+#endif
+
+}
+#endif
diff --git a/drivers/video/pxa168fb.h b/drivers/video/pxa168fb.h
new file mode 100644
index 0000000000..73fc06d388
--- /dev/null
+++ b/drivers/video/pxa168fb.h
@@ -0,0 +1,106 @@
+/*
+ * linux/include/video/dovefbreg.h -- Marvell frame buffer for DOVE
+ *
+ *
+ * Copyright (C) Marvell Semiconductor Company.  All rights reserved.
+ *
+ * Written by Green Wan <gwan@marvell.com>
+ *
+ * Adapted from:  linux/drivers/video/skeletonfb.c
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive for
+ * more details.
+ *
+ */
+#ifndef _PXA168FB_H_
+#define _PXA168FB_H_
+
+#define DISPLAY_CONTROLLER_BASE			0xD420B000
+#define LCD_TOP_CTRL				0x01DC
+#define VDMA_ENABLE				0xfff0
+
+#define DSI1_REG_BASE				0xD420B800
+
+/* DMA Control 0 Register */
+#define LCD_SPU_DMA_CTRL0			0x0190
+#define     CFG_ARBFAST_ENA(an)			((an)<<27)
+/* for graphic part */
+#define     CFG_GRA_HSMOOTH(smooth)		((smooth)<<14)
+
+/* for video part */
+#define     CFG_DMA_HSMOOTH(smooth)		((smooth)<<6)
+
+/* DMA Control 1 Register */
+#define LCD_SPU_DMA_CTRL1			0x0194
+
+#define  CFG_ALPHA_MODE(amode)                  ((amode)<<16)
+#define  CFG_ALPHA_MODE_MASK                    0x00030000
+#define  CFG_ALPHA(alpha)                       ((alpha)<<8)
+#define  CFG_ALPHA_MASK                         0x0000FF00
+
+/* Smart or Dumb Panel Clock Divider */
+#define LCD_CFG_SCLK_DIV			0x01A8
+/* Dump LCD Panel Control Register */
+#define LCD_SPU_DUMB_CTRL			0x01B8
+/* LCD I/O Pads Control Register */
+#define SPU_IOPAD_CONTROL			0x01BC
+/* csc */
+#define     CFG_CYC_BURST_LEN16			(1<<4)
+#define     CFG_CYC_BURST_LEN8			(0<<4)
+
+#define SPU_IRQ_ISR                     	0x01C4
+
+/* LCD Interrupt Control Register */
+#define     GRA_FRAME_IRQ0_ENA_MASK		0x08000000
+
+
+
+
+#define     GRA_FRAME_IRQ1_ENA_MASK		0x04000000
+
+
+#define     VSYNC_IRQ_ENA_MASK			0x00800000
+
+
+
+#define     DUMB_FRAMEDONE_ENA_MASK		0x00400000
+
+#define	    TVSYNC_IRQ_ENA_MASK			0x00001000
+
+
+#define     TV_FRAME_IRQ0_ENA_MASK		0x00000800
+#define     TV_FRAME_IRQ1_ENA_MASK              0x00000400
+#define     TV_FRAMEDONE_ENA_MASK		0x00000100
+
+#define  TV_DMA_FRAME_IRQ0_ENA_MASK             0x00008000
+#define  TV_DMA_FRAME_IRQ1_ENA_MASK             0x00004000
+
+/* FIXME - JUST GUESS */
+#define	    PN2_DMA_FRAME_IRQ0_ENA_MASK		0x00000080
+#define	    PN2_DMA_FRAME_IRQ1_ENA_MASK		0x00000040
+#define     PN2_GRA_FRAME_IRQ0_ENA_MASK		0x00000008
+#define     PN2_GRA_FRAME_IRQ1_ENA_MASK		0x04000004
+#define     PN2_SYNC_IRQ_ENA_MASK               0x00000001
+
+#define gf0_imask(id)	((id) ? (((id) & 1) ? TV_FRAME_IRQ0_ENA_MASK \
+		: PN2_GRA_FRAME_IRQ0_ENA_MASK) : GRA_FRAME_IRQ0_ENA_MASK)
+#define gf1_imask(id)	((id) ? (((id) & 1) ? TV_FRAME_IRQ1_ENA_MASK \
+		: PN2_GRA_FRAME_IRQ1_ENA_MASK) : GRA_FRAME_IRQ1_ENA_MASK)
+#define vsync_imask(id)	((id) ? (((id) & 1) ? TVSYNC_IRQ_ENA_MASK \
+		: PN2_SYNC_IRQ_ENA_MASK) : VSYNC_IRQ_ENA_MASK)
+
+#define display_done_imask(id)	((id) ? (((id) & 1) ? TV_FRAMEDONE_ENA_MASK\
+	: (PN2_DMA_FRAME_IRQ0_ENA_MASK | PN2_DMA_FRAME_IRQ1_ENA_MASK))\
+	: DUMB_FRAMEDONE_ENA_MASK)
+#define LCD_PN2_CTRL0                           (0x02C8)
+#define LCD_DUMB2_CTRL                          (0x02d8)
+#define LCD_PN2_CTRL1                           (0x02DC)
+#define LCD_PN2_SCLK_DIV                        (0x01EC)
+
+#define LCD_TCLK_DIV		(0x009C)
+#define clk_div(id)     ((id) ? ((id) & 1 ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV) \
+		: LCD_CFG_SCLK_DIV)
+
+#endif
+
diff --git a/drivers/video/tc35876x.h b/drivers/video/tc35876x.h
new file mode 100644
index 0000000000..79490a376d
--- /dev/null
+++ b/drivers/video/tc35876x.h
@@ -0,0 +1,43 @@
+/*
+ *
+ * Copyright (C) 2006, Marvell Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __MACH_TC35876x_H
+#define __MACH_TC35876x_H
+
+/* DSI PPI Layer Registers */
+#define PPI_STARTPPI				0x0104
+#define PPI_LPTXTIMECNT				0x0114
+#define PPI_LANEENABLE				0x0134
+#define PPI_TX_RX_TA		                0x013c
+#define PPI_D0S_CLRSIPOCOUNT	                0x0164
+#define PPI_D1S_CLRSIPOCOUNT	                0x0168
+#define PPI_D2S_CLRSIPOCOUNT	                0x016c
+#define PPI_D3S_CLRSIPOCOUNT	                0x0170
+/* DSI Protocol Layer Register */
+#define DSI_STARTDSI		                0x0204
+#define DSI_LANEENABLE				0x0210
+/* Video Path Register */
+#define VPCTRL					0x0450
+#define HTIM1					0x0454
+#define HTIM2					0x0458
+#define VTIM1					0x045C
+#define VTIM2					0x0460
+#define VFUEN					0x0464
+/* LVDS Registers */
+#define LVCFG					0x049c
+/* DSI Protocol Layer Regsters */
+#define DSI_LANESTATUS0				0x0214
+#define DSI_INTSTAUS			        0x0220
+#define DSI_INTCLR				0x0228
+/* DSI General Registers */
+#define DSIERRCNT				0x0300
+/* System Registers */
+#define SYSSTAT					0x0500
+
+#endif
diff --git a/include/common.h b/include/common.h
index d244bd40b5..4e79a67268 100644
--- a/include/common.h
+++ b/include/common.h
@@ -789,6 +789,72 @@ int cpu_release(int nr, int argc, char * const argv[]);
 #define ALIGN(x,a)		__ALIGN_MASK((x),(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)	(((x)+(mask))&~(mask))
 
+/*
+ * The ALLOC_CACHE_ALIGN_BUFFER macro is used to allocate a buffer on the
+ * stack that meets the minimum architecture alignment requirements for DMA.
+ * Such a buffer is useful for DMA operations where flushing and invalidating
+ * the cache before and after a read and/or write operation is required for
+ * correct operations.
+ *
+ * When called the macro creates an array on the stack that is sized such
+ * that:
+ *
+ * 1) The beginning of the array can be advanced enough to be aligned.
+ *
+ * 2) The size of the aligned portion of the array is a multiple of the minimum
+ *    architecture alignment required for DMA.
+ *
+ * 3) The aligned portion contains enough space for the original number of
+ *    elements requested.
+ *
+ * The macro then creates a pointer to the aligned portion of this array and
+ * assigns to the pointer the address of the first element in the aligned
+ * portion of the array.
+ *
+ * Calling the macro as:
+ *
+ *     ALLOC_CACHE_ALIGN_BUFFER(uint32_t, buffer, 1024);
+ *
+ * Will result in something similar to saying:
+ *
+ *     uint32_t    buffer[1024];
+ *
+ * The following differences exist:
+ *
+ * 1) The resulting buffer is guaranteed to be aligned to the value of
+ *    ARCH_DMA_MINALIGN.
+ *
+ * 2) The buffer variable created by the macro is a pointer to the specified
+ *    type, and NOT an array of the specified type.  This can be very important
+ *    if you want the address of the buffer, which you probably do, to pass it
+ *    to the DMA hardware.  The value of &buffer is different in the two cases.
+ *    In the macro case it will be the address of the pointer, not the address
+ *    of the space reserved for the buffer.  However, in the second case it
+ *    would be the address of the buffer.  So if you are replacing hard coded
+ *    stack buffers with this macro you need to make sure you remove the & from
+ *    the locations where you are taking the address of the buffer.
+ *
+ * Note that the size parameter is the number of array elements to allocate,
+ * not the number of bytes.
+ *
+ * This macro can not be used outside of function scope, or for the creation
+ * of a function scoped static buffer.  It can not be used to create a cache
+ * line aligned global buffer.
+ */
+#define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)			\
+	char __##name[ROUND(size * sizeof(type), ARCH_DMA_MINALIGN) +	\
+		      ARCH_DMA_MINALIGN - 1];				\
+									\
+	type *name = (type *) ALIGN((uintptr_t)__##name, ARCH_DMA_MINALIGN)
+
+/*
+ * ARCH_DMA_MINALIGN is defined in asm/cache.h for each architecture.  It
+ * is used to align DMA buffers.
+ */
+#ifndef __ASSEMBLY__
+#include <asm/cache.h>
+#endif
+
 /* Pull in stuff for the build system */
 #ifdef DO_DEPS_ONLY
 # include <environment.h>
diff --git a/include/configs/abilene.h b/include/configs/abilene.h
new file mode 100644
index 0000000000..14191aa770
--- /dev/null
+++ b/include/configs/abilene.h
@@ -0,0 +1,101 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_ABILENE_H
+#define __CONFIG_ABILENE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-AbileneEX"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7			1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX		1	/* SOC Family Name */
+#define CONFIG_MACH_ABILENE		1	/* Machine type */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1020000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	8
+#define CONFIG_DISPLAY_BOARDINFO
+
+#define CONFIG_PXA168_FB
+//#define CONFIG_HDMI
+//#define CONFIG_MMP_HDMI
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_GPIO
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_UNSPARSE
+#ifdef CONFIG_TZ_HYPERVISOR
+#define CONFIG_SYS_TEXT_BASE		0x00200000
+#define CONFIG_SYS_SDRAM_BASE		0x00200000
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x00200000
+#else
+#define CONFIG_SYS_TEXT_BASE		0
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_TZ_HYPERVISOR_SIZE	0
+#endif
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MIPS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"mmc dev 0; mmc read $loadaddr" \
+					" 0x4c00 0x2000; bootm $loadaddr"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_ABILENE_H */
diff --git a/include/configs/dkb.h b/include/configs/dkb.h
index 3d27c5857e..08777a80c5 100644
--- a/include/configs/dkb.h
+++ b/include/configs/dkb.h
@@ -47,6 +47,9 @@
 #define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
 #include <config_cmd_default.h>
 #define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
 #undef CONFIG_CMD_NET
 #undef CONFIG_CMD_NFS
 /*
diff --git a/include/configs/mk2.h b/include/configs/mk2.h
new file mode 100644
index 0000000000..75b42a8281
--- /dev/null
+++ b/include/configs/mk2.h
@@ -0,0 +1,155 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_MK2_H
+#define __CONFIG_MK2_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING		"\nMarvell-MK2"
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7				1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX			1	/* SOC Family Name */
+#define CONFIG_MACH_MK2				1	/* Machine type */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1020000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	8
+
+//#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_PXA168_FB
+
+
+#define CONFIG_PXA168_FB
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_MMC
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_UNSPARSE
+#ifdef CONFIG_TZ_HYPERVISOR
+#define CONFIG_SYS_TEXT_BASE		0x00200000
+#define CONFIG_SYS_SDRAM_BASE		0x00200000
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x00200000
+#else
+#define CONFIG_SYS_TEXT_BASE		0x100000
+#define CONFIG_SYS_SDRAM_BASE		0x0
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x0
+#endif
+#define CONFIG_SYS_BOOTPARAMS_LEN (128 * 1024)
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MIPS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY		0
+
+
+#define CONFIG_BOOTCOMMAND		"mmc dev 1; runscript; " \
+					"mmc dev 0 0; " \
+					"mmc read 0x7fc0 0x4c00 0x3000; " \
+					"mmc read 0x2100000 0x8c00 0x200; " \
+					"bootm 0x7fc0 0x2100000\0"
+
+#define CONFIG_BOOTARGS			"initrd=0x2100000,1m root=/dev/ram rw init=/init "	\
+					"androidboot.console=ttyS2 " \
+					"console=ttyS2,115200 emmc_boot"
+					
+#define CONFIG_MV_RECOVERY
+
+#ifdef CONFIG_LOADADDR
+#undef CONFIG_LOADADDR
+#endif
+
+#define CONFIG_TRUST_BOOT
+
+#define CONFIG_LOADADDR		0x1017fc0
+#ifdef CONFIG_MV_RECOVERY
+#define __stringify_1(x...)		#x
+#define __stringify(x...)		__stringify_1(x)
+#define CONFIG_TRUST_BOOT_MAGIC		0x54525354
+#define CONFIG_RESIDUE_CMD		"bootm $loadaddr"
+#define CONFIG_GO_RUBOOT_CMD	"mmc dev 0 2; mmc read " \
+	__stringify(CONFIG_SYS_TEXT_BASE)		\
+	" 0x400 0x400; go " __stringify(CONFIG_SYS_TEXT_BASE)
+//#define CONFIG_GO_RKERNEL_CMD	"mmc dev 0 0; mmc read $loadaddr " \
+//	"0xcc00 0x3000; bootm $loadaddr"
+
+//Support for recovery kernel command
+#define CONFIG_GO_RKERNEL_CMD		"mmc dev 1; runscript; " \
+					"mmc dev 0 0; mmc read 0x7fc0 " \
+					"0xcc00 0x3000; mmc read 0x2100000 0x10c00 0x1000; bootm 0x7fc0 0x2100000"
+
+
+
+#endif
+
+//#define CONFIG_BOOTARGS			"rdinit=/busybox/rdinit "	\
+//					"androidboot.console=ttyS2 " \
+//					"console=ttyS2,115200 emmc_boot fb_share"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define CONFIG_MV_WTM
+#define CONFIG_MARVELL_TAG
+
+// Wistron
+#define CONFIG_CMD_SETEXPR	1
+//#define CONFIG_CMD_RUNSCRIPT	1
+//#define SCRIPT_FILE_NAME	"tlite2.txt" 
+#define CONFIG_FB_RESV		512
+
+#define BOARD_LATE_INIT 1 
+
+#endif	/* __CONFIG_MK2_H */
diff --git a/include/configs/mmp2_brownstone.h b/include/configs/mmp2_brownstone.h
new file mode 100644
index 0000000000..7220c26bfe
--- /dev/null
+++ b/include/configs/mmp2_brownstone.h
@@ -0,0 +1,117 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell version: 1.1.1.1 MMP2"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7			1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX		1	/* SOC Family Name */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1000000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	4
+#define CONFIG_MACH_BROWNSTONE			/* Used to read DRAM size */
+#define CONFIG_MACH_MMP2
+
+#define CONFIG_MMP_POWER
+#define CONFIG_DDR3_EPD_1G
+
+#define CONFIG_PXA168_FB
+
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_GPIO
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_UNSPARSE
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_SYS_TEXT_BASE		0x100000
+#define CONFIG_NR_DRAM_BANKS		2
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MIPS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+#define CONFIG_MV_WTM
+#define CONFIG_DISPLAY_BOARDINFO
+#define CONFIG_BROWNSTONE_VOLT
+
+#define CONFIG_POWEROFF_CHARGE
+#define CONFIG_MAX17042_BATTERY
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTCOMMAND             "mmc dev 0 0; mmc read $(loadaddr) 0x4c00 0x2000; bootm $(loadaddr)"
+
+#define CONFIG_MV_RECOVERY
+#ifdef CONFIG_MV_RECOVERY
+#define __stringify_1(x...)		#x
+#define __stringify(x...)		__stringify_1(x)
+#define CONFIG_TRUST_BOOT_MAGIC		0x54525354
+#define CONFIG_RESIDUE_CMD		"bootm $(loadaddr)"
+#define CONFIG_GO_RUBOOT_CMD		"mmc dev 0 1; mmc read "__stringify(CONFIG_SYS_TEXT_BASE) \
+					" 0x580 0x280; go " __stringify(CONFIG_SYS_TEXT_BASE)
+#define CONFIG_GO_RKERNEL_CMD		"mmc dev 0 0; mmc read $(loadaddr)" \
+					" 0xcc00 0x2000; bootm $(loadaddr)"
+#endif	/* CONFIG_MV_RECOVERY */
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_IN_MMC	1	/* if env in MMC */
+#define CONFIG_ENV_SIZE	0x20000	/* 128k */
+#define CONFIG_CMD_SAVEENV
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_OFFSET 0x900000
+
+#endif	/* __CONFIG_ABILENE_H */
diff --git a/include/configs/mmp2_g50.h b/include/configs/mmp2_g50.h
new file mode 100644
index 0000000000..431b9d2d68
--- /dev/null
+++ b/include/configs/mmp2_g50.h
@@ -0,0 +1,84 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell version: 1.1.1.1 MMP2"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7			1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX		1	/* SOC Family Name */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1000000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	4
+#define CONFIG_MACH_BROWNSTONE
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_MMC
+#define CONFIG_CMD_GPIO
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_UNSPARSE
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_SYS_TEXT_BASE		0x100000
+#define CONFIG_NR_DRAM_BANKS		2
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+#define CONFIG_SKIP_LOWLEVEL_INIT
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY               3
+#define CONFIG_BOOTCOMMAND             "mmc dev 1; mmc read $(loadaddr) \
+					0x4c00 0x2000; bootm $(loadaddr)"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+
+#endif	/* __CONFIG_ABILENE_H */
diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h
index 3f5fcc69a2..75cbdbd626 100644
--- a/include/configs/mv-common.h
+++ b/include/configs/mv-common.h
@@ -46,7 +46,14 @@
 #endif /* CONFIG_SYS_TEXT_BASE */
 
 /* additions for new ARM relocation support */
+#ifndef CONFIG_SYS_SDRAM_BASE
 #define CONFIG_SYS_SDRAM_BASE	0x00000000
+#endif
+
+/* setting for trustzone hypervisor size */
+#ifndef CONFIG_TZ_HYPERVISOR_SIZE
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x00000000
+#endif
 
 /*
  * CLKs configurations
@@ -74,6 +81,7 @@
 					  115200,230400, 460800, 921600 }
 /* auto boot */
 #define CONFIG_BOOTDELAY	3	/* default enable autoboot */
+#define CONFIG_BOOTFILE		"uImage"        /* file to load */
 
 /*
  * For booting Linux, the board info and command line data
diff --git a/include/configs/orchid.h b/include/configs/orchid.h
new file mode 100644
index 0000000000..d600df9ff7
--- /dev/null
+++ b/include/configs/orchid.h
@@ -0,0 +1,100 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_ORCHID_H
+#define __CONFIG_ORCHID_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING		"\nMarvell-Orchid"
+
+/*
+ * High Level Configuration Options
+ */
+
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7				1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX			1	/* SOC Family Name */
+#define CONFIG_MACH_ORCHID			1	/* Machine type */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1020000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	8
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_CMD_MMC
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_UNSPARSE
+#ifdef CONFIG_TZ_HYPERVISOR
+#define CONFIG_SYS_TEXT_BASE		0x00200000
+#define CONFIG_SYS_SDRAM_BASE		0x00200000
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x00200000
+#else
+#define CONFIG_SYS_TEXT_BASE		0
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_TZ_HYPERVISOR_SIZE	0
+#endif
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MIPS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"mmc dev 0; mmc read $loadaddr" \
+					" 0x4c00 0x2000; bootm $loadaddr"
+#define CONFIG_BOOTARGS			"rdinit=/busybox/rdinit " \
+					"androidboot.console=ttyS2 " \
+					"console=ttyS2,115200 emmc_boot fb_share"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_ORCHID_H */
diff --git a/include/configs/yellowstone.h b/include/configs/yellowstone.h
new file mode 100644
index 0000000000..e2bb2f8519
--- /dev/null
+++ b/include/configs/yellowstone.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2011
+ * Marvell Semiconductor <www.marvell.com>
+ * Written-by: Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __CONFIG_YELLOWSTONE_H
+#define __CONFIG_YELLOWSTONE_H
+
+/*
+ * Version number information
+ */
+#define CONFIG_IDENT_STRING	"\nMarvell-Yellowstone"
+
+/*
+ * High Level Configuration Options
+ */
+#define CONFIG_SHEEVA_88SV584xV7	1	/* CPU Core subversion */
+#define CONFIG_ARMV7			1	/* ARM926EJS cpu family */
+#define CONFIG_ARMADA6XX		1	/* SOC Family Name */
+#define CONFIG_MACH_YELLOWSTONE		1	/* Machine type */
+
+#define CONFIG_SYS_INIT_SP_ADDR		(0xd1020000 + 0x1000)
+#define CONFIG_NR_DRAM_BANKS_MAX	8
+
+/*
+ * Commands configuration
+ */
+#define CONFIG_SYS_NO_FLASH		/* Declare no flash (NOR/SPI) */
+#include <config_cmd_default.h>
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_GPIO
+#define CONFIG_CMD_MMC
+#define CONFIG_USB_ETHER
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_MISC_INIT_R
+#define CONFIG_CMD_AUTOSCRIPT
+#define CONFIG_CMD_UNSPARSE
+#ifdef CONFIG_TZ_HYPERVISOR
+#define CONFIG_SYS_TEXT_BASE		0x00200000
+#define CONFIG_SYS_SDRAM_BASE		0x00200000
+#define CONFIG_TZ_HYPERVISOR_SIZE	0x00200000
+#else
+#define CONFIG_SYS_TEXT_BASE		0
+#define CONFIG_SYS_SDRAM_BASE		0
+#define CONFIG_TZ_HYPERVISOR_SIZE	0
+#endif
+#undef CONFIG_CMD_NET
+#undef CONFIG_CMD_NFS
+
+#define CONFIG_CMD_MIPS
+
+/*
+ * mv-common.h should be defined after CMD configs since it used them
+ * to enable certain macros
+ */
+#include "mv-common.h"
+
+#undef CONFIG_ARCH_MISC_INIT
+#define CONFIG_L2_OFF
+
+/*
+ * Boot setting
+ */
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+#define CONFIG_SHOW_BOOT_PROGRESS
+#define CONFIG_BOOTDELAY		3
+#define CONFIG_BOOTCOMMAND		"mmc dev 0; mmc read $loadaddr" \
+					" 0x4c00 0x2000; bootm $loadaddr"
+#define CONFIG_BOOTARGS			"rdinit=/busybox/rdinit androidboot.console=ttyS2" \
+					" console=ttyS2,115200 emmc_boot fb_share"
+
+/*
+ * Environment variables configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE	1	/* if env in SDRAM */
+#define CONFIG_ENV_SIZE	0x20000	/* 64k */
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+
+#endif	/* __CONFIG_YELLOWSTONE_H */
diff --git a/include/fastboot.h b/include/fastboot.h
new file mode 100644
index 0000000000..064453b96e
--- /dev/null
+++ b/include/fastboot.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Back ported to the 8xx platform (from the 8260 platform) by
+ * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
+ */
+#ifndef __FASTBOOT_H_
+#define __FASTBOOT_H_	1
+
+void rcv_cmd(void);
+void fb_set_buf(void *buf);
+void fb_tx_status(const char *status);
+void fb_tx_data(void *data, unsigned long len);
+int fb_get_rcv_len(void);
+void *fb_get_buf(void);
+void fb_init(void);
+void fb_run(void);
+void fb_halt(void);
+
+
+#endif	/* __FASTBOOT_H_ */
diff --git a/include/hdmi.h b/include/hdmi.h
new file mode 100644
index 0000000000..1931aaaf83
--- /dev/null
+++ b/include/hdmi.h
@@ -0,0 +1,25 @@
+#ifndef _LINUX_HDMI_H
+#include <linux/list.h>
+#include <linux/fb.h>
+
+extern const struct fb_videomode cea_modes[65];
+
+typedef u32 cea_mode_id;
+
+struct hdmi_dev {
+	struct fb_info          *fb_info;
+	cea_mode_id		mode_id;
+	u32                     enable;
+	u32                     mode_3d;
+	u32                     pixel_rept;
+	u32                     ratio;
+};
+
+
+
+void hdmi_init(struct fb_var_screeninfo *var, u32 id, u32 enable_3d);
+int hdmi_vender_info_frame (struct hdmi_dev *hd, char buf[]);
+int hdmi_avi_info_frame (struct hdmi_dev *hd, char buf[]);
+int hdmi_get_freq (struct hdmi_dev *hd, u32 *need_freq);
+void *pxa168fb_hdmi_set_mode(u32 cea_id, u32 enable_3d);
+#endif
diff --git a/include/linux/fb.h b/include/linux/fb.h
index 3858f8f80f..b39752cdc9 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -581,6 +581,7 @@ struct fb_info {
 #define FB_MODE_IS_CALCULATED	8
 #define FB_MODE_IS_FIRST	16
 #define FB_MODE_IS_FROM_VAR	32
+#define FB_MODE_IS_CEA		64
 
 
 /* drivers/video/fbcmap.c */
diff --git a/include/mmp_freq.h b/include/mmp_freq.h
new file mode 100644
index 0000000000..3a00041552
--- /dev/null
+++ b/include/mmp_freq.h
@@ -0,0 +1,7 @@
+#ifndef _MMP_FREQ_
+#define _MMP_FREQ_
+
+int setop(int num);
+int set_volt(u32 vol);
+
+#endif /* _MMP_FREQ_ */
diff --git a/include/mv_recovery.h b/include/mv_recovery.h
new file mode 100644
index 0000000000..dfbe78f7c8
--- /dev/null
+++ b/include/mv_recovery.h
@@ -0,0 +1,24 @@
+/*
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MV_RECOVERY_H__
+#define __MV_RECOVERY_H__
+
+inline void magic_read(void);
+void mv_recovery(void);
+
+int magic_key_detect_recovery(void);
+#endif /* __MV_RECOVERY_H__ */
+
diff --git a/include/mv_wtm.h b/include/mv_wtm.h
new file mode 100644
index 0000000000..e014f5276d
--- /dev/null
+++ b/include/mv_wtm.h
@@ -0,0 +1,22 @@
+/*
+ * (C) Copyright 2012
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __MV_WTM_H__
+#define __MV_WTM_H__
+
+int  wtm_read_profile(void);
+void wtm_read_stepping(void);
+void wtm_dump_info(void);
+
+#endif
diff --git a/include/mvgpio.h b/include/mvgpio.h
new file mode 100644
index 0000000000..03f0df06cc
--- /dev/null
+++ b/include/mvgpio.h
@@ -0,0 +1,74 @@
+/*
+ * (C) Copyright 2011
+ * eInfochips Ltd. <www.einfochips.com>
+ * Written-by: Ajay Bhargav <ajay.bhargav@einfochips.com>
+ *
+ * (C) Copyright 2010
+ * Marvell Semiconductor <www.marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#ifndef __MVGPIO_H__
+#define __MVGPIO_H__
+
+#include <common.h>
+
+#if defined(CONFIG_SHEEVA_88SV331xV5) || defined(CONFIG_SHEEVA_88SV584xV7)
+/*
+ * GPIO Register map for SHEEVA 88SV331xV5
+ */
+struct gpio_reg {
+	u32 gplr;	/* Pin Level Register - 0x0000 */
+	u32 pad0[2];
+	u32 gpdr;	/* Pin Direction Register - 0x000C */
+	u32 pad1[2];
+	u32 gpsr;	/* Pin Output Set Register - 0x0018 */
+	u32 pad2[2];
+	u32 gpcr;	/* Pin Output Clear Register - 0x0024 */
+	u32 pad3[2];
+	u32 grer;	/* Rising-Edge Detect Enable Register - 0x0030 */
+	u32 pad4[2];
+	u32 gfer;	/* Falling-Edge Detect Enable Register - 0x003C */
+	u32 pad5[2];
+	u32 gedr;	/* Edge Detect Status Register - 0x0048 */
+	u32 pad6[2];
+	u32 gsdr;	/* Bitwise Set of GPIO Direction Register - 0x0054 */
+	u32 pad7[2];
+	u32 gcdr;	/* Bitwise Clear of GPIO Direction Register - 0x0060 */
+	u32 pad8[2];
+	u32 gsrer;	/* Bitwise Set of Rising-Edge Detect Enable
+			   Register - 0x006C */
+	u32 pad9[2];
+	u32 gcrer;	/* Bitwise Clear of Rising-Edge Detect Enable
+			   Register - 0x0078 */
+	u32 pad10[2];
+	u32 gsfer;	/* Bitwise Set of Falling-Edge Detect Enable
+			   Register - 0x0084 */
+	u32 pad11[2];
+	u32 gcfer;	/* Bitwise Clear of Falling-Edge Detect Enable
+			   Register - 0x0090 */
+	u32 pad12[2];
+	u32 apmask;	/* Bitwise Mask of Edge Detect Register - 0x009C */
+};
+#else
+#error "CPU core subversion not defined"
+#endif
+
+#endif /* __MVGPIO_H__ */
diff --git a/include/mvmfp.h b/include/mvmfp.h
index 0b36393f90..55fb34b34a 100644
--- a/include/mvmfp.h
+++ b/include/mvmfp.h
@@ -37,6 +37,7 @@
 /*
  * MFP configuration is represented by a 32-bit unsigned integer
  */
+#ifdef CONFIG_ARMADA100
 #define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
 	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
 	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
@@ -48,6 +49,19 @@
 	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
 	/* bits 03..00 - Alt-fun flag */	(((_aF) & 0x1) << 3) | \
 	/* bits Alternate-fun select */		((_afn) & 0x7))
+#else
+#define MFP(_off, _pull, _pF, _drv, _dF, _edge, _eF, _afn, _aF) ( \
+	/* bits 31..16 - MFP Register Offset */	(((_off) & 0xffff) << 16) | \
+	/* bits 15..13 - Run Mode Pull State */	(((_pull) & 0x7) << 13) | \
+	/* bit  12..11 - Driver Strength */	(((_drv) & 0x3) << 11) | \
+	/* bits 10     - Unused */ \
+	/* bit  09     - Pull State flag */	(((_pF) & 0x1) << 9) | \
+	/* bit  08     - Drv-strength flag */	(((_dF) & 0x1) << 8) | \
+	/* bit  07     - Edge-det flag */	(((_eF) & 0x1) << 7) | \
+	/* bits 06..04 - Edge Detection */	(((_edge) & 0x7) << 4) | \
+	/* bits 03..00 - Alt-fun flag */	(((_aF) & 0x1) << 3) | \
+	/* bits Alternate-fun select */		((_afn) & 0x7))
+#endif
 
 /*
  * to facilitate the definition, the following macros are provided
@@ -86,9 +100,9 @@
 #define MFP_DRIVE_MASK		MFP(0x0000,    0,0,    3,0,     0,0,   0,0)
 
 #define MFP_PULL_NONE		MFP(0x0000,    0,1,    0,0,     0,0,   0,0)
-#define MFP_PULL_LOW		MFP(0x0000,    1,1,    0,0,     0,0,   0,0)
-#define MFP_PULL_HIGH		MFP(0x0000,    2,1,    0,0,     0,0,   0,0)
-#define MFP_PULL_BOTH		MFP(0x0000,    3,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_LOW		MFP(0x0000,    5,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_HIGH		MFP(0x0000,    6,1,    0,0,     0,0,   0,0)
+#define MFP_PULL_BOTH		MFP(0x0000,    7,1,    0,0,     0,0,   0,0)
 #define MFP_PULL_FLOAT		MFP(0x0000,    4,1,    0,0,     0,0,   0,0)
 #define MFP_PULL_MASK		MFP(0x0000,    7,0,    0,0,     0,0,   0,0)
 
diff --git a/include/netdev.h b/include/netdev.h
index 96c7b9b5f2..5c5941cabc 100644
--- a/include/netdev.h
+++ b/include/netdev.h
@@ -94,6 +94,7 @@ int smc911x_initialize(u8 dev_num, int base_addr);
 int tsi108_eth_initialize(bd_t *bis);
 int uec_standard_init(bd_t *bis);
 int uli526x_initialize(bd_t *bis);
+int armada100_fec_register(unsigned long base_addr);
 int xilinx_emaclite_initialize (bd_t *bis, int base_addr);
 
 /* Boards with PCI network controllers can call this from their board_eth_init()
diff --git a/include/ns16550.h b/include/ns16550.h
index 9ea81e9463..51f1c17b31 100644
--- a/include/ns16550.h
+++ b/include/ns16550.h
@@ -21,8 +21,12 @@
  * will not allocate storage for arrays of size 0
  */
 
+#include <linux/types.h>
+
 #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
 #error "Please define NS16550 registers size."
+#elif defined(CONFIG_SYS_NS16550_MEM32)
+#define UART_REG(x) u32 x
 #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
 #define UART_REG(x)						   \
 	unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
diff --git a/include/part.h b/include/part.h
index 182776791d..dac2bddd77 100644
--- a/include/part.h
+++ b/include/part.h
@@ -41,6 +41,7 @@ typedef struct block_dev_desc {
 	char		vendor [40+1];	/* IDE model, SCSI Vendor */
 	char		product[20+1];	/* IDE Serial no, SCSI product */
 	char		revision[8+1];	/* firmware revision */
+	int		(*dev_init)(int dev);
 	unsigned long	(*block_read)(int dev,
 				      unsigned long start,
 				      lbaint_t blkcnt,
@@ -108,6 +109,7 @@ block_dev_desc_t* mg_disk_get_dev(int dev);
 
 /* disk/part.c */
 int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+int get_partition_num (block_dev_desc_t *dev_desc);
 void print_part (block_dev_desc_t *dev_desc);
 void  init_part (block_dev_desc_t *dev_desc);
 void dev_print(block_dev_desc_t *dev_desc);
@@ -138,6 +140,7 @@ int   test_part_mac (block_dev_desc_t *dev_desc);
 #ifdef CONFIG_DOS_PARTITION
 /* disk/part_dos.c */
 int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+int get_partition_num_dos(block_dev_desc_t * dev_desc);
 void print_part_dos (block_dev_desc_t *dev_desc);
 int   test_part_dos (block_dev_desc_t *dev_desc);
 #endif
@@ -159,6 +162,7 @@ int   test_part_amiga (block_dev_desc_t *dev_desc);
 #ifdef CONFIG_EFI_PARTITION
 /* disk/part_efi.c */
 int get_partition_info_efi (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+int get_partition_num_efi(block_dev_desc_t * dev_desc);
 void print_part_efi (block_dev_desc_t *dev_desc);
 int   test_part_efi (block_dev_desc_t *dev_desc);
 #endif
diff --git a/include/pxa168fb.h b/include/pxa168fb.h
new file mode 100644
index 0000000000..61957dc9db
--- /dev/null
+++ b/include/pxa168fb.h
@@ -0,0 +1,581 @@
+/*
+ * linux/arch/arm/mach-mmp/include/mach/pxa168fb.h
+ *
+ *  Copyright (C) 2009 Marvell International Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __ASM_MACH_PXA168FB_H
+#define __ASM_MACH_PXA168FB_H
+
+#include <linux/types.h>
+#include <linux/list.h>
+#include <linux/fb.h>
+
+/*
+ * panel interface
+ */
+#define DPI             0
+#define DSI2DPI         1
+#define DSI             2
+#define LVDS            4
+
+#define fb_base         0
+#define fb_dual         1
+#define FB_MODE_DUP     ((fbi->id == fb_base) && fb_mode && \
+		gfx_info.fbi[fb_dual])
+
+/* DSI burst mode */
+#define DSI_BURST_MODE_SYNC_PULSE                       0x0
+#define DSI_BURST_MODE_SYNC_EVENT                       0x1
+#define DSI_BURST_MODE_BURST                            0x2
+
+/* ------------< LCD register >------------ */
+struct lcd_regs {
+	/* Video Frame 0/1 Y/U/V/Command Starting Addr */
+	u32 v_y0;
+	u32 v_u0;
+	u32 v_v0;
+	u32 v_c0;
+	u32 v_y1;
+	u32 v_u1;
+	u32 v_v1;
+	u32 v_c1;
+	/* Video Y and C Line Length (Pitch) */
+	u32 v_pitch_yc;
+	/* Video U and V Line Length (Pitch) */
+	u32 v_pitch_uv;
+	/* Video Starting Point on Screen */
+	u32 v_start;
+	/* Video Source Size */
+	u32 v_size;
+	/* Video Destination Size (After Zooming) */
+	u32 v_size_z;
+	/* Graphic Frame 0/1 Starting Address */
+	u32 g_0;
+	u32 g_1;
+	/* Graphic Line Length (Pitch) */
+	u32 g_pitch;
+	/* Graphic Starting Point on Screen */
+	u32 g_start;
+	/* Graphic Source Size */
+	u32 g_size;
+	/* Graphic Destination Size (After Zooming) */
+	u32 g_size_z;
+	/* Hardware Cursor */
+	u32 hc_start;
+	/* Hardware Cursor */
+	u32 hc_size;
+	/* Screen Total Size */
+	u32 screen_size;
+	/* Screen Active Size */
+	u32 screen_active;
+	/* Screen Horizontal Porch */
+	u32 screen_h_porch;
+	/* Screen Vertical Porch */
+	u32 screen_v_porch;
+	/* Screen Blank Color */
+	u32 blank_color;
+	/* Hardware Cursor Color1 */
+	u32 hc_Alpha_color1;
+	/* Hardware Cursor Color2 */
+	u32 hc_Alpha_color2;
+	/* Video Y Color Key Control */
+	u32 v_colorkey_y;
+	/* Video U Color Key Control */
+	u32 v_colorkey_u;
+	/* Video V Color Key Control */
+	u32 v_colorkey_v;
+	/* VSYNC PulsePixel Edge Control */
+	u32 vsync_ctrl;
+};
+
+#define intf_ctrl(id)		((id) ? (((id) & 1) ? LCD_TVIF_CTRL \
+			: LCD_DUMB2_CTRL) : LCD_SPU_DUMB_CTRL)
+#define dma_ctrl0(id)           ((id) ? (((id) & 1) ? LCD_TV_CTRL0 \
+			: LCD_PN2_CTRL0) : LCD_SPU_DMA_CTRL0)
+#define dma_ctrl1(id)           ((id) ? (((id) & 1) ? LCD_TV_CTRL1 \
+			: LCD_PN2_CTRL1) : LCD_SPU_DMA_CTRL1)
+#define dma_ctrl(ctrl1, id)     (ctrl1 ? dma_ctrl1(id) : dma_ctrl0(id))
+
+/* 32 bit       TV Path DMA Control 0*/
+#define LCD_TV_CTRL0                     (0x0080)
+/* 32 bit       TV Path DMA Control 1*/
+#define LCD_TV_CTRL1                     (0x0084)
+/* 32 bit TV Path TVIF Control  Register */
+#define LCD_TVIF_CTRL                    (0x0094)
+
+/*
+ * Buffer pixel format
+ * bit0 is for rb swap.
+ * bit12 is for Y UorV swap
+ */
+#define PIX_FMT_RGB565		0
+#define PIX_FMT_BGR565		1
+#define PIX_FMT_RGB1555		2
+#define PIX_FMT_BGR1555		3
+#define PIX_FMT_RGB888PACK	4
+#define PIX_FMT_BGR888PACK	5
+#define PIX_FMT_RGB888UNPACK	6
+#define PIX_FMT_BGR888UNPACK	7
+#define PIX_FMT_RGBA888		8
+#define PIX_FMT_BGRA888		9
+#define PIX_FMT_YUV422PACK	10
+#define PIX_FMT_YVU422PACK	11
+#define PIX_FMT_YUV422PLANAR	12
+#define PIX_FMT_YVU422PLANAR	13
+#define PIX_FMT_YUV420PLANAR	14
+#define PIX_FMT_YVU420PLANAR	15
+#define PIX_FMT_PSEUDOCOLOR	20
+#define PIX_FMT_UYVY422PACK	(0x1000|PIX_FMT_YUV422PACK)
+
+struct dsi_phy {
+	unsigned int hs_prep_constant;    /* Unit: ns. */
+	unsigned int hs_prep_ui;
+	unsigned int hs_zero_constant;
+	unsigned int hs_zero_ui;
+	unsigned int hs_trail_constant;
+	unsigned int hs_trail_ui;
+	unsigned int hs_exit_constant;
+	unsigned int hs_exit_ui;
+	unsigned int ck_zero_constant;
+	unsigned int ck_zero_ui;
+	unsigned int ck_trail_constant;
+	unsigned int ck_trail_ui;
+	unsigned int req_ready;
+};
+
+struct dsi_info {
+	unsigned        id;
+	unsigned        regs;
+	unsigned        lanes;
+	unsigned        bpp;
+	unsigned        rgb_mode;
+	unsigned        burst_mode;
+	unsigned        lpm_line_en;
+	unsigned        lpm_frame_en;
+	unsigned        last_line_turn;
+	unsigned        hex_slot_en;
+	unsigned        all_slot_en;
+	unsigned        hbp_en;
+	unsigned        hact_en;
+	unsigned        hfp_en;
+	unsigned        hex_en;
+	unsigned        hlp_en;
+	unsigned        hsa_en;
+	unsigned        hse_en;
+	unsigned        eotp_en;
+	struct dsi_phy  *phy;
+};
+
+/* LVDS info */
+struct lvds_info {
+#define LVDS_SRC_PN	0
+#define LVDS_SRC_CMU	1
+#define LVDS_SRC_PN2	2
+#define LVDS_SRC_TV	3
+	u32	src;
+#define LVDS_FMT_24BIT	0
+#define LVDS_FMT_18BIT	1
+	u32	fmt;
+};
+
+struct cmu_calibration {
+	int left;
+	int right;
+	int top;
+	int bottom;
+};
+
+
+struct pxa168fb_mach_info {
+	char    id[16];
+	unsigned	index;
+	unsigned int    sclk_src;
+	unsigned int    sclk_div;
+
+	int             num_modes;
+	struct fb_videomode *modes;
+	unsigned int max_fb_size;
+
+	/*
+	 * Pix_fmt
+	 */
+	unsigned        pix_fmt;
+
+	/*
+	 * Burst length
+	 */
+	unsigned        burst_len;
+
+	/*
+	 * I/O pin allocation.
+	 */
+	unsigned int    io_pin_allocation_mode;
+
+	/*
+	 * Dumb panel -- assignment of R/G/B component info to the 24
+	 * available external data lanes.
+	 */
+	unsigned        dumb_mode:4;
+	unsigned        panel_rgb_reverse_lanes:1;
+
+	/*
+	 * Dumb panel -- GPIO output data.
+	 */
+	unsigned        gpio_output_mask:8;
+	unsigned        gpio_output_data:8;
+
+	/*
+	 * Dumb panel -- configurable output signal polarity.
+	 */
+	unsigned        invert_composite_blank:1;
+	unsigned        invert_pix_val_ena:1;
+	unsigned        invert_pixclock:1;
+	unsigned        invert_vsync:1;
+	unsigned        invert_hsync:1;
+	unsigned        panel_rbswap:1;
+	unsigned        active:1;
+	unsigned        enable_lcd:1;
+	/*
+	 * SPI control
+	 */
+	unsigned int    spi_ctrl;
+	unsigned int    spi_gpio_cs;
+	unsigned int    spi_gpio_reset;
+
+	/*
+	 * panel interface
+	 */
+	unsigned int    phy_type;
+	unsigned int    twsi_id;
+
+	/*
+	 * vdma option
+	 */
+	unsigned int vdma_enable;
+
+	/* phy interface info */
+	void *phy_info;
+
+	/*CMU platform calibration*/
+	struct cmu_calibration cmu_cal[3];
+	struct cmu_calibration cmu_cal_letter_box[3];
+};
+
+#define MAX_QUEUE_NUM 30
+
+#define DEFAULT_FB_BASE		0x19000000
+#define BMP_DOWNLOAD_BASE	0x15000000
+#define DEFAULT_FB_SIZE		(1024*768*4)
+#define DEFAULT_VID_BASE	(0x19000000 + 0x67A4000)
+#define DEFAULT_VID_SIZE	(0x67A4000)
+#define DEFAULT_VID_BASE2	(0x19000000 + 2*0x67A4000)
+
+struct pxa168fb_info {
+	struct device           *dev;
+	struct clk              *clk;
+	int                     id;
+	void                    *reg_base;
+	void                    *dsi1_reg_base;
+	void                    *dsi2_reg_base;
+	unsigned long           new_addr[3];    /* three addr for YUV
+						   planar */
+	unsigned char           *filterBufList[MAX_QUEUE_NUM][3];
+	unsigned char           *buf_freelist[MAX_QUEUE_NUM];
+	unsigned char           *buf_waitlist[MAX_QUEUE_NUM];
+	unsigned char           *buf_current;
+	dma_addr_t              fb_start_dma;
+	void                    *fb_start;
+	int                     fb_size;
+	dma_addr_t              fb_start_dma_bak;
+	void                    *fb_start_bak;
+	int                     fb_size_bak;
+	int                     dma_ctrl0;
+	int                     fixed_output;
+	unsigned char           *hwc_buf;
+	unsigned int            pseudo_palette[16];
+	char                    *mode_option;
+	struct fb_info          *fb_info;
+	int                     io_pin_allocation;
+	int                     pix_fmt;
+	unsigned                is_blanked:1;
+	unsigned                edid:1;
+	unsigned                cursor_enabled:1;
+	unsigned                cursor_cfg:1;
+	unsigned                panel_rbswap:1;
+	unsigned                debug:1;
+	unsigned                active:1;
+	unsigned                enabled:1;
+	unsigned                edid_en:1;
+
+	/*
+	 * 0: DMA mem is from DMA region.
+	 * 1: DMA mem is from normal region.
+	 */
+	unsigned                mem_status:1;
+	unsigned                wait_vsync;
+
+	struct pxa168fb_mach_info	*mi;
+	struct fb_var_screeninfo	*var;
+	struct fb_fix_screeninfo	*fix;
+};
+
+#define FB_VISUAL_TRUECOLOR             2       /* True color   */
+#define FB_VISUAL_PSEUDOCOLOR           3       /* Pseudo color (like atari) */
+
+#define FB_SYNC_HOR_HIGH_ACT    1       /* horizontal sync high active  */
+#define FB_SYNC_VERT_HIGH_ACT   2       /* vertical sync high active    */
+
+/*       DSI Controller Registers       */
+struct dsi_lcd_regs {
+	u32 ctrl0;
+	u32 ctrl1;
+	u32 reserved1[2];
+	u32 timing0;
+	u32 timing1;
+	u32 timing2;
+	u32 timing3;
+	u32 wc0;
+	u32 wc1;
+	u32 wc2;
+	u32 reserved[1];
+	u32 slot_cnt0;
+	u32 slot_cnt1;
+};
+
+
+
+struct dsi_regs {
+	u32 ctrl0;
+	u32 ctrl1;
+	u32 reserved1[2];
+	u32 irq_status;
+	u32 irq_mask;
+	u32 reserved2[2];
+	u32 cmd0;
+	u32 cmd1;
+	u32 cmd2;
+	u32 cmd3;
+	u32 dat0;
+	u32 reserved3[7];
+
+	u32 smt_cmd;
+	u32 smt_ctrl0;
+	u32 smt_ctrl1;
+	u32 reserved4[1];
+
+	u32 rx0_status;
+	u32 rx0_header;
+	u32 rx1_status;
+	u32 rx1_header;
+	u32 rx_ctrl;
+	u32 rx_ctrl1;
+	u32 rx2_status;
+	u32 rx2_header;
+	u32 reserved5[1];
+
+	u32 phy_ctrl1;
+	u32 phy_ctrl2;
+	u32 phy_ctrl3;
+	u32 phy_status0;
+	u32 reserved6[7];
+
+	u32 phy_rcomp0;
+	u32 reserved7[3];
+	u32 phy_timing0;
+	u32 phy_timing1;
+	u32 phy_timing2;
+	u32 phy_timing3;
+	u32 phy_timing4;
+	u32 phy_timing5;
+	u32 reserved8[2];
+	u32 mem_ctrl;
+	u32 tx_timer;
+	u32 rx_timer;
+	u32 turn_timer;
+	u32 reserved9[4];
+
+	struct dsi_lcd_regs lcd1;
+	u32 reserved10[18];
+	struct dsi_lcd_regs lcd2;
+};
+
+#define DSI_CTRL_0_CFG_SOFT_RST				(1<<31)
+#define DSI_CTRL_0_CFG_SOFT_RST_REG			(1<<30)
+#define DSI_CTRL_0_CFG_LCD1_TX_EN			(1<<8)
+#define DSI_CTRL_0_CFG_LCD1_SLV				(1<<4)
+#define DSI_CTRL_0_CFG_LCD1_EN				(1<<0)
+
+#define DSI_CTRL_1_CFG_EOTP				(1<<8)
+#define DSI_CTRL_1_CFG_LCD2_VCH_NO_MASK			(3<<2)
+#define DSI_CTRL_1_CFG_LCD2_VCH_NO_SHIFT		2
+#define DSI_CTRL_1_CFG_LCD1_VCH_NO_MASK			(3<<0)
+#define DSI_CTRL_1_CFG_LCD1_VCH_NO_SHIFT		0
+
+/* LCD 1 Vsync Reset Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_VSYNC_RST_EN		(1<<31)
+/* Long Blanking Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HLP_PKT_EN		(1<<22)
+/* Front Porch Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HFP_PKT_EN		(1<<20)
+/* hact Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HACT_PKT_EN		(1<<19)
+/* Back Porch Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HBP_PKT_EN		(1<<18)
+/* hse Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HSE_PKT_EN		(1<<17)
+/* hsa Packet Enable */
+#define	DSI_LCD1_CTRL_1_CFG_L1_HSA_PKT_EN		(1<<16)
+/* Turn Around Bus at Last h Line */
+#define	DSI_LCD1_CTRL_1_CFG_L1_LAST_LINE_TURN		(1<<10)
+/* Go to Low Power Every Frame */
+#define	DSI_LCD1_CTRL_1_CFG_L1_LPM_FRAME_EN		(1<<9)
+/* Go to Low Power Every Line */
+#define	DSI_LCD1_CTRL_1_CFG_L1_LPM_LINE_EN		(1<<8)
+/* DSI Transmission Mode for LCD 1 */
+#define DSI_LCD1_CTRL_1_CFG_L1_BURST_MODE_SHIFT		2
+/* LCD 1 Input Data RGB Mode for LCD 1 */
+#define DSI_LCD2_CTRL_1_CFG_L1_RGB_TYPE_SHIFT		0
+
+/* DPHY Data Lane Enable */
+#define	DSI_PHY_CTRL_2_CFG_CSR_LANE_EN_SHIFT		4
+
+/*		Bit(s) DSI_CPU_CMD_1_RSRV_31_24 reserved */
+/* LPDT TX Enable */
+#define	DSI_CPU_CMD_1_CFG_TXLP_LPDT_SHIFT		20
+/* Low Power TX Trigger Code */
+#define	DSI_CPU_CMD_1_CFG_TXLP_TRIGGER_CODE_SHIFT	0
+
+/* Length of HS Exit Period in tx_clk_esc Cycles */
+#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_EXIT_SHIFT	24
+/* DPHY HS Trail Period Length */
+#define	DSI_PHY_TIME_0_CFG_CSR_TIME_HS_TRAIL_SHIFT	16
+/* DPHY HS Zero State Length */
+#define	DSI_PHY_TIME_0_CDG_CSR_TIME_HS_ZERO_SHIFT	8
+
+/* Time to Drive LP-00 by New Transmitter */
+#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GET_SHIFT	24
+/* Time to Drive LP-00 after Turn Request */
+#define	DSI_PHY_TIME_1_CFG_CSR_TIME_TA_GO_SHIFT		16
+
+/* DPHY CLK Exit Period Length */
+#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_EXIT_SHIFT	24
+/* DPHY CLK Trail Period Length */
+#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_TRAIL_SHIFT	16
+/* DPHY CLK Zero State Length */
+#define	DSI_PHY_TIME_2_CFG_CSR_TIME_CK_ZERO_SHIFT	8
+
+/* DPHY LP Length */
+#define	DSI_PHY_TIME_3_CFG_CSR_TIME_LPX_SHIFT		8
+
+/* DSI timings */
+#define DSI_ESC_CLK                 66  /* Unit: Mhz */
+#define DSI_ESC_CLK_T               15  /* Unit: ns */
+
+/* LVDS */
+#define LCD_LVDS_SCLK_DIV_WR		(0x01f4)
+#define LCD_LVDS_SCLK_DIV_RD		(0x01fc)
+
+#define LCD_2ND_BLD_CTL				(0x02fc)
+#define LVDS_SRC_MASK				(3 << 30)
+#define LVDS_SRC_SHIFT				(30)
+#define LVDS_FMT_MASK				(1 << 28)
+#define LVDS_FMT_SHIFT				(28)
+
+/* LVDS_PHY_CTRL */
+#define LVDS_PHY_CTL				0x2a4
+#define LVDS_PLL_LOCK				(1 << 31)
+#define LVDS_PHY_EXT_MASK			(7 << 28)
+#define LVDS_PHY_EXT_SHIFT			(28)
+#define LVDS_CLK_PHASE_MASK			(0x7f << 16)
+#define LVDS_CLK_PHASE_SHIFT		(16)
+#define LVDS_SSC_RESET_EXT			(1 << 13)
+#define LVDS_SSC_MODE_DOWN_SPREAD	(1 << 12)
+#define LVDS_SSC_EN					(1 << 11)
+#define LVDS_PU_PLL					(1 << 10)
+#define LVDS_PU_TX					(1 << 9)
+#define LVDS_PU_IVREF				(1 << 8)
+#define LVDS_CLK_SEL				(1 << 7)
+#define LVDS_CLK_SEL_LVDS_PCLK		(1 << 7)
+#define LVDS_PD_CH_MASK				(0x3f << 1)
+#define LVDS_PD_CH(ch)				((ch) << 1)
+#define LVDS_RST					(1 << 0)
+
+#define LVDS_PHY_CTL_EXT			0x2A8
+
+/* LVDS_PHY_CTRL_EXT1 */
+#define LVDS_SSC_RNGE_MASK			(0x7ff << 16)
+#define LVDS_SSC_RNGE_SHIFT			(16)
+#define LVDS_RESERVE_IN_MASK		(0xf << 12)
+#define LVDS_RESERVE_IN_SHIFT		(12)
+#define LVDS_TEST_MON_MASK			(0x7 << 8)
+#define LVDS_TEST_MON_SHIFT			(8)
+#define LVDS_POL_SWAP_MASK			(0x3f << 0)
+#define LVDS_POL_SWAP_SHIFT			(0)
+
+/* LVDS_PHY_CTRL_EXT2 */
+#define LVDS_TX_DIF_AMP_MASK		(0xf << 24)
+#define LVDS_TX_DIF_AMP_SHIFT		(24)
+#define LVDS_TX_DIF_CM_MASK			(0x3 << 22)
+#define LVDS_TX_DIF_CM_SHIFT		(22)
+#define LVDS_SELLV_TXCLK_MASK		(0x1f << 16)
+#define LVDS_SELLV_TXCLK_SHIFT		(16)
+#define LVDS_TX_CMFB_EN				(0x1 << 15)
+#define LVDS_TX_TERM_EN				(0x1 << 14)
+#define LVDS_SELLV_TXDATA_MASK		(0x1f << 8)
+#define LVDS_SELLV_TXDATA_SHIFT		(8)
+#define LVDS_SELLV_OP7_MASK			(0x3 << 6)
+#define LVDS_SELLV_OP7_SHIFT		(6)
+#define LVDS_SELLV_OP6_MASK			(0x3 << 4)
+#define LVDS_SELLV_OP6_SHIFT		(4)
+#define LVDS_SELLV_OP9_MASK			(0x3 << 2)
+#define LVDS_SELLV_OP9_SHIFT		(2)
+#define LVDS_STRESSTST_EN			(0x1 << 0)
+
+/* LVDS_PHY_CTRL_EXT3 */
+#define LVDS_KVCO_MASK				(0xf << 28)
+#define LVDS_KVCO_SHIFT				(28)
+#define LVDS_CTUNE_MASK				(0x3 << 26)
+#define LVDS_CTUNE_SHIFT			(26)
+#define LVDS_VREG_IVREF_MASK		(0x3 << 24)
+#define LVDS_VREG_IVREF_SHIFT		(24)
+#define LVDS_VDDL_MASK				(0xf << 20)
+#define LVDS_VDDL_SHIFT				(20)
+#define LVDS_VDDM_MASK				(0x3 << 18)
+#define LVDS_VDDM_SHIFT				(18)
+#define LVDS_FBDIV_MASK				(0xf << 8)
+#define LVDS_FBDIV_SHIFT			(8)
+#define LVDS_REFDIV_MASK			(0x7f << 0)
+#define LVDS_REFDIV_SHIFT			(0)
+
+/* LVDS_PHY_CTRL_EXT4 */
+#define LVDS_SSC_FREQ_DIV_MASK		(0xffff << 16)
+#define LVDS_SSC_FREQ_DIV_SHIFT		(16)
+#define LVDS_INTPI_MASK				(0xf << 12)
+#define LVDS_INTPI_SHIFT			(12)
+#define LVDS_VCODIV_SEL_SE_MASK		(0xf << 8)
+#define LVDS_VCODIV_SEL_SE_SHIFT	(8)
+#define LVDS_RESET_INTP_EXT			(0x1 << 7)
+#define LVDS_VCO_VRNG_MASK			(0x7 << 4)
+#define LVDS_VCO_VRNG_SHIFT			(4)
+#define LVDS_PI_EN					(0x1 << 3)
+#define LVDS_ICP_MASK				(0x7 << 0)
+#define LVDS_ICP_SHIFT				(0)
+
+/* LVDS_PHY_CTRL_EXT5 */
+#define LVDS_FREQ_OFFSET_MASK			(0x1ffff << 15)
+#define LVDS_FREQ_OFFSET_SHIFT			(15)
+#define LVDS_FREQ_OFFSET_VALID			(0x1 << 2)
+#define LVDS_FREQ_OFFSET_MODE_CK_DIV4_OUT	(0x1 << 1)
+#define LVDS_FREQ_OFFSET_MODE_EN		(0x1 << 0)
+
+void *pxa168fb_init(struct pxa168fb_mach_info *mi);
+void *pxa168fb_hdmi_set_mode(u32 cea_id, u32 enable_3d);
+void pxa168fb_vid(u32 enable, u32 xres, u32 yres);
+
+
+#endif /* __ASM_MACH_PXA168FB_H */
diff --git a/include/sdhci.h b/include/sdhci.h
index 6d52ce9f75..2dd36a47c0 100644
--- a/include/sdhci.h
+++ b/include/sdhci.h
@@ -27,6 +27,7 @@
 #define __SDHCI_HW_H
 
 #include <asm/io.h>
+#include <mmc.h>
 /*
  * Controller registers
  */
@@ -219,6 +220,7 @@
  */
 #define SDHCI_DEFAULT_BOUNDARY_SIZE	(512 * 1024)
 #define SDHCI_DEFAULT_BOUNDARY_ARG	(7)
+struct sdhci_host;
 struct sdhci_ops {
 #ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
 	u32             (*read_l)(struct sdhci_host *host, int reg);
@@ -236,6 +238,7 @@ struct sdhci_host {
 	unsigned int quirks;
 	unsigned int version;
 	unsigned int clock;
+	struct mmc *mmc;
 	const struct sdhci_ops *ops;
 };
 
diff --git a/include/sparse_format.h b/include/sparse_format.h
new file mode 100644
index 0000000000..fae8bcc739
--- /dev/null
+++ b/include/sparse_format.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+typedef struct sparse_header {
+  __le32	magic;		/* 0xed26ff3a */
+  __le16	major_version;	/* (0x1) - reject images with higher major versions */
+  __le16	minor_version;	/* (0x0) - allow images with higer minor versions */
+  __le16	file_hdr_sz;	/* 28 bytes for first revision of the file format */
+  __le16	chunk_hdr_sz;	/* 12 bytes for first revision of the file format */
+  __le32	blk_sz;		/* block size in bytes, must be a multiple of 4 (4096) */
+  __le32	total_blks;	/* total blocks in the non-sparse output image */
+  __le32	total_chunks;	/* total chunks in the sparse input image */
+  __le32	image_checksum; /* CRC32 checksum of the original data, counting "don't care" */
+				/* as 0. Standard 802.3 polynomial, use a Public Domain */
+				/* table implementation */
+  __le32	reserved1;
+} sparse_header_t;
+
+#define SPARSE_HEADER_MAGIC	0xed26ff3a
+
+#define CHUNK_TYPE_RAW		0xCAC1
+#define CHUNK_TYPE_FILL		0xCAC2
+#define CHUNK_TYPE_DONT_CARE	0xCAC3
+
+typedef struct chunk_header {
+  __le16	chunk_type;	/* 0xCAC1 -> raw; 0xCAC2 -> fill; 0xCAC3 -> don't care */
+  __le16	reserved1;
+  __le32	reserved2;
+  __le32	chunk_sz;	/* in blocks in output image */
+  __le32	total_sz;	/* in bytes of chunk input file including chunk header and data */
+} chunk_header_t;
diff --git a/include/usb/mv_udc.h b/include/usb/mv_udc.h
new file mode 100644
index 0000000000..51d36c3f34
--- /dev/null
+++ b/include/usb/mv_udc.h
@@ -0,0 +1,151 @@
+/*
+ * Copyright 2011, Marvell Semiconductor Inc.
+ * Lei Wen <leiwen@marvell.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+
+#ifndef __MV_UDC_H__
+#define __MV_UDC_H__
+
+#include <asm/byteorder.h>
+#include <asm/errno.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+/* Endpoint 0 states */
+#define EP0_IDLE		0
+#define EP0_IN_DATA		1
+#define EP0_OUT_DATA		2
+#define EP0_XFER_COMPLETE	3
+
+
+/* Endpoint parameters */
+#define MAX_ENDPOINTS		4
+#define EP_MAX_PACKET_SIZE	0x200
+
+#define EP0_MAX_PACKET_SIZE	64
+#define UDC_OUT_ENDPOINT        0x02
+#define UDC_OUT_PACKET_SIZE	EP_MAX_PACKET_SIZE
+#define UDC_IN_ENDPOINT         0x01
+#define UDC_IN_PACKET_SIZE      EP_MAX_PACKET_SIZE
+#define UDC_INT_ENDPOINT        0x05
+#define UDC_INT_PACKET_SIZE     EP_MAX_PACKET_SIZE
+#define UDC_BULK_PACKET_SIZE    EP_MAX_PACKET_SIZE
+
+#define        NUM_ENDPOINTS   6
+#define		REQ_COUNT	12
+struct mv_ep {
+	struct usb_ep ep;
+	struct usb_request req;
+	struct list_head queue;
+	const struct usb_endpoint_descriptor *desc;
+};
+
+struct mv_udc {
+	u32 pad0[80];
+#define MICRO_8FRAME	0x8
+#define USBCMD_ITC(x)	(((x > 0xff) ? 0xff : x) << 16)
+#define USBCMD_FS2	(1 << 15)
+#define USBCMD_RST	(1 << 1)
+#define USBCMD_RUN	(1)
+	u32 usbcmd;		/* 0x140 */
+#define STS_SLI		(1 << 8)
+#define STS_URI		(1 << 6)
+#define STS_PCI		(1 << 2)
+#define STS_UEI		(1 << 1)
+#define STS_UI		(1 << 0)
+	u32 usbsts;		/* 0x144 */
+	u32 pad1[3];
+	u32 devaddr;		/* 0x154 */
+	u32 epinitaddr;		/* 0x158 */
+	u32 pad2[10];
+#define PTS_ENABLE	2
+#define PTS(x)		((x & 0x3) << 30)
+#define PFSC		(1 << 24)
+	u32 portsc;		/* 0x184 */
+	u32 pad3[8];
+#define USBMODE_DEVICE	2
+	u32 usbmode;		/* 0x1a8 */
+	u32 epstat;		/* 0x1ac */
+#define EPT_TX(x)	(1 << ((x & 0xffff) + 16))
+#define EPT_RX(x)	(1 << (x & 0xffff))
+	u32 epprime;		/* 0x1b0 */
+	u32 epflush;		/* 0x1b4 */
+	u32 pad4;
+	u32 epcomp;		/* 0x1bc */
+#define CTRL_TXE              (1 << 23)
+#define CTRL_TXR              (1 << 22)
+#define CTRL_RXE              (1 << 7)
+#define CTRL_RXR              (1 << 6)
+#define CTRL_TXT_BULK         (2 << 18)
+#define CTRL_RXT_BULK         (2 << 2)
+	u32 epctrl[16];		/* 0x1c0 */
+};
+
+struct mv_drv {
+	struct usb_gadget		gadget;
+	struct usb_gadget_driver		*driver;
+	struct mv_udc			*udc;
+};
+
+struct ept_queue_head {
+	unsigned config;
+	unsigned current; /* read-only */
+
+	unsigned next;
+	unsigned info;
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved_0;
+
+	unsigned char setup_data[8];
+
+	unsigned reserved_1;
+	unsigned reserved_2;
+	unsigned reserved_3;
+	unsigned reserved_4;
+};
+
+#define CONFIG_MAX_PKT(n)     ((n) << 16)
+#define CONFIG_ZLT            (1 << 29)    /* stop on zero-len xfer */
+#define CONFIG_IOS            (1 << 15)    /* IRQ on setup */
+
+struct ept_queue_item {
+	unsigned next;
+	unsigned info;
+	unsigned page0;
+	unsigned page1;
+	unsigned page2;
+	unsigned page3;
+	unsigned page4;
+	unsigned reserved;
+};
+
+#define TERMINATE 1
+#define INFO_BYTES(n)         ((n) << 16)
+#define INFO_IOC              (1 << 15)
+#define INFO_ACTIVE           (1 << 7)
+#define INFO_HALTED           (1 << 6)
+#define INFO_BUFFER_ERROR     (1 << 5)
+#define INFO_TX_ERROR         (1 << 3)
+
+extern int usb_lowlevel_init(void);
+#endif /* __MV_UDC_H__ */