diff options
| author | James Bottomley <JBottomley@Parallels.com> | 2015-01-12 10:50:51 -0800 |
|---|---|---|
| committer | James Bottomley <JBottomley@Parallels.com> | 2015-01-24 17:32:16 -0800 |
| commit | e2bd80690bc6b636fd117040257b2160c71263a6 (patch) | |
| tree | 0cc3fdb22a27bd6f24819c307527aeae96a698c7 | |
| parent | 6436c3346e8f19bc8220bcc5266129aa070a9520 (diff) | |
| download | Quark_EDKII-e2bd80690bc6b636fd117040257b2160c71263a6.tar.gz | |
v1.0.2
76 files changed, 3814 insertions, 2806 deletions
diff --git a/IA32FamilyCpuBasePkg/SecCore/Ia32/ResetVec.asm16 b/IA32FamilyCpuBasePkg/SecCore/Ia32/ResetVec.asm16 index 63db4f8..04161a6 100644 --- a/IA32FamilyCpuBasePkg/SecCore/Ia32/ResetVec.asm16 +++ b/IA32FamilyCpuBasePkg/SecCore/Ia32/ResetVec.asm16 @@ -41,7 +41,6 @@ .model tiny
.686p
- .stack 0h
.code
;
@@ -49,6 +48,8 @@ ;
ORG 0h
+__ModuleEntryPoint PROC
+__ModuleEntryPoint ENDP
;
; FIT table pointer for LT-SX.
;
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi new file mode 100644 index 0000000..9908a83 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/AD7298.asi @@ -0,0 +1,69 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ AD7298.asi
+
+ Abstract:
+
+ Analog devices AD7298 ADC.
+
+--*/
+
+Device(ADC1)
+{
+ Name(_HID, "INT3494") // Galileo Version 1 Low-Speed ADC.
+ Name(_CID, "INT3494")
+ Name(RBUF, ResourceTemplate()
+ {
+ // SPI0: mode 2, 4Mhz, 16-bit data length
+ SpiSerialBus (0x0000, PolarityLow, FourWireMode, 16, ControllerInitiated, 4000000, ClockPolarityHigh, ClockPhaseFirst, "\\_SB_.PCI0.SPI0",0x00, ResourceConsumer, ,)
+
+ // GPIO<0> is SPI0_CS_N
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {QUARK_GPIO0_MAPPING}
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi new file mode 100644 index 0000000..58bd862 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/ADC108S102.asi @@ -0,0 +1,64 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ ADC108S102.asi
+
+ Abstract:
+
+ TI ADC108S102 ADC.
+
+--*/
+
+Device(ADC2)
+{
+ Name(_HID, "INT3495") // GalileoGen2 Low-Speed ADC.
+ Name(_CID, "INT3495")
+ Name(RBUF, ResourceTemplate()
+ {
+ SPISerialBus(0x0000, PolarityLow, ThreeWireMode, 0x10, ControllerInitiated, 0x1E8480, ClockPolarityLow, ClockPhaseFirst, "\\_SB.PCI0.SPI0", 0x00, ResourceConsumer, ,)
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi new file mode 100644 index 0000000..08065f5 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CAT24C08.asi @@ -0,0 +1,65 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ CAT24C08.asi
+
+ Abstract:
+
+ ONSEMI CAT24C08 I2C 8KB EEPROM.
+
+--*/
+
+Device(EEP2)
+{
+ Name(_HID, "INT3499") // ONSEMI CAT24C08 I2C 8KB EEPROM.
+ Name(_CID, "INT3499")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x54, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi new file mode 100644 index 0000000..75aa886 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/CY8C9540A.asi @@ -0,0 +1,77 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ CY8C9540A.asi
+
+ Abstract:
+
+ CY8C9540A 40 Bit I/O Expander with EEPROM.
+
+--*/
+
+Device(CY8C)
+{
+ Name(_HID, "INT3490") // Cypress CY8C9540A Io Expander Function.
+ Name(_CID, "INT3490")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x20, ControllerInitiated, 100000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO5_MAPPING} /* GPIO<5> is INT_S0 */
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ CreateByteField(RBUF, 16, OB1)
+ if (LEqual (ALTS, 0))
+ {
+ Store(0x20, OB1)
+ }
+ Else
+ {
+ Store(0x21, OB1)
+ }
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi new file mode 100644 index 0000000..19979c7 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/GpioClient.asi @@ -0,0 +1,120 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ GpioClient.asi
+
+ Abstract:
+
+ Expose GPIO resources to usermode through client driver.
+
+--*/
+
+Device(GPOT)
+{
+ Name(_HID, "INT349A")
+ Name(_CID, "INT349A")
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Name(RBUF, ResourceTemplate()
+ {
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x1}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x2}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x3}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x4}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x5}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x6}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x7}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x8}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0x9}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xa}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xb}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xc}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xd}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xe}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.PCI0.GIP0.GPO_", 0, ResourceConsumer, , ) {0xf}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x2}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x3}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x4}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x5}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x6}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x7}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x8}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x9}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xa}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xb}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xc}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xd}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xe}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0xf}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x10}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x11}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x12}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x13}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x14}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x15}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x16}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x17}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x18}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x19}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1a}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1b}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1c}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1d}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1e}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x1f}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x20}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x21}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x22}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x23}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x24}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x25}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x26}
+ GpioIO(Shared, PullDefault, 0, 0, IoRestrictionNone, "\\_SB.CY8C", 0, ResourceConsumer, , ) {0x27}
+ })
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Galileo platform has this device.
+ // EFI_PLATFORM_TYPE enum value Galileo = 6.
+ //
+ If(LNotEqual(PTYP, 6))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi index 1e2597e..0796022 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/LpcDev.asi @@ -180,17 +180,8 @@ Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else 0,
0,
0x01,
- 0x20,
- FIX6
- )
-
- IO(
- Decode16,
- 0,
- 0,
- 0x01,
0x40,
- FIX7
+ FIX6
)
}
@@ -218,13 +209,9 @@ Device(XTRA) // all "PNP0C02" devices- pieces that don't fit anywhere else CreateWordField (CRS, ^FIX5._MAX, MBR9)
Store(\SMBB, MBR9)
CreateWordField (CRS, ^FIX6._MIN, MBRA)
- Store(\SPIB, MBRA)
+ Store(\WDTB, MBRA)
CreateWordField (CRS, ^FIX6._MAX, MBRB)
- Store(\SPIB, MBRB)
- CreateWordField (CRS, ^FIX7._MIN, MBRC)
- Store(\WDTB, MBRC)
- CreateWordField (CRS, ^FIX7._MAX, MBRD)
- Store(\WDTB, MBRD)
+ Store(\WDTB, MBRB)
return (CRS)
}
}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi new file mode 100644 index 0000000..4907a17 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCA9685.asi @@ -0,0 +1,65 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ PCA9685.asi
+
+ Abstract:
+
+ NXP PCA9685 i2c-accessible PWM/LED controller.
+
+--*/
+
+Device(PWM1)
+{
+ Name(_HID, "INT3492") // NXP PCA9685 i2c-accessible PWM/LED controller.
+ Name(_CID, "INT3492")
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x47, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi new file mode 100644 index 0000000..4f6c894 --- /dev/null +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PCAL9555A.asi @@ -0,0 +1,121 @@ +/*++
+
+ Copyright (c) 2013 Intel Corporation.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+ Module Name:
+
+ PCAL9555A.asi
+
+ Abstract:
+
+ NXP PCAL9555A i2c-accessible I/O expander.
+
+--*/
+
+Device(NIO1)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 1)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x25, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
+Device(NIO2)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 2)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x26, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
+
+Device(NIO3)
+{
+ Name(_HID, "INT3491") // NXP PCAL9555A i2c-accessible I/O expander.
+ Name(_CID, "INT3491")
+ Name(_UID, 3)
+
+ Name(RBUF, ResourceTemplate()
+ {
+ I2CSerialBus(0x27, ControllerInitiated, 400000, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer, , )
+ GpioInt (Level, ActiveLow, Exclusive, PullDefault, , "\\_SB.PCI0.GIP0.GPO", 0, ResourceConsumer, , ) {QUARK_GPIO1_MAPPING} /* GPIO<1> is EXP2_INT */
+ })
+ Method(_CRS, 0x0, NotSerialized)
+ {
+ Return(RBUF)
+ }
+ Method(_STA, 0x0, NotSerialized)
+ {
+ //
+ // Only Platform Type / Id 8 has this device.
+ //
+ If(LNotEqual(PTYP, 8))
+ {
+ return (0)
+ }
+ Return(0xf)
+ }
+}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi index db8aef8..8ffbb13 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/PciIrq.asi @@ -78,7 +78,7 @@ Device(LNKA) // PCI IRQ link A Or(PIRA, 0x80, PIRA)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -145,7 +145,7 @@ Device(LNKB) // PCI IRQ link B Or(PIRB, 0x80,PIRB)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -211,7 +211,7 @@ Device(LNKC) // PCI IRQ link C Or(PIRC, 0x80,PIRC)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -275,7 +275,7 @@ Device(LNKD) // PCI IRQ link D Or(PIRD, 0x80,PIRD)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -340,7 +340,7 @@ Device(LNKE) // PCI IRQ link E Or(PIRE, 0x80, PIRE)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -407,7 +407,7 @@ Device(LNKF) // PCI IRQ link F Or(PIRB, 0x80,PIRF)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -473,7 +473,7 @@ Device(LNKG) // PCI IRQ link G Or(PIRG, 0x80,PIRG)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
@@ -537,7 +537,7 @@ Device(LNKH) // PCI IRQ link H Or(PIRH, 0x80,PIRH)
}
- Method(_CRS,0,NotSerialized)
+ Method(_CRS,0,Serialized)
{
Name(BUF0,
ResourceTemplate()
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl index c145ea5..d3c6fe8 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Platform.asl @@ -38,7 +38,6 @@ --*/
-
//
// OS TYPE DEFINITION
//
@@ -48,8 +47,35 @@ #define WINDOWS_2003 0x08
#define WINDOWS_Vista 0x10
#define WINDOWS_WIN7 0x11
+#define WINDOWS_WIN8 0x12
+#define WINDOWS_WIN8_1 0x13
#define LINUX 0xF0
+//
+// GPIO Interrupt Connection Resource Descriptor (GpioInt) usage.
+// GpioInt() descriptors maybe used in this file and included .asi files.
+//
+// The mapping below was provided by the first OS user that requested
+// GpioInt() support.
+// Other OS users that need GpioInt() support must use the following mapping.
+//
+#define QUARK_GPIO8_MAPPING 0x00
+#define QUARK_GPIO9_MAPPING 0x01
+#define QUARK_GPIO_SUS0_MAPPING 0x02
+#define QUARK_GPIO_SUS1_MAPPING 0x03
+#define QUARK_GPIO_SUS2_MAPPING 0x04
+#define QUARK_GPIO_SUS3_MAPPING 0x05
+#define QUARK_GPIO_SUS4_MAPPING 0x06
+#define QUARK_GPIO_SUS5_MAPPING 0x07
+#define QUARK_GPIO0_MAPPING 0x08
+#define QUARK_GPIO1_MAPPING 0x09
+#define QUARK_GPIO2_MAPPING 0x0A
+#define QUARK_GPIO3_MAPPING 0x0B
+#define QUARK_GPIO4_MAPPING 0x0C
+#define QUARK_GPIO5_MAPPING 0x0D
+#define QUARK_GPIO6_MAPPING 0x0E
+#define QUARK_GPIO7_MAPPING 0x0F
+
DefinitionBlock (
"Platform.aml",
"DSDT",
@@ -65,7 +91,7 @@ DefinitionBlock ( //
// Port 80
- //
+ //
OperationRegion (DBG0, SystemIO, 0x80, 1)
Field (DBG0, ByteAcc, NoLock, Preserve)
{ IO80,8 }
@@ -88,12 +114,12 @@ DefinitionBlock ( HPEA, 32, // HPET Enabled ?
P1BB, 32, // Pm1blkIoBaseAddress;
- PBAB, 32, // PmbaIoBaseAddress;
+ PBAB, 32, // PmbaIoBaseAddress;
GP0B, 32, // Gpe0blkIoBaseAddress;
GPAB, 32, // GbaIoBaseAddress;
SMBB, 32, // SmbaIoBaseAddress;
- SPIB, 32, // SpiDmaIoBaseAddress;
+ NRV1, 32, // GNVS reserved field 1.
WDTB, 32, // WdtbaIoBaseAddress;
HPTB, 32, // HpetBaseAddress;
@@ -107,6 +133,9 @@ DefinitionBlock ( APCS, 32, // IoApicSize;
TPMP, 32, // TpmPresent ?
+ DBGP, 32, // DBG2 Present?
+ PTYP, 32, // Set to one of EFI_PLATFORM_TYPE enums.
+ ALTS, 32, // Use alternate I2c SLA addresses.
}
OperationRegion (GPEB, SystemIO, 0x1100, 0x40) //GPE Block
@@ -237,7 +266,7 @@ DefinitionBlock ( //
Method(_WAK, 1, Serialized)
{
- // Do nothing here
+ // Do nothing here
Return (0)
}
@@ -306,6 +335,14 @@ DefinitionBlock ( {
Store (WINDOWS_WIN7, OSTP)
}
+ If (\_OSI("Windows 2012"))
+ {
+ Store (WINDOWS_WIN8, OSTP)
+ }
+ If (\_OSI("Windows 2013"))
+ {
+ Store (WINDOWS_WIN8_1, OSTP)
+ }
If (\_OSI("Linux"))
{
Store (LINUX, OSTP)
@@ -313,13 +350,29 @@ DefinitionBlock ( }
}
- Include ("PciHostBridge.asi") // PCI0 Host bridge
+ Include ("PciHostBridge.asi") // PCI0 Host bridge
Include ("QNC.asi") // QNC miscellaneous
- Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
+ Include ("PcieExpansionPrt.asi") // PCIe expansion bridges/devices
Include ("QuarkSouthCluster.asi") // Quark South Cluster devices
Include ("QNCLpc.asi") // LPC bridge device
Include ("QNCApic.asi") // QNC I/O Apic device
+
}
- Include ("Tpm.asi") // TPM device
+
+ //
+ // Include asi files for I2C and SPI onboard devices.
+ // Devices placed here instead of below relevant controllers.
+ // Hardware topology information is maintained by the
+ // ResourceSource arg to the I2CSerialBus/SPISerialBus macros
+ // within the device asi files.
+ //
+ Include ("Tpm.asi") // TPM device.
+ Include ("CY8C9540A.asi") // CY8C9540A 40Bit I/O Expander & EEPROM
+ Include ("PCAL9555A.asi") // NXP PCAL9555A I/O expander.
+ Include ("PCA9685.asi") // NXP PCA9685 PWM/LED controller.
+ Include ("CAT24C08.asi") // ONSEMI CAT24C08 I2C 8KB EEPROM.
+ Include ("AD7298.asi") // Analog devices AD7298 ADC.
+ Include ("ADC108S102.asi") // TI ADC108S102 ADC.
+ Include ("GpioClient.asi") // Software device to expose GPIO
}
}
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi index ea9bebb..dfe1b82 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/QuarkSouthCluster.asi @@ -34,7 +34,7 @@ Abstract:
- Quark South Cluster Devices
+ Quark South Cluster Devices.
--*/
@@ -116,6 +116,26 @@ Device (GIP0) // I2C/GPIO [Bus 0, Device 21, Function 2] Name(_ADR,0x00150002) // Device (HI WORD)=21, Func (LO WORD)=2
Name(_STA,0xF) // Enabled, do Display
Name(_PRW,Package(){0x0F,0x03}) // GPE pin 0x0F, Wake from S3 -- PCI PME#
-}
+ Device(GPO_) // GPIO Virtual Child Device- for BAR0 resources
+ {
+ Name(_ADR, 0)
+ Name(_STA, 0xf)
+ Name(_PRW, Package(0x2)
+ {
+ 0xf,
+ 0x3
+ })
+ }
+ Device(I2C_) // I2C Controller Virtual Child Device- for BAR1 resources
+ {
+ Name(_ADR, 1)
+ Name(_STA, 0xf)
+ Name(_PRW, Package(0x2)
+ {
+ 0xf,
+ 0x3
+ })
+ }
+}
#endif
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi index a893b82..0638e6d 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Dsdt/Tpm.asi @@ -1,4 +1,5 @@ /** @file
+
The Infineon SLB9645 TPM ACPI definition block.
Provides TPM device info. and TPM presence check only.
@@ -48,12 +49,10 @@ Device (TPM) //
// Return the resource consumed by TPM device.
- // Quark validated ACPI compiler does not support ACPI 5.0.
- // Hence comment out _CRS!
//
- //Name (_CRS, ResourceTemplate () {
- // I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\_SB.TPM", 0, ResourceConsumer,,)
- //})
+ Name (_CRS, ResourceTemplate () {
+ I2cSerialBus (0x20, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.GIP0.I2C_", 0, ResourceConsumer,,)
+ })
//
// Check if TPM present.
diff --git a/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h b/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h index 7403200..5aee519 100644 --- a/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h +++ b/QuarkPlatformPkg/Acpi/AcpiTables/Fadt/Fadt.h @@ -53,7 +53,7 @@ Abstract: //
#define EFI_ACPI_OEM_ID 'I','N','T','E','L',' ' // OEMID 6 bytes long
#define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('T','I','A','N','O',' ',' ',' ') // OEM table id 8 bytes long
-#define EFI_ACPI_OEM_REVISION 0x00000003
+#define EFI_ACPI_OEM_REVISION 0x00000004
#define EFI_ACPI_CREATOR_ID SIGNATURE_32('I','N','T','L')
#define EFI_ACPI_CREATOR_REVISION 0x0100000D
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c index f80584c..981b606 100644 --- a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c +++ b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.c @@ -220,7 +220,7 @@ DsdtTableUpdate ( *Size = sizeof (EFI_GLOBAL_NVS_AREA);
}
break;
-
+
//
// Update processor PBLK register I/O base address
//
@@ -275,7 +275,7 @@ ApicTableUpdate ( UINTN NumberOfEnabledCPUs;
UINTN BufferSize;
EFI_PROCESSOR_INFORMATION MpContext;
- ACPI_APIC_STRUCTURE_PTR *ApicPtr;
+ ACPI_APIC_STRUCTURE_PTR *ApicPtr;
CurrIoApic = 0;
CurrProcessor = 0;
@@ -311,7 +311,7 @@ ApicTableUpdate ( EndPtr = EndPtr + TableHeader->Length;
while (CurrPtr < EndPtr) {
-
+
ApicPtr = (ACPI_APIC_STRUCTURE_PTR*) CurrPtr;
switch (ApicPtr->AcpiApicCommon.Type) {
@@ -353,7 +353,7 @@ ApicTableUpdate ( }
CurrIoApic++;
break;
-
+
default:
break;
};
@@ -420,31 +420,31 @@ AcpiUpdateTable ( FadtHeader1->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader1->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader1->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
- FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
+ FadtHeader1->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader1->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
} else if (TableHeader->Revision == EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
*Version = EFI_ACPI_TABLE_VERSION_2_0;
- FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
+ FadtHeader2 = (EFI_ACPI_2_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader2->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader2->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader2->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
- FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
+ FadtHeader2->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
FadtHeader2->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader2->XPm1aEvtBlk.Address = FadtHeader2->Pm1aEvtBlk;
FadtHeader2->XPm1aCntBlk.Address = FadtHeader2->Pm1aCntBlk;
- FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk;
+ FadtHeader2->XPmTmrBlk.Address = FadtHeader2->PmTmrBlk;
FadtHeader2->XGpe0Blk.Address = FadtHeader2->Gpe0Blk;
} else if (TableHeader->Revision == EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION) {
- *Version = EFI_ACPI_TABLE_VERSION_3_0;
+ *Version = EFI_ACPI_TABLE_VERSION_3_0;
FadtHeader3 = (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE *) TableHeader;
FadtHeader3->SmiCmd = PcdGet16(PcdSmmActivationPort);
FadtHeader3->Pm1aEvtBlk = PcdGet16(PcdPm1blkIoBaseAddress);
FadtHeader3->Pm1aCntBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1C;
- FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
- FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
+ FadtHeader3->PmTmrBlk = PcdGet16(PcdPm1blkIoBaseAddress) + R_QNC_PM1BLK_PM1T;
+ FadtHeader3->Gpe0Blk = PcdGet16(PcdGpe0blkIoBaseAddress);
FadtHeader3->XPm1aEvtBlk.Address = FadtHeader3->Pm1aEvtBlk;
FadtHeader3->XPm1aCntBlk.Address = FadtHeader3->Pm1aCntBlk;
- FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk;
+ FadtHeader3->XPmTmrBlk.Address = FadtHeader3->PmTmrBlk;
FadtHeader3->XGpe0Blk.Address = FadtHeader3->Gpe0Blk;
}
break;
@@ -571,23 +571,26 @@ AcpiPlatformEntryPoint ( IN EFI_SYSTEM_TABLE *SystemTable
)
{
- EFI_STATUS Status;
+ EFI_STATUS Status;
EFI_ACPI_TABLE_PROTOCOL *AcpiTable;
EFI_FIRMWARE_VOLUME2_PROTOCOL *FwVol;
- INTN Instance;
- EFI_ACPI_COMMON_HEADER *CurrentTable;
- UINTN TableHandle;
- UINT32 FvStatus;
- UINTN Size;
- EFI_ACPI_TABLE_VERSION Version;
- QNC_DEVICE_ENABLES QNCDeviceEnables;
- EFI_HANDLE Handle;
+ INTN Instance;
+ EFI_ACPI_COMMON_HEADER *CurrentTable;
+ UINTN TableHandle;
+ UINT32 FvStatus;
+ UINTN Size;
+ EFI_ACPI_TABLE_VERSION Version;
+ QNC_DEVICE_ENABLES QNCDeviceEnables;
+ EFI_HANDLE Handle;
UINTN Index;
PCI_DEVICE_INFO *PciDeviceInfo;
EFI_ACPI_HANDLE PciRootHandle;
BOOLEAN UpdatePRT;
BOOLEAN UpdatePRW;
PCI_DEVICE_SETTING *mConfigData;
+ EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
+
+ DEBUG((DEBUG_INFO, "ACPI Platform start...\n"));
Instance = 0;
TableHandle = 0;
@@ -598,6 +601,9 @@ AcpiPlatformEntryPoint ( //
// Initialize the EFI Driver Library
//
+ Status = gBS->LocateProtocol (&gEfiPlatformTypeProtocolGuid, NULL, (VOID **) &PlatformType);
+ DEBUG((DEBUG_INFO, "ACPI Platform locate gEfiPlatformTypeProtocolGuid protocol...\n"));
+ ASSERT_EFI_ERROR (Status);
ASSERT (sizeof (EFI_GLOBAL_NVS_AREA) == 512);
@@ -627,23 +633,35 @@ AcpiPlatformEntryPoint ( //
// Initialize the data. Eventually, this will be controlled by setup options.
//
- mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable);
+ mGlobalNvsArea.Area->HpetEnable = PcdGetBool (PcdHpetEnable);
mGlobalNvsArea.Area->Pm1blkIoBaseAddress = PcdGet16(PcdPm1blkIoBaseAddress);
- mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress);
+ mGlobalNvsArea.Area->PmbaIoBaseAddress = PcdGet16(PcdPmbaIoBaseAddress);
mGlobalNvsArea.Area->Gpe0blkIoBaseAddress = PcdGet16(PcdGpe0blkIoBaseAddress);
- mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress);
+ mGlobalNvsArea.Area->GbaIoBaseAddress = PcdGet16(PcdGbaIoBaseAddress);
mGlobalNvsArea.Area->SmbaIoBaseAddress = PcdGet16(PcdSmbaIoBaseAddress);
- mGlobalNvsArea.Area->SpiDmaIoBaseAddress = PcdGet16(PcdSpiDmaIoBaseAddress);
mGlobalNvsArea.Area->WdtbaIoBaseAddress = PcdGet16(PcdWdtbaIoBaseAddress);
- mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress);
- mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize);
- mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress);
- mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize);
- mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);
- mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize);
- mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
+ mGlobalNvsArea.Area->HpetBaseAddress = (UINT32)PcdGet64(PcdHpetBaseAddress);
+ mGlobalNvsArea.Area->HpetSize = (UINT32)PcdGet64(PcdHpetSize);
+ mGlobalNvsArea.Area->PciExpressBaseAddress= (UINT32)PcdGet64(PcdPciExpressBaseAddress);
+ mGlobalNvsArea.Area->PciExpressSize = (UINT32)PcdGet64(PcdPciExpressSize);
+ mGlobalNvsArea.Area->RcbaMmioBaseAddress = (UINT32)PcdGet64(PcdRcbaMmioBaseAddress);
+ mGlobalNvsArea.Area->RcbaMmioSize = (UINT32)PcdGet64(PcdRcbaMmioSize);
+ mGlobalNvsArea.Area->IoApicBaseAddress = (UINT32)PcdGet64(PcdIoApicBaseAddress);
mGlobalNvsArea.Area->IoApicSize = (UINT32)PcdGet64(PcdIoApicSize);
mGlobalNvsArea.Area->TpmPresent = (UINT32)(FALSE);
+ mGlobalNvsArea.Area->DBG2Present = (UINT32)(FALSE);
+ mGlobalNvsArea.Area->PlatformType = (UINT32)PlatformType->Type;
+
+ //
+ // Configure platform IO expander I2C Slave Address.
+ //
+ if (PlatformType->Type == Galileo) {
+ if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {
+ mGlobalNvsArea.Area->AlternateSla = FALSE;
+ } else {
+ mGlobalNvsArea.Area->AlternateSla = TRUE;
+ }
+ }
//
// Find the AcpiTable protocol
@@ -655,7 +673,7 @@ AcpiPlatformEntryPoint ( //
// Initialize MADT table
- //
+ //
Status = MadtTableInitialize (&CurrentTable, &Size);
ASSERT_EFI_ERROR (Status);
//
@@ -664,13 +682,13 @@ AcpiPlatformEntryPoint ( AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
- // Update the check sum
+ // Update the check sum
// It needs to be zeroed before the checksum calculation
//
- ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
- ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
-
+
//
// Add the table
//
@@ -725,13 +743,13 @@ AcpiPlatformEntryPoint ( AcpiUpdateTable ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable, &Version);
//
- // Update the check sum
+ // Update the check sum
// It needs to be zeroed before the checksum calculation
//
- ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
- ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum = 0;
+ ((EFI_ACPI_SDT_HEADER *)CurrentTable)->Checksum =
CalculateCheckSum8 ((VOID *)CurrentTable, CurrentTable->Length);
-
+
//
// Add the table
//
@@ -758,7 +776,7 @@ AcpiPlatformEntryPoint ( PciRootHandle = NULL;
PciRootHandle = SdtGetRootBridgeHandle (mAcpiSdt, mDsdtHandle);
- ASSERT (PciRootHandle != NULL);
+ ASSERT (PciRootHandle != NULL);
PciDeviceInfo = NULL;
for (Index = 0; Index < mConfigData->PciDeviceInfoNumber; Index++) {
@@ -783,7 +801,7 @@ AcpiPlatformEntryPoint ( // Update the pci routing information
//
//DEBUG ((EFI_D_ERROR, "Update _PRT\n"));
- SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);
+ SdtUpdatePciRouting (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
//
// Check whether there is any valid pci routing item
@@ -793,7 +811,7 @@ AcpiPlatformEntryPoint ( // Update the pci wakeup information
//
//DEBUG ((EFI_D_ERROR, "Update _PRW\n"));
- SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);
+ SdtUpdatePowerWake (mAcpiSdt, PciRootHandle, PciDeviceInfo);
}
}
}
@@ -805,7 +823,7 @@ AcpiPlatformEntryPoint ( ((EFI_AML_HANDLE *)mDsdtHandle)->Modified = TRUE;
Status = mAcpiSdt->Close (mDsdtHandle);
ASSERT_EFI_ERROR (Status);
- }
+ }
//
// Increment the instance
//
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h index 8af6070..4525831 100644 --- a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h +++ b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.h @@ -51,11 +51,16 @@ Abstract: #include <PiDxe.h>
#include <IntelQNCDxe.h>
#include <QuarkPlatformDxe.h>
+#include <Platform.h>
+#include <PlatformBoards.h>
+#include <Ioh.h>
+#include <QNCCommonDefinitions.h>
#include <Protocol/GlobalNvsArea.h>
#include <Protocol/MpService.h>
#include <Protocol/AcpiSupport.h>
#include <Protocol/FirmwareVolume2.h>
+#include <Protocol/PlatformType.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/UefiBootServicesTableLib.h>
@@ -68,6 +73,8 @@ Abstract: #include <Library/DxeServicesLib.h>
#include <Library/DevicePathLib.h>
#include <Library/MemoryAllocationLib.h>
+#include <Library/QNCAccessLib.h>
+#include <Library/PlatformHelperLib.h>
#include <IndustryStandard/Acpi.h>
#include <IndustryStandard/HighPrecisionEventTimerTable.h>
diff --git a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf index 8a003c3..03fee10 100644 --- a/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf +++ b/QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf @@ -75,112 +75,114 @@ UefiBootServicesTableLib
UefiDriverEntryPoint
DevicePathLib
+ PlatformHelperLib
[Protocols]
gEfiGlobalNvsAreaProtocolGuid # PROTOCOL ALWAYS_CONSUMED
gEfiMpServiceProtocolGuid # PROTOCOL SOMETIMES_CONSUMED
gEfiAcpiSdtProtocolGuid # PROTOCOL ALWAYS_CONSUMED
- gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+ gEfiAcpiTableProtocolGuid # PROTOCOL ALWAYS_CONSUMED
+ gEfiPlatformTypeProtocolGuid # PROTOCOL ALWAYS_CONSUMED
[FixedPcd]
gUefiCpuPkgTokenSpaceGuid.PcdCpuLocalApicBaseAddress
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable1GlobalIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable3GlobalIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable4GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable5GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable6GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable7GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable8GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9Polarity
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq
-
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq
-
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable9GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable10GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable11GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable12GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable13GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable14GlobalIrq
+
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Enable
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15SourceIrq
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15Polarity
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15TrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable15GlobalIrq
+
gEfiQuarkNcSocIdTokenSpaceGuid.PcdIoApicBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingIoApicAddress
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingGlobalInterruptBase
@@ -188,7 +190,7 @@ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiEnable
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingNmiSource
gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingPolarity
- gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode
+ gQuarkPlatformTokenSpaceGuid.PcdIoApicSettingTrigerMode
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingNmiEnabelApicIdMask
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingAddressOverrideEnable
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingPolarity
@@ -209,8 +211,7 @@ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciExpressSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
- gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize
- gEfiQuarkNcSocIdTokenSpaceGuid.PcdSpiDmaIoBaseAddress
+ gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioSize
gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress
gQuarkPlatformTokenSpaceGuid.PcdHpetEnable
gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables
diff --git a/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c b/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c index 7172f50..5ddb386 100755 --- a/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c +++ b/QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.c @@ -807,9 +807,7 @@ Returns: // When entering a power-managed state like S3,
// PERST# must be asserted in advance of power-off.
//
- if (mPlatformType != GalileoFabE) {
- PlatformPERSTAssert (mPlatformType);
- }
+ PlatformPERSTAssert (mPlatformType);
return EFI_SUCCESS;
}
diff --git a/QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin b/QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin Binary files differdeleted file mode 100644 index da17eb4..0000000 --- a/QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin +++ /dev/null diff --git a/QuarkPlatformPkg/Cpu/Sec/ResetVector/Ia32/ResetVec.asm16 b/QuarkPlatformPkg/Cpu/Sec/ResetVector/Ia32/ResetVec.asm16 index 86e2ade..bf924c2 100644 --- a/QuarkPlatformPkg/Cpu/Sec/ResetVector/Ia32/ResetVec.asm16 +++ b/QuarkPlatformPkg/Cpu/Sec/ResetVector/Ia32/ResetVec.asm16 @@ -41,7 +41,6 @@ .model tiny
.686p
- .stack 0h
.code
;
@@ -49,6 +48,8 @@ ;
ORG 0h
+__ModuleEntryPoint PROC
+__ModuleEntryPoint ENDP
;
; This is located at 0xFFFFFFD0h
;
diff --git a/QuarkPlatformPkg/Include/Guid/PlatformDataFileNameGuids.h b/QuarkPlatformPkg/Include/Guid/PlatformDataFileNameGuids.h index de01552..c7e1dd0 100644 --- a/QuarkPlatformPkg/Include/Guid/PlatformDataFileNameGuids.h +++ b/QuarkPlatformPkg/Include/Guid/PlatformDataFileNameGuids.h @@ -61,6 +61,10 @@ Abstract: #ifndef _PLATFORM_DATA_FILE_NAME_GUIDS_H_
#define _PLATFORM_DATA_FILE_NAME_GUIDS_H_
+//
+// Known platform file name Guids.
+//
+
#define SVP_PDAT_FILE_NAME_GUID \
{ 0xa975562, 0xdf47, 0x4dc3, { 0x8a, 0xb0, 0x3b, 0xa2, 0xc3, 0x52, 0x23, 0x2 } }
@@ -76,9 +80,6 @@ Abstract: #define GALILEO_PDAT_FILE_NAME_GUID \
{ 0xe4ad87c8, 0xd20e, 0x40ce, { 0x97, 0xf5, 0x97, 0x56, 0xfd, 0xe, 0x81, 0xd4 } }
-#define GALILEO_FABE_PDAT_FILE_NAME_GUID \
- { 0xe27ada6a, 0x9f8a, 0x4f2e, { 0xb0, 0x9e, 0x4c, 0xcd, 0xd8, 0x2c, 0x2f, 0x54 } }
-
#define GALILEO_GEN2_PDAT_FILE_NAME_GUID \
{ 0x23b3c10d, 0x46e3, 0x4a78, { 0x8a, 0xaa, 0x21, 0x7b, 0x6a, 0x39, 0xef, 0x4 } }
@@ -94,8 +95,6 @@ Abstract: CLANTONHILL_PDAT_FILE_NAME_GUID,\
/* EFI_PLATFORM_TYPE - Galileo*/\
GALILEO_PDAT_FILE_NAME_GUID,\
- /* EFI_PLATFORM_TYPE - GalileoFabE*/\
- GALILEO_FABE_PDAT_FILE_NAME_GUID,\
/* EFI_PLATFORM_TYPE - GalileoGen2*/\
GALILEO_GEN2_PDAT_FILE_NAME_GUID,\
diff --git a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h index f5af79d..81bccb7 100644 --- a/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h +++ b/QuarkPlatformPkg/Include/Library/PlatformHelperLib.h @@ -41,6 +41,7 @@ Abstract: #ifndef __PLATFORM_HELPER_LIB_H__
#define __PLATFORM_HELPER_LIB_H__
+#include "Platform.h"
#include "PlatformData.h"
//
@@ -108,10 +109,10 @@ PlatformDebugPortGetChar8 ( /**
Return platform type string given platform type enum.
- ASSERT if invalid platform type enum.
+ @param PlatformType Executing platform type.
+ ASSERT if invalid platform type enum.
ASSERT if EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION has no entries.
-
ASSERT if EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION has no string for type.
@return string for platform type enum.
@@ -120,7 +121,22 @@ PlatformDebugPortGetChar8 ( CHAR16 *
EFIAPI
PlatformTypeString (
- IN CONST UINT16 Type
+ IN CONST EFI_PLATFORM_TYPE Type
+ );
+
+/**
+ Return if platform type value is supported.
+
+ @param PlatformType Executing platform type.
+
+ @retval TRUE If type within range and not reserved.
+ @retval FALSE if type is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformIsSupportedPlatformType (
+ IN CONST EFI_PLATFORM_TYPE Type
);
/**
@@ -302,4 +318,118 @@ PlatformLegacyGpioSetLevel ( IN CONST UINT32 GpioNum,
IN CONST BOOLEAN HighLevel
);
+
+/**
+ Get Legacy GPIO Level
+
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.
+ @param GpioNum GPIO bit to check.
+
+ @retval TRUE If bit is SET.
+ @retval FALSE If bit is CLEAR.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformLegacyGpioGetLevel (
+ IN CONST UINT32 LevelRegOffset,
+ IN CONST UINT32 GpioNum
+ );
+
+/**
+ Set the direction of Pcal9555 IO Expander GPIO pin.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0
+ and 8-15 for Port1.
+ @param CfgAsInput If TRUE set pin direction as input else set as output.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetDir (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN CfgAsInput
+ );
+
+/**
+ Set the level of Pcal9555 IO Expander GPIO high or low.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+ @param HighLevel If TRUE set pin high else set pin low.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetLevel (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN HighLevel
+ );
+
+/**
+
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioEnablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ );
+
+/**
+
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioDisablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ );
+
+/**
+ Init platform LEDs into known state.
+
+ @param PlatformType Executing platform type.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformLedInit (
+ IN CONST EFI_PLATFORM_TYPE Type
+ );
+
+/**
+ Turn on or off platform flash update LED.
+
+ @param PlatformType Executing platform type.
+ @param TurnOn If TRUE turn on else turn off.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashUpdateLed (
+ IN CONST EFI_PLATFORM_TYPE Type,
+ IN CONST BOOLEAN TurnOn
+ );
+
#endif // #ifndef __PLATFORM_HELPER_LIB_H__
diff --git a/QuarkPlatformPkg/Include/Pcal9555.h b/QuarkPlatformPkg/Include/Pcal9555.h index cfbd46b..9b2ad2d 100644 --- a/QuarkPlatformPkg/Include/Pcal9555.h +++ b/QuarkPlatformPkg/Include/Pcal9555.h @@ -43,6 +43,11 @@ Abstract: #define __PCAL9555_H__
#define PCAL9555_REG_OUT_PORT0 0x02
+#define PCAL9555_REG_OUT_PORT1 0x03
#define PCAL9555_REG_CFG_PORT0 0x06
+#define PCAL9555_REG_CFG_PORT1 0x07
+
+#define PCAL9555_REG_PULL_EN_PORT0 0x46
+#define PCAL9555_REG_PULL_EN_PORT1 0x47
#endif
diff --git a/QuarkPlatformPkg/Include/Platform.h b/QuarkPlatformPkg/Include/Platform.h index 6f34ff5..04f2d81 100755 --- a/QuarkPlatformPkg/Include/Platform.h +++ b/QuarkPlatformPkg/Include/Platform.h @@ -94,6 +94,12 @@ Abstract: #define PLATFORM_CATASTROPHIC_TRIP_CELSIUS 105
//
+// Platform flash update LED common definitions.
+//
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT 7
+#define PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA (1000 * 1000) // In Microseconds for EFI_STALL.
+
+//
// This structure stores the base and size of the ACPI reserved memory used when
// resuming from S3. This region must be allocated by the platform code.
//
@@ -109,17 +115,19 @@ typedef struct { // Define valid platform types.
// First add value before TypePlatformMax in EFI_PLATFORM_TYPE definition
// and then add string description to end of EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION.
+// Value shown for supported platforms to help sanity checking with build tools
+// and ACPI method usage.
//
typedef enum {
TypeUnknown = 0, // !!! SHOULD BE THE FIRST ENTRY !!!
- QuarkEmulation,
- ClantonPeakSVP,
- KipsBay,
- CrossHill,
- ClantonHill,
- Galileo,
- GalileoFabE,
- GalileoGen2,
+ QuarkEmulation = 1,
+ ClantonPeakSVP = 2,
+ KipsBay = 3,
+ CrossHill = 4,
+ ClantonHill = 5,
+ Galileo = 6,
+ TypePlatformRsv7 = 7,
+ GalileoGen2 = 8,
TypePlatformMax // !!! SHOULD BE THE LAST ENTRY !!!
} EFI_PLATFORM_TYPE;
@@ -131,7 +139,7 @@ typedef enum { L"CrossHill",\
L"ClantonHill",\
L"Galileo",\
- L"GalileoGen2", /* FabE should use same name as final Gen2 */\
+ L"TypePlatformRsv7",\
L"GalileoGen2",\
typedef struct {
diff --git a/QuarkPlatformPkg/Include/PlatformBoards.h b/QuarkPlatformPkg/Include/PlatformBoards.h index de942bb..783ae90 100755 --- a/QuarkPlatformPkg/Include/PlatformBoards.h +++ b/QuarkPlatformPkg/Include/PlatformBoards.h @@ -64,7 +64,6 @@ Abstract: #define CROSS_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x03,0x10,0x00,0x03,0x03,0x00,0x3f,0x00}
#define CLANTON_HILL_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x06,0x10,0x00,0x04,0x04,0x00,0x3f,0x00}
#define GALILEO_LEGACY_GPIO_INITIALIZER {0x03,0x00,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x21,0x14,0x00,0x00,0x00,0x00,0x3f,0x00}
-#define GALILEO_FABE_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1f,0x00,0x00,0x00,0x00,0x00,0x3f,0x00}
#define GALILEO_GEN2_LEGACY_GPIO_INITIALIZER {0x03,0x03,0x00,0x00,0x00,0x00,0x00,0x03,0x00,0x3f,0x1c,0x02,0x00,0x00,0x00,0x00,0x3f,0x00}
#define NULL_GPIO_CONTROLLER_INITIALIZER {0,0,0,0,0,0,0,0}
@@ -76,7 +75,6 @@ Abstract: #define CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER {0x01,0x39,0,0,0,0,0,0}
#define GALILEO_GPIO_CONTROLLER_INITIALIZER {0x05,0x15,0,0,0,0,0,0}
#define GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER {0x05,0x05,0,0,0,0,0,0}
-#define GALILEO_FABE_GPIO_CONTROLLER_INITIALIZER GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER
//
// Legacy Gpio to be used to assert / deassert PCI express PERST# signal
@@ -85,14 +83,28 @@ Abstract: #define GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO 0
//
-// Galileo Gen 2 I2C PCAL9555 IO Expander definitions
+// Io expander slave address.
//
-#define PCAL9555_GALILEO_GEN2_7BIT_SLAVE_ADDR 0x27
-#define PCAL9555_GALILEO_GEN2_PORT0_CFG 0xff
-#define PCAL9555_GALILEO_GEN2_PORT1_CFG 0x9f
-#define PCAL9555_GALILEO_GEN2_PORT0_DEFAULT_OUT 0xff
-#define PCAL9555_GALILEO_GEN2_PORT1_DEFAULT_OUT 0xbf
-#define PCAL9555_GALILEO_GEN2_PERST_GPIO 13 // 0-7 Port0 8-15 Port1
+
+//
+// On Galileo value of Jumper J2 determines slave address of io expander.
+//
+#define GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO 5
+#define GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR 0x20
+#define GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR 0x21
+
+//
+// Three IO Expmanders at fixed addresses on Galileo Gen2.
+//
+#define GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR 0x25
+#define GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR 0x26
+#define GALILEO_GEN2_IOEXP2_7BIT_SLAVE_ADDR 0x27
+
+//
+// Led GPIOs for flash update / recovery.
+//
+#define GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO 1
+#define GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO 5
//
// Legacy GPIO config struct for each element in PLATFORM_LEGACY_GPIO_TABLE_DEFINITION.
@@ -152,8 +164,8 @@ typedef struct { CLANTON_HILL_LEGACY_GPIO_INITIALIZER,\
/* EFI_PLATFORM_TYPE - Galileo*/\
GALILEO_LEGACY_GPIO_INITIALIZER,\
- /* EFI_PLATFORM_TYPE - GalileoFabE*/\
- GALILEO_FABE_LEGACY_GPIO_INITIALIZER,\
+ /* EFI_PLATFORM_TYPE - TypePlatformRsv7*/\
+ NULL_LEGACY_GPIO_INITIALIZER,\
/* EFI_PLATFORM_TYPE - GalileoGen2*/\
GALILEO_GEN2_LEGACY_GPIO_INITIALIZER,\
@@ -177,8 +189,8 @@ typedef struct { CLANTON_HILL_GPIO_CONTROLLER_INITIALIZER,\
/* EFI_PLATFORM_TYPE - Galileo*/\
GALILEO_GPIO_CONTROLLER_INITIALIZER,\
- /* EFI_PLATFORM_TYPE - GalileoFabE */\
- GALILEO_FABE_GPIO_CONTROLLER_INITIALIZER,\
+ /* EFI_PLATFORM_TYPE - TypePlatformRsv7 */\
+ NULL_GPIO_CONTROLLER_INITIALIZER,\
/* EFI_PLATFORM_TYPE - GalileoGen2*/\
GALILEO_GEN2_GPIO_CONTROLLER_INITIALIZER,\
diff --git a/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h b/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h index 40aff32..58769e5 100644 --- a/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h +++ b/QuarkPlatformPkg/Include/Protocol/GlobalNvsArea.h @@ -69,7 +69,7 @@ typedef struct { UINT32 GbaIoBaseAddress;
UINT32 SmbaIoBaseAddress;
- UINT32 SpiDmaIoBaseAddress;
+ UINT32 Reserved1;
UINT32 WdtbaIoBaseAddress;
UINT32 HpetBaseAddress;
@@ -83,8 +83,11 @@ typedef struct { UINT32 IoApicSize;
UINT32 TpmPresent;
+ UINT32 DBG2Present;
+ UINT32 PlatformType; // Set to one of EFI_PLATFORM_TYPE enums.
+ UINT32 AlternateSla; // If TRUE use alternate I2C Slave addresses.
- UINT8 Reserved[512 - 4 * 19]; // Total 512 Bytes
+ UINT8 Reserved[512 - 4 * 22]; // Total 512 Bytes
} EFI_GLOBAL_NVS_AREA;
#pragma pack ()
diff --git a/QuarkPlatformPkg/Library/MfhLib/MfhLib.c b/QuarkPlatformPkg/Library/MfhLib/MfhLib.c index b9ab18a..14bbc97 100644 --- a/QuarkPlatformPkg/Library/MfhLib/MfhLib.c +++ b/QuarkPlatformPkg/Library/MfhLib/MfhLib.c @@ -89,8 +89,8 @@ FindNext ( FlashItem = &FindContext->FlashItemList[*IdxPtr];
if (*IdxPtr >= FlashItemCount || FlashItem->Type > 63) {
//
- // Index must < FlashItemCount
- // and since filter is UINT64 the max type is 63 for BIT63.
+ // BootItems must have Index < FlashItemCount
+ // and type <= 63
//
ASSERT (FALSE);
} else {
@@ -110,15 +110,11 @@ FindNext ( }
FlashItem = &FindContext->FlashItemList[*IdxPtr];
- if (FlashItem->Type > 63) {
- //
- // Since Filter is UINT64 the max type is 63 for BIT63.
- //
- ASSERT (FALSE);
- } else {
- if (MFH_IS_FILTER_MATCH (ItemTypeFilter, FlashItem->Type)) {
- break;
- }
+ //
+ // Since filter is UINT64 then only check types with value < 64.
+ //
+ if (FlashItem->Type < 64 && MFH_IS_FILTER_MATCH (ItemTypeFilter, FlashItem->Type)) {
+ break;
}
(*IdxPtr)++;
} while (TRUE);
diff --git a/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.c b/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.c index 2e6d6e4..25e54a8 100755 --- a/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.c +++ b/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.c @@ -45,12 +45,13 @@ extern USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath; EFI_USER_PROFILE_HANDLE mCurrentUser = NULL;
UINT16 mPayloadBootOptionNumber = 0xffff;
SECUREBOOT_HELPER_PROTOCOL *gSecureBootHelperProtocol = NULL;
+EFI_PLATFORM_TYPE_PROTOCOL *gPlatformType = NULL;
/**
Identify a user and, if authenticated, returns the current user profile handle.
@param[out] User Point to user profile handle.
-
+
@retval EFI_SUCCESS User is successfully identified, or user identification
is not supported.
@retval EFI_ACCESS_DENIED User is not successfully identified
@@ -63,7 +64,7 @@ UserIdentify ( {
EFI_STATUS Status;
EFI_USER_MANAGER_PROTOCOL *Manager;
-
+
Status = gBS->LocateProtocol (
&gEfiUserManagerProtocolGuid,
NULL,
@@ -112,7 +113,7 @@ PlatformGetVideoController ( if (EFI_ERROR (Status) || (RootBridgeHandleCount == 0)) {
return NULL;
}
-
+
Status = gBS->LocateProtocol (
&gEfiPciPlatformProtocolGuid,
NULL,
@@ -153,7 +154,7 @@ PlatformGetVideoController ( &Pci
);
if (!EFI_ERROR (Status) && IS_PCI_VGA (&Pci)) {
- // Set VideoController to default to first video controller.
+ // Set VideoController to default to first video controller.
// This will be the device used if Video Select is set to Auto.
if(VideoController == NULL) {
VideoController = HandleBuffer[Index];
@@ -169,7 +170,7 @@ PlatformGetVideoController ( }
}
FreePool (RootBridgeHandleBuffer);
-
+
return VideoController;
}
@@ -189,11 +190,11 @@ UpdateConOut ( // Get the platform vga device
//
VideoController = PlatformGetVideoController (&OnboardVideoController, &AddinVideoController);
-
+
if (VideoController == NULL) {
return ;
}
-
+
// Force to Auto
VideoSelect = 0;
@@ -207,7 +208,7 @@ UpdateConOut ( }
switch(VideoSelect) {
- case 1:
+ case 1:
// Onboard selected
VideoController = OnboardVideoController;
DEBUG((EFI_D_INFO, "Video select: Onboard\n"));
@@ -225,9 +226,9 @@ UpdateConOut ( }
//
- // Try to connect the PCI device path, so that GOP dirver could start on this
+ // Try to connect the PCI device path, so that GOP dirver could start on this
// device and create child handles with GraphicsOutput Protocol installed
- // on them, then we get device paths of these child handles and select
+ // on them, then we get device paths of these child handles and select
// them as possible console device.
//
gBS->ConnectController (VideoController, NULL, NULL, FALSE);
@@ -346,7 +347,7 @@ PlatformBootManagerBeforeConsole ( InitializeConsoleVariables (gPlatformConsole);
UpdateConOut ();
-
+
RegisterLoadOptions ();
@@ -356,7 +357,7 @@ PlatformBootManagerBeforeConsole ( }
//
- // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
+ // Inform the SMM infrastructure that we're entering BDS and may run 3rd party code hereafter
//
Handle = NULL;
Status = gBS->InstallProtocolInterface (
@@ -366,18 +367,18 @@ PlatformBootManagerBeforeConsole ( NULL
);
ASSERT_EFI_ERROR (Status);
-
+
//
- // Append Usb Keyboard short form DevicePath into "ConInDev"
+ // Append Usb Keyboard short form DevicePath into "ConInDev"
//
EfiBootManagerUpdateConsoleVariable (
ConInDev,
(EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,
NULL
);
-
+
//
- // Before user authentication, the user identification devices need be connected
+ // Before user authentication, the user identification devices need be connected
// from the platform customized device paths
//
ConnectAuthDevice ();
@@ -396,17 +397,17 @@ ConnectSequence ( Routine Description:
- Connect with predeined platform connect sequence,
+ Connect with predeined platform connect sequence,
the OEM/IBV can customize with their own connect sequence.
-
+
Arguments:
None.
-
+
Returns:
None.
-
+
--*/
{
UINTN Index;
@@ -437,11 +438,11 @@ FvFilePath ( EFI_GUID *FileGuid
)
{
-
+
EFI_STATUS Status;
EFI_LOADED_IMAGE_PROTOCOL *LoadedImage;
MEDIA_FW_VOL_FILEPATH_DEVICE_PATH FileNode;
- EFI_HANDLE FvProtocolHandle;
+ EFI_HANDLE FvProtocolHandle;
EFI_HANDLE *FvHandleBuffer;
UINTN FvHandleCount;
EFI_FV_FILETYPE Type;
@@ -468,7 +469,7 @@ FvFilePath ( else {
//
// Expose Payload file in FV
- //
+ //
gDS->ProcessFirmwareVolume (
(VOID *)FvBaseAddress,
(UINT32)FvSize,
@@ -680,7 +681,7 @@ Routine Description: Arguments:
BdsDriverLists - The header of the driver option link list.
-
+
Returns:
None.
@@ -774,19 +775,19 @@ Routine Description: Perform the platform diagnostic, such like test memory. OEM/IBV also
can customize this fuction to support specific platform diagnostic.
-
+
Arguments:
MemoryTestLevel - The memory test intensive level
-
+
QuietBoot - Indicate if need to enable the quiet boot
BaseMemoryTest - A pointer to BdsMemoryTest()
-
+
Returns:
None.
-
+
--*/
{
EFI_STATUS Status;
@@ -820,7 +821,7 @@ Returns: /**
Returns the priority number.
- @param BootOption
+ @param BootOption
**/
UINTN
BootOptionPriority (
@@ -830,6 +831,12 @@ BootOptionPriority ( //
// Make sure Shell is in the last
//
+ if (StrCmp (BootOption->Description, L"USB Device") == 0) {
+ return 10;
+ }
+ if (StrCmp (BootOption->Description, L"UEFI Payload") == 0) {
+ return 90;
+ }
if (StrCmp (BootOption->Description, L"UEFI Internal Shell") == 0) {
return 100;
}
@@ -852,7 +859,7 @@ extern EFI_GUID gSignalBeforeEnterSetupGuid; This function Installs a guid before entering the Setup.
**/
-VOID
+VOID
SignalProtocolEvent(IN EFI_GUID *ProtocolGuid)
{
EFI_HANDLE Handle = NULL;
@@ -927,21 +934,21 @@ Routine Description: The function will excute with as the platform policy, current policy
is driven by boot mode. IBV/OEM can customize this code for their specific
policy action.
-
+
Arguments:
DriverOptionList - The header of the driver option link list
-
+
BootOptionList - The header of the boot option link list
ProcessCapsules - A pointer to ProcessCapsules()
BaseMemoryTest - A pointer to BaseMemoryTest()
-
+
Returns:
None.
-
+
--*/
{
EFI_HANDLE Handle;
@@ -956,8 +963,10 @@ Returns: 0x60b5e939, 0xfcf, 0x4227, { 0xba, 0x83, 0x6b, 0xbe, 0xd4, 0x5b, 0xc0, 0xe3 }
};
BOOLEAN SecureBootEnabled;
+ BOOLEAN FalseUpdateLedOn;
SecureBootEnabled = FALSE;
+ FalseUpdateLedOn = FALSE;
if(gSecureBootHelperProtocol != NULL) {
SecureBootEnabled = gSecureBootHelperProtocol->IsSecureBootEnabled (
@@ -977,7 +986,7 @@ Returns: DEBUG ((EFI_D_INFO, "[PlatformBds]BootMode = %d\n", (UINTN) BootMode));
//
- // Clear all the capsule variables CapsuleUpdateData, CapsuleUpdateData1, CapsuleUpdateData2...
+ // Clear all the capsule variables CapsuleUpdateData, CapsuleUpdateData1, CapsuleUpdateData2...
// as early as possible which will avoid the next time boot after the capsule update
// will still into the capsule loop
//
@@ -1009,7 +1018,7 @@ Returns: // No deferred image exists by default
//
DeferredImageExist = FALSE;
-
+
//
// Go the different platform policy with different boot mode
// Notes: this part code can be change with the table policy
@@ -1042,6 +1051,16 @@ Returns: ConnectSequence ();
}
}
+
+ //
+ // If unsecure refresh and sort boot options.
+ //
+ if (!FeaturePcdGet (PcdEnableSecureLock)) {
+ DEBUG ((EFI_D_INFO, "[PlatformBds]: Refresh All and Sort.\n"));
+ EfiBootManagerRefreshAllBootOption ();
+ EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);
+ }
+
break;
case BOOT_ON_FLASH_UPDATE:
@@ -1050,6 +1069,8 @@ Returns: //
Status = PlatformClearSpiProtect ();
ASSERT_EFI_ERROR (Status);
+ FalseUpdateLedOn = TRUE;
+ PlatformFlashUpdateLed (gPlatformType->Type, FalseUpdateLedOn);
if (FeaturePcdGet (PcdSupportUpdateCapsuleReset)) {
EfiBootManagerProcessCapsules ();
} else {
@@ -1057,6 +1078,16 @@ Returns: }
//
+ // Toggle flash update LED for a predefined number of times with
+ // a predefined interval.
+ //
+ for (Index = 0; Index < PLATFORM_FLASH_UPDATE_LED_TOGGLE_COUNT; Index++) {
+ FalseUpdateLedOn = (FalseUpdateLedOn) ? FALSE : TRUE;
+ PlatformFlashUpdateLed (gPlatformType->Type, FalseUpdateLedOn);
+ gBS->Stall (PLATFORM_FLASH_UPDATE_LED_TOGGLE_DELTA);
+ }
+
+ //
// Cold reset the system as any flash update are now complete
//
gRT->ResetSystem (EfiResetCold, EFI_SUCCESS, 0, NULL);
@@ -1084,7 +1115,7 @@ Returns: EfiBootManagerConnectAll ();
}
}
-
+
break;
case BOOT_WITH_FULL_CONFIGURATION:
@@ -1115,14 +1146,12 @@ Returns: ConnectSequence ();
}
}
-
+
//
// Here we have enough time to do the enumeration of boot device
//
EfiBootManagerRefreshAllBootOption ();
- if (BootState == NULL) {
- EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);
- }
+ EfiBootManagerSortLoadOptionVariable (LoadOptionTypeBoot, CompareBootOption);
break;
}
@@ -1173,7 +1202,7 @@ Returns: Connect the predefined platform default authentication devices.
This function connects the predefined device path for authentication device,
- and if the predefined device path has child device path, the child handle will
+ and if the predefined device path has child device path, the child handle will
be connected too. But the child handle of the child will not be connected.
**/
@@ -1185,7 +1214,7 @@ ConnectAuthDevice ( {
EFI_STATUS Status;
UINTN Index;
- UINTN HandleIndex;
+ UINTN HandleIndex;
UINTN HandleCount;
EFI_HANDLE *HandleBuffer;
EFI_DEVICE_PATH_PROTOCOL *ChildDevicePath;
@@ -1198,15 +1227,15 @@ ConnectAuthDevice ( );
if (EFI_ERROR (Status)) {
//
- // As user manager protocol is not installed, the authentication devices
+ // As user manager protocol is not installed, the authentication devices
// should not be connected.
//
return ;
}
-
+
Index = 0;
while (gUserAuthenticationDevice[Index] != NULL) {
- //
+ //
// Connect the platform customized device paths
//
EfiBootManagerConnectDevicePath (gUserAuthenticationDevice[Index], NULL);
@@ -1226,7 +1255,7 @@ ConnectAuthDevice ( &HandleCount,
&HandleBuffer
);
- ASSERT_EFI_ERROR (Status);
+ ASSERT_EFI_ERROR (Status);
//
// Find and connect the child device paths of gUserIdentificationDevice[Index]
@@ -1248,7 +1277,7 @@ ConnectAuthDevice ( (GetDevicePathSize (gUserAuthenticationDevice[Index]) - sizeof (EFI_DEVICE_PATH_PROTOCOL))
) != 0) {
continue;
- }
+ }
gBS->ConnectController (HandleBuffer[HandleIndex], NULL, NULL, TRUE);
}
}
@@ -1280,11 +1309,11 @@ CheckDeferredImage ( UINTN DriverIndex;
EFI_DEVICE_PATH_PROTOCOL *ImageDevicePath;
VOID *DriverImage;
- UINTN ImageSize;
+ UINTN ImageSize;
BOOLEAN BootOption;
//
- // Perform user identification
+ // Perform user identification
//
do {
Status = UserIdentify (User);
@@ -1313,31 +1342,31 @@ CheckDeferredImage ( &gEfiDeferredImageLoadProtocolGuid,
(VOID **) &DeferredImage
);
- if (!EFI_ERROR (Status)) {
+ if (!EFI_ERROR (Status)) {
//
// Find whether deferred image exists in this instance.
//
DriverIndex = 0;
Status = DeferredImage->GetImageInfo(
- DeferredImage,
- DriverIndex,
- &ImageDevicePath,
+ DeferredImage,
+ DriverIndex,
+ &ImageDevicePath,
(VOID **) &DriverImage,
- &ImageSize,
+ &ImageSize,
&BootOption
);
if (!EFI_ERROR (Status)) {
//
// The deferred image is found.
//
- FreePool (HandleBuf);
+ FreePool (HandleBuf);
*DeferredImageExist = TRUE;
return ;
- }
- }
+ }
+ }
}
-
- FreePool (HandleBuf);
+
+ FreePool (HandleBuf);
}
/** Constructor for this lib.
@@ -1379,5 +1408,12 @@ PlatformBootManagerLibConstructor ( //
gSecureBootHelperProtocol = NULL;
}
+
+ //
+ // Get reference to platform type protocol.
+ //
+ Status = gBS->LocateProtocol (&gEfiPlatformTypeProtocolGuid, NULL, (VOID **) &gPlatformType);
+ ASSERT_EFI_ERROR (Status);
+
return EFI_SUCCESS;
}
diff --git a/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.h b/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.h index 51a729e..8e04756 100644 --- a/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.h +++ b/QuarkPlatformPkg/Library/PlatformBootManagerLib/BdsPlatform.h @@ -61,6 +61,7 @@ Abstract: #include <Protocol/AcpiS3Save.h>
#include <Protocol/DxeSmmReadyToLock.h>
#include <Protocol/SecureBootHelper.h>
+#include <Protocol/PlatformType.h>
#include <Guid/CapsuleVendor.h>
#include <Guid/MemoryTypeInformation.h>
@@ -90,7 +91,6 @@ Abstract: #include <IndustryStandard/Pci.h>
#include <IndustryStandard/Atapi.h>
-
typedef struct {
EFI_DEVICE_PATH_PROTOCOL *DevicePath;
UINTN ConnectType;
@@ -101,12 +101,6 @@ typedef struct { #define CONSOLE_IN 0x00000004
#define CONSOLE_ALL (CONSOLE_OUT | CONSOLE_IN | STD_ERROR)
-//
-//
-//
-#define VIDEO_DEV_NUM 0x00
-#define VIDEO_FUNC_NUM 0x00
-
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformRootBridges [];
extern BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole [];
extern EFI_DEVICE_PATH_PROTOCOL *gPlatformAllPossibleAgpConsole [];
@@ -173,8 +167,9 @@ typedef struct { // Platform BDS global variables.
//
-extern PLATFORM_PCI_SERIAL_DEVICE_PATH gSerialDevicePath;
-extern SECUREBOOT_HELPER_PROTOCOL *gSecureBootHelperProtocol;
+extern PLATFORM_PCI_SERIAL_DEVICE_PATH gSerialDevicePath;
+extern SECUREBOOT_HELPER_PROTOCOL *gSecureBootHelperProtocol;
+extern EFI_PLATFORM_TYPE_PROTOCOL *gPlatformType;
//
// Platform BDS Functions
diff --git a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf index b20ed0c..d380864 100755 --- a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf +++ b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf @@ -84,6 +84,7 @@ PlatformHelperLib
[Protocols]
+ gEfiPlatformTypeProtocolGuid
gEfiPciRootBridgeIoProtocolGuid
gEfiLegacyBiosProtocolGuid
gEfiPciIoProtocolGuid
diff --git a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c index 15a4eeb..98fe613 100755 --- a/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c +++ b/QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformData.c @@ -101,17 +101,17 @@ USB_CLASS_FORMAT_DEVICE_PATH gUsbClassKeyboardDevicePath = { (UINT8) (sizeof (USB_CLASS_DEVICE_PATH)),
(UINT8) ((sizeof (USB_CLASS_DEVICE_PATH)) >> 8)
},
- 0xffff, // VendorId
- 0xffff, // ProductId
- CLASS_HID, // DeviceClass
+ 0xffff, // VendorId
+ 0xffff, // ProductId
+ CLASS_HID, // DeviceClass
SUBCLASS_BOOT, // DeviceSubClass
PROTOCOL_KEYBOARD // DeviceProtocol
},
- {
- END_DEVICE_PATH_TYPE,
- END_ENTIRE_DEVICE_PATH_SUBTYPE,
- END_DEVICE_PATH_LENGTH,
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ END_DEVICE_PATH_LENGTH,
0
}
};
@@ -125,7 +125,7 @@ BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = { (CONSOLE_OUT | CONSOLE_IN)
},
{
- (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,
+ (EFI_DEVICE_PATH_PROTOCOL *) &gUsbClassKeyboardDevicePath,
CONSOLE_IN
},
{
@@ -133,7 +133,7 @@ BDS_CONSOLE_CONNECT_ENTRY gPlatformConsole[] = { 0
}
};
-
+
//
// Predefined platform specific perdict boot option
//
@@ -147,16 +147,11 @@ EFI_DEVICE_PATH_PROTOCOL *gPlatformBootOption[] = { EFI_DEVICE_PATH_PROTOCOL *gPlatformDriverOption[] = { NULL };
//
-// Predefined platform connect sequence
-//
-EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = { NULL };
-
-//
// Platform specific USB controller device path
//
PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = {
gPciRootBridge,
- {
+ {
HARDWARE_DEVICE_PATH,
HW_PCI_DP,
(UINT8)(sizeof(PCI_DEVICE_PATH)),
@@ -172,7 +167,7 @@ PLATFORM_USB_DEVICE_PATH gUsbDevicePath0 = { //
PLATFORM_USB_DEVICE_PATH gUsbDevicePath1 = {
gPciRootBridge,
- {
+ {
HARDWARE_DEVICE_PATH,
HW_PCI_DP,
(UINT8)(sizeof(PCI_DEVICE_PATH)),
@@ -195,3 +190,12 @@ EFI_DEVICE_PATH_PROTOCOL* gUserAuthenticationDevice[] = { NULL
};
+//
+// Predefined platform connect sequence
+//
+EFI_DEVICE_PATH_PROTOCOL *gPlatformConnectSequence[] = {
+ (EFI_DEVICE_PATH_PROTOCOL*)&gPlatformRootBridge0, // Force PCI enumer before Legacy OpROM shadow
+ (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath0,
+ (EFI_DEVICE_PATH_PROTOCOL*)&gUsbDevicePath1,
+ NULL
+};
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h b/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h index 7363119..f0e09fb 100644 --- a/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/CommonHeader.h @@ -45,6 +45,8 @@ #include <Library/PlatformDataLib.h>
#include <Library/IntelQNCLib.h>
#include <Platform.h>
+#include <PlatformBoards.h>
+#include <Pcal9555.h>
#include "FlashLayout.h"
#include <CommonIncludes.h>
#include <QNCAccess.h>
@@ -66,4 +68,12 @@ WriteFirstFreeSpiProtect ( OUT UINT32 *OffsetPtr
);
+VOID
+Pcal9555SetPortRegBit (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST UINT8 RegBase,
+ IN CONST BOOLEAN LogicOne
+ );
+
#endif
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf b/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf index bb82271..6a2773b 100644 --- a/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf @@ -57,6 +57,7 @@ PlatformHelperDxe.c
Crc32.c
PlatformSecureBoot.c
+ PlatformLeds.c
[Packages]
MdePkg/MdePkg.dec
@@ -69,7 +70,6 @@ PcdLib
BaseMemoryLib
SerialPortLib
- IohLib
S3BootScriptLib
UefiBootServicesTableLib
UefiRuntimeServicesTableLib
@@ -84,6 +84,7 @@ gEfiSmmSpiProtocolGuid
gSecureBootHelperProtocolGuid
gEfiSmmBase2ProtocolGuid
+ gEfiI2CHcProtocolGuid
[Guids]
gEfiGlobalVariableGuid
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf b/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf index c872a96..069ab67 100644 --- a/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf @@ -70,7 +70,6 @@ PeiServicesTablePointerLib
PeiServicesLib
SerialPortLib
- IohLib
[Guids]
gEfiQuarkCapsuleGuid
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c index 0483134..c95059c 100644 --- a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperDxe.c @@ -48,6 +48,7 @@ Abstract: #include <Protocol/PlatformType.h>
#include <Protocol/SmmBase2.h>
#include <Protocol/Spi.h>
+#include <Protocol/I2CHc.h>
#include <Guid/QuarkVariableLock.h>
@@ -66,6 +67,92 @@ EFI_SPI_PROTOCOL *mPlatHelpSpiProtocolRef = NULL; // Routines local to this component.
//
+//
+// Routines shared with other souce modules in this component.
+//
+
+VOID
+Pcal9555SetPortRegBit (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST UINT8 RegBase,
+ IN CONST BOOLEAN LogicOne
+ )
+{
+ EFI_STATUS Status;
+ UINTN ReadLength;
+ UINTN WriteLength;
+ UINT8 Data[2];
+ EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
+ EFI_I2C_ADDR_MODE I2cAddrMode;
+ UINT8 *RegValuePtr;
+ UINT8 GpioNumMask;
+ UINT8 SubAddr;
+ EFI_I2C_HC_PROTOCOL *I2cBus;
+
+ //
+ // Locate I2C host controller driver.
+ //
+ Status = gBS->LocateProtocol (&gEfiI2CHcProtocolGuid, NULL, (VOID **) &I2cBus);
+ ASSERT_EFI_ERROR (Status);
+
+ I2cDeviceAddr.I2CDeviceAddress = (UINTN) Pcal9555SlaveAddr;
+ I2cAddrMode = EfiI2CSevenBitAddrMode;
+
+ if (GpioNum < 8) {
+ SubAddr = RegBase;
+ GpioNumMask = (UINT8) (1 << GpioNum);
+ } else {
+ SubAddr = RegBase + 1;
+ GpioNumMask = (UINT8) (1 << (GpioNum - 8));
+ }
+
+ //
+ // Output port value always at 2nd byte in Data variable.
+ //
+ RegValuePtr = &Data[1];
+
+ //
+ // On read entry sub address at 2nd byte, on read exit output
+ // port value in 2nd byte.
+ //
+ Data[1] = SubAddr;
+ WriteLength = 1;
+ ReadLength = 1;
+ Status = I2cBus->ReadMultipleByte (
+ I2cBus,
+ I2cDeviceAddr,
+ I2cAddrMode,
+ &WriteLength,
+ &ReadLength,
+ &Data[1]
+ );
+ ASSERT_EFI_ERROR (Status);
+
+ //
+ // Adjust output port bit given callers request.
+ //
+ if (LogicOne) {
+ *RegValuePtr = *RegValuePtr | GpioNumMask;
+ } else {
+ *RegValuePtr = *RegValuePtr & ~(GpioNumMask);
+ }
+
+ //
+ // Update register. Sub address at 1st byte, value at 2nd byte.
+ //
+ WriteLength = 2;
+ Data[0] = SubAddr;
+ Status = I2cBus->WriteMultipleByte (
+ I2cBus,
+ I2cDeviceAddr,
+ I2cAddrMode,
+ &WriteLength,
+ Data
+ );
+ ASSERT_EFI_ERROR (Status);
+}
+
EFI_SPI_PROTOCOL *
LocateSpiProtocol (
@@ -550,4 +637,103 @@ PlatformIsBootWithRecoveryStage1 ( )
{
ASSERT_EFI_ERROR (EFI_UNSUPPORTED);
+ return FALSE;
+}
+
+/**
+ Set the direction of Pcal9555 IO Expander GPIO pin.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio direction to configure - values 0-7 for Port0
+ and 8-15 for Port1.
+ @param CfgAsInput If TRUE set pin direction as input else set as output.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetDir (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN CfgAsInput
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_CFG_PORT0,
+ CfgAsInput
+ );
}
+
+/**
+ Set the level of Pcal9555 IO Expander GPIO high or low.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+ @param HighLevel If TRUE set pin high else set pin low.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioSetLevel (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum,
+ IN CONST BOOLEAN HighLevel
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_OUT_PORT0,
+ HighLevel
+ );
+}
+
+/**
+
+ Enable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioEnablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_PULL_EN_PORT0,
+ TRUE
+ );
+}
+
+/**
+
+ Disable pull-up/pull-down resistors of Pcal9555 GPIOs.
+
+ @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
+ @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
+ for Port1.
+
+**/
+VOID
+EFIAPI
+PlatformPcal9555GpioDisablePull (
+ IN CONST UINT32 Pcal9555SlaveAddr,
+ IN CONST UINT32 GpioNum
+ )
+{
+ Pcal9555SetPortRegBit (
+ Pcal9555SlaveAddr,
+ GpioNum,
+ PCAL9555_REG_PULL_EN_PORT0,
+ FALSE
+ );
+}
\ No newline at end of file diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c index b485fb3..083ad94 100644 --- a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformHelperLib.c @@ -144,10 +144,10 @@ PlatformDebugPortGetChar8 ( /**
Return platform type string given platform type enum.
- ASSERT if invalid platform type enum.
+ @param PlatformType Executing platform type.
+ ASSERT if invalid platform type enum.
ASSERT if EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION has no entries.
-
ASSERT if EFI_PLATFORM_TYPE_NAME_TABLE_DEFINITION has no string for type.
@return string for platform type enum.
@@ -156,14 +156,50 @@ PlatformDebugPortGetChar8 ( CHAR16 *
EFIAPI
PlatformTypeString (
- IN CONST UINT16 Type
+ IN CONST EFI_PLATFORM_TYPE Type
)
{
- ASSERT ((EFI_PLATFORM_TYPE) Type < TypePlatformMax);
+ ASSERT (Type < TypePlatformMax);
ASSERT (mPlatTypeNameTableLen > 0);
ASSERT ((UINTN) Type < mPlatTypeNameTableLen);
- return mPlatTypeNameTable [Type];
+ return mPlatTypeNameTable [(UINTN) Type];
+}
+
+/**
+ Return if platform type value is supported.
+
+ @param PlatformType Executing platform type.
+
+ @retval TRUE If type within range and not reserved.
+ @retval FALSE if type is not supported.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformIsSupportedPlatformType (
+ IN CONST EFI_PLATFORM_TYPE Type
+ )
+{
+ //
+ // Out of range types not supported.
+ //
+ if ((Type == TypeUnknown) || (Type >= TypePlatformMax)) {
+ return FALSE;
+ }
+
+ //
+ // Reserved types not supported.
+ //
+ if (Type == TypePlatformRsv7) {
+ return FALSE;
+ }
+
+ //
+ // All others supported.
+ //
+ return TRUE;
+
}
/**
@@ -306,3 +342,30 @@ PlatformLegacyGpioSetLevel ( }
IoWrite32 (GpioBaseAddress + LevelRegOffset, RegValue);
}
+
+/**
+ Get Legacy GPIO Level
+
+ @param LevelRegOffset GPIO level register Offset from GPIO Base Address.
+ @param GpioNum GPIO bit to check.
+
+ @retval TRUE If bit is SET.
+ @retval FALSE If bit is CLEAR.
+
+**/
+BOOLEAN
+EFIAPI
+PlatformLegacyGpioGetLevel (
+ IN CONST UINT32 LevelRegOffset,
+ IN CONST UINT32 GpioNum
+ )
+{
+ UINT32 RegValue;
+ UINT32 GpioBaseAddress;
+ UINT32 GpioNumMask;
+
+ GpioBaseAddress = LpcPciCfg32 (R_QNC_LPC_GBA_BASE) & B_QNC_LPC_GPA_BASE_MASK;
+ RegValue = IoRead32 (GpioBaseAddress + LevelRegOffset);
+ GpioNumMask = (1 << GpioNum);
+ return ((RegValue & GpioNumMask) != 0);
+}
diff --git a/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c new file mode 100644 index 0000000..0429bc2 --- /dev/null +++ b/QuarkPlatformPkg/Library/PlatformHelperLib/PlatformLeds.c @@ -0,0 +1,177 @@ +/** @file
+
+Copyright (c) 2013 Intel Corporation.
+
+Redistribution and use in source and binary forms, with or without
+modification, are permitted provided that the following conditions
+are met:
+
+* Redistributions of source code must retain the above copyright
+notice, this list of conditions and the following disclaimer.
+* Redistributions in binary form must reproduce the above copyright
+notice, this list of conditions and the following disclaimer in
+the documentation and/or other materials provided with the
+distribution.
+* Neither the name of Intel Corporation nor the names of its
+contributors may be used to endorse or promote products derived
+from this software without specific prior written permission.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+Module Name:
+
+ PlatformLeds.c
+
+Abstract:
+
+ Platform helper LED routines.
+
+--*/
+
+#include <PiDxe.h>
+
+#include "CommonHeader.h"
+
+//
+// Routines defined in other source modules of this component.
+//
+
+//
+// Routines local to this source module.
+//
+
+VOID
+GalileoGen2RouteOutFlashUpdateLed (
+ VOID
+ )
+{
+ //
+ // For GpioNums below values 0 to 7 are for Port0 ie P0-0 - P0-7 and
+ // values 8 to 15 are for Port1 ie P1-0 - P1-7.
+ //
+
+ //
+ // Disable Pull-ups / pull downs on EXP0 pin for LVL_B_PU7 signal.
+ //
+ PlatformPcal9555GpioDisablePull (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 15 // P1-7.
+ );
+
+ //
+ // Make LVL_B_OE7_N an output pin.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 14, // P1-6.
+ FALSE
+ );
+
+ //
+ // Set level of LVL_B_OE7_N to low.
+ //
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR,
+ 14,
+ FALSE
+ );
+
+ //
+ // Make MUX8_SEL an output pin.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 14, // P1-6.
+ FALSE
+ );
+
+ //
+ // Set level of MUX8_SEL to low to route GPIO_SUS<5> to LED.
+ //
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 14, // P1-6.
+ FALSE
+ );
+}
+
+//
+// Routines exported by this source module.
+//
+
+/**
+ Init platform LEDs into known state.
+
+ @param PlatformType Executing platform type.
+ @param I2cBus Pointer to I2c Host controller protocol.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformLedInit (
+ IN CONST EFI_PLATFORM_TYPE Type
+ )
+{
+ EFI_BOOT_MODE BootMode;
+
+ BootMode = GetBootModeHob ();
+
+ //
+ // Init Flash update / recovery LED in OFF state.
+ //
+ if (BootMode == BOOT_ON_FLASH_UPDATE || BootMode == BOOT_IN_RECOVERY_MODE) {
+ if (Type == GalileoGen2) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);
+ GalileoGen2RouteOutFlashUpdateLed ();
+ } else if (Type == Galileo) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, FALSE);
+ } else {
+ //
+ // These platforms have no flash update LED.
+ //
+ }
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
+ Turn on or off platform flash update LED.
+
+ @param PlatformType Executing platform type.
+ @param TurnOn If TRUE turn on else turn off.
+
+ @retval EFI_SUCCESS Operation success.
+
+**/
+EFI_STATUS
+EFIAPI
+PlatformFlashUpdateLed (
+ IN CONST EFI_PLATFORM_TYPE Type,
+ IN CONST BOOLEAN TurnOn
+ )
+{
+ if (Type == GalileoGen2) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);
+ } else if (Type == Galileo) {
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_FLASH_UPDATE_LED_RESUMEWELL_GPIO, TurnOn);
+ } else {
+ //
+ // These platforms have no flash update LED.
+ //
+ }
+
+ return EFI_SUCCESS;
+}
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h index 616c240..331ee41 100644 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h +++ b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/CommonHeader.h @@ -77,16 +77,4 @@ SocUnitReleasePcieControllerPostPllLock ( IN CONST EFI_PLATFORM_TYPE PlatformType
);
-VOID
-EFIAPI
-GalileoFabEPERSTAssert (
- VOID
- );
-
-VOID
-EFIAPI
-GalileoFabEPERSTDeAssert (
- VOID
- );
-
#endif
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/DxePlatformPcieHelperLib.inf b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/DxePlatformPcieHelperLib.inf deleted file mode 100644 index 10faef7..0000000 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/DxePlatformPcieHelperLib.inf +++ /dev/null @@ -1,83 +0,0 @@ -#/*++
-#
-# Copyright (c) 2013 Intel Corporation.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions
-# are met:
-#
-# * Redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer.
-# * Redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in
-# the documentation and/or other materials provided with the
-# distribution.
-# * Neither the name of Intel Corporation nor the names of its
-# contributors may be used to endorse or promote products derived
-# from this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-#
-# Module Name:
-#
-# DxePlatformPcieHelperLib.inf
-#
-# Abstract:
-#
-# Library producing Pci express helper routines for DXE enviroment.
-#
-#--*/
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = DxePlatformPcieHelperLib
- FILE_GUID = 0AEA3B34-2BC9-4fe7-98F3-6F9D963A28E1
- MODULE_TYPE = DXE_DRIVER
- VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformPcieHelperLib|DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SAL_DRIVER SMM_CORE DXE_SMM_DRIVER UEFI_APPLICATION UEFI_DRIVER
-
-#
-# The following information is for reference only and not required by the build tools.
-#
-# VALID_ARCHITECTURES = IA32
-#
-
-[Sources]
- PlatformPcieHelperLib.c
- SocUnit.c
- PlatformPcieHelperDxe.c
-
-[Packages]
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- QuarkSocPkg/QuarkSocPkg.dec
- QuarkPlatformPkg/QuarkPlatformPkg.dec
-
-[LibraryClasses]
- BaseLib
- PcdLib
- IoLib
- DebugLib
- TimerLib
- QNCAccessLib
- IntelQNCLib
- UefiLib
-
-[Protocols]
- gEfiI2CHcProtocolGuid
-
-[Guids]
-
-[FeaturePcd]
-
-[FixedPcd]
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperDxe.c b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperDxe.c deleted file mode 100644 index ed3ff9d..0000000 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperDxe.c +++ /dev/null @@ -1,198 +0,0 @@ -/** @file
-
-Copyright (c) 2013 Intel Corporation.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-* Redistributions of source code must retain the above copyright
-notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-* Neither the name of Intel Corporation nor the names of its
-contributors may be used to endorse or promote products derived
-from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-Module Name:
-
- PlatformPcieHelperDxe.c
-
-Abstract:
-
- Implementation of Pci express helper routines for DXE enviroment.
-
---*/
-
-#include <PiDxe.h>
-
-#include <Library/UefiBootServicesTableLib.h>
-#include <Library/S3BootScriptLib.h>
-#include <Library/DxeServicesLib.h>
-#include <Library/UefiLib.h>
-
-#include <Protocol/PlatformType.h>
-#include <Protocol/I2CHc.h>
-
-#include "CommonHeader.h"
-
-//
-// Routines defined in other source modules of this component.
-//
-
-//
-// Routines local to this component.
-//
-
-/**
- Set the level of Pcal9555 IO Expander GPIO high or low.
-
- No error returned. Function asserts if unable to address io expander.
- Expected to be used with on board devices.
-
- @param I2cBus I2c Host controller protocol.
- @param Pcal9555SlaveAddr I2c Slave address of Pcal9555 Io Expander.
- @param GpioNum Gpio to change values 0-7 for Port0 and 8-15
- for Port1.
- @param HighLevel If TRUE set pin high else set pin low.
-
-**/
-STATIC
-VOID
-Pcal9555GpioSetLevel (
- IN EFI_I2C_HC_PROTOCOL *I2cBus,
- IN CONST UINTN Pcal9555SlaveAddr,
- IN CONST UINT16 GpioNum,
- IN CONST BOOLEAN HighLevel
- )
-{
- EFI_STATUS Status;
- UINTN ReadLength;
- UINTN WriteLength;
- UINT8 Data[2];
- EFI_I2C_DEVICE_ADDRESS I2cDeviceAddr;
- EFI_I2C_ADDR_MODE I2cAddrMode;
- UINT8 *RegValuePtr;
- UINT8 GpioNumMask;
- UINT8 SubAddr;
-
- ASSERT (I2cBus != NULL);
-
- I2cDeviceAddr.I2CDeviceAddress = Pcal9555SlaveAddr;
- I2cAddrMode = EfiI2CSevenBitAddrMode;
-
- if (GpioNum < 8) {
- SubAddr = PCAL9555_REG_OUT_PORT0;
- GpioNumMask = (UINT8) (1 << GpioNum);
- } else {
- SubAddr = PCAL9555_REG_OUT_PORT0 + 1;
- GpioNumMask = (UINT8) (1 << (GpioNum - 8));
- }
-
- //
- // Output port value always at 2nd byte in Data variable.
- //
- RegValuePtr = &Data[1];
-
- //
- // On read entry sub address at 2nd byte, on read exit output
- // port value in 2nd byte.
- //
- Data[1] = SubAddr;
- WriteLength = 1;
- ReadLength = 1;
- Status = I2cBus->ReadMultipleByte (
- I2cBus,
- I2cDeviceAddr,
- I2cAddrMode,
- &WriteLength,
- &ReadLength,
- &Data[1]
- );
- ASSERT_EFI_ERROR (Status);
-
- //
- // Adjust output port value given callers request.
- //
- if (HighLevel) {
- *RegValuePtr = *RegValuePtr | GpioNumMask;
- } else {
- *RegValuePtr = *RegValuePtr & ~(GpioNumMask);
- }
-
- //
- // Update register. Sub address at 1st byte, value at 2nd byte.
- //
- WriteLength = 2;
- Data[0] = SubAddr;
- Status = I2cBus->WriteMultipleByte (
- I2cBus,
- I2cDeviceAddr,
- I2cAddrMode,
- &WriteLength,
- Data
- );
- ASSERT_EFI_ERROR (Status);
-}
-
-//
-// Routines exported by this source module.
-//
-
-/**
- Galileo FabE assert PCI express PERST# signal.
-
-**/
-VOID
-EFIAPI
-GalileoFabEPERSTAssert (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_I2C_HC_PROTOCOL *I2cBus;
-
- Status = gBS->LocateProtocol (&gEfiI2CHcProtocolGuid, NULL, (VOID **) &I2cBus);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Inverter after pin on GalileoGen2 so assert signal with high gpio value.
- //
- Pcal9555GpioSetLevel (I2cBus, PCAL9555_GALILEO_GEN2_7BIT_SLAVE_ADDR, PCAL9555_GALILEO_GEN2_PERST_GPIO, TRUE);
-}
-
-/**
- Galileo FabE de assert PCI express PERST# signal.
-
-**/
-VOID
-EFIAPI
-GalileoFabEPERSTDeAssert (
- VOID
- )
-{
- EFI_STATUS Status;
- EFI_I2C_HC_PROTOCOL *I2cBus;
-
- Status = gBS->LocateProtocol (&gEfiI2CHcProtocolGuid, NULL, (VOID **) &I2cBus);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Inverter after pin on GalileoFabE so de-assert signal with low gpio value.
- //
- Pcal9555GpioSetLevel (I2cBus, PCAL9555_GALILEO_GEN2_7BIT_SLAVE_ADDR, PCAL9555_GALILEO_GEN2_PERST_GPIO, FALSE);
-}
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c index 30ae691..5989dc6 100644 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c +++ b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.c @@ -77,9 +77,7 @@ PlatformPERSTAssert ( IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
- if (PlatformType == GalileoFabE) {
- GalileoFabEPERSTAssert ();
- } else if (PlatformType == GalileoGen2) {
+ if (PlatformType == GalileoGen2) {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
} else {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, FALSE);
@@ -98,9 +96,7 @@ PlatformPERSTDeAssert ( IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
- if (PlatformType == GalileoFabE) {
- GalileoFabEPERSTDeAssert ();
- } else if (PlatformType == GalileoGen2) {
+ if (PlatformType == GalileoGen2) {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_GEN2_PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
} else {
LegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, PCIEXP_PERST_RESUMEWELL_GPIO, TRUE);
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PeiPlatformPcieHelperLib.inf b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf index 5c30749..8380468 100644 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PeiPlatformPcieHelperLib.inf +++ b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf @@ -30,21 +30,21 @@ #
# Module Name:
#
-# PeiPlatformPcieHelperLib.inf
+# PlatformPcieHelperLib.inf
#
# Abstract:
#
-# Library producing Pci Express Helper routines for PEI enviroment.
+# Library producing Pci Express Helper routines.
#
#--*/
[Defines]
INF_VERSION = 0x00010005
- BASE_NAME = PeiPlatformPcieHelperLib
+ BASE_NAME = PlatformPcieHelperLib
FILE_GUID = C153F460-5D8A-4d44-83BB-A8AF5CEF132C
- MODULE_TYPE = PEIM
+ MODULE_TYPE = BASE
VERSION_STRING = 1.0
- LIBRARY_CLASS = PlatformPcieHelperLib|PEIM PEI_CORE SEC
+ LIBRARY_CLASS = PlatformPcieHelperLib
#
# The following information is for reference only and not required by the build tools.
@@ -55,8 +55,7 @@ [Sources]
PlatformPcieHelperLib.c
SocUnit.c
- PlatformPcieHelperPei.c
-
+
[Packages]
MdePkg/MdePkg.dec
MdeModulePkg/MdeModulePkg.dec
diff --git a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperPei.c b/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperPei.c deleted file mode 100644 index e06a203..0000000 --- a/QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperPei.c +++ /dev/null @@ -1,81 +0,0 @@ -/** @file
-
-Copyright (c) 2013 Intel Corporation.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions
-are met:
-
-* Redistributions of source code must retain the above copyright
-notice, this list of conditions and the following disclaimer.
-* Redistributions in binary form must reproduce the above copyright
-notice, this list of conditions and the following disclaimer in
-the documentation and/or other materials provided with the
-distribution.
-* Neither the name of Intel Corporation nor the names of its
-contributors may be used to endorse or promote products derived
-from this software without specific prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-Module Name:
-
- PlatformPcieHelperPei.c
-
-Abstract:
-
- Implementation of Pci Express Helper routines for PEI enviroment.
-
---*/
-
-#include <PiPei.h>
-
-#include "CommonHeader.h"
-
-//
-// Routines defined in other source modules of this component.
-//
-
-//
-// Routines local to this source module.
-//
-
-//
-// Routines exported by this source module.
-//
-
-/**
- Galileo FabE assert PCI express PERST# signal.
-
-**/
-VOID
-EFIAPI
-GalileoFabEPERSTAssert (
- VOID
- )
-{
- // Not implemented for PEI.
-}
-
-/**
- Galileo FabE de assert PCI express PERST# signal.
-
-**/
-VOID
-EFIAPI
-GalileoFabEPERSTDeAssert (
- VOID
- )
-{
- // Not implemented for PEI.
-}
diff --git a/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template b/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template index 92a207d..c24b328 100644 --- a/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template +++ b/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template @@ -439,8 +439,9 @@ <Command.MSFT, Command.INTEL>
"$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
Trim --source-code --convert-hex -o ${d_path}(+)${s_base}.iii ${d_path}(+)${s_base}.i
- "$(ASM16)" /nologo /c /omf $(INC) /Fo$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj ${d_path}(+)${s_base}.iii
- "$(ASMLINK)" $(ASMLINK_FLAGS) $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj,${dst},,,,
+ "$(ASM16)" $(ASM16_FLAGS) $(INC) /Fo$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj ${d_path}(+)${s_base}.iii
+ "$(ASMLINK)" $(ASMLINK_FLAGS) /OUT:$(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.exe $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.obj
+ "$(GENFW)" -o $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.com -b $(OUTPUT_DIR)(+)${s_dir}(+)${s_base}.exe
<Command.GCC>
"$(PP)" $(PP_FLAGS) $(INC) ${src} > ${d_path}(+)${s_base}.i
diff --git a/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template b/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template index ff702d9..24334ba 100755 --- a/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template +++ b/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template @@ -5061,8 +5061,9 @@ RELEASE_ARMLINUXGCC_ARM_CC_FLAGS = $(ARCHCC_FLAGS) $(PLATFORM_FLAGS) DEF(GCC_ARM #################
# ASM 16 linker defintions
#################
-*_*_*_ASMLINK_PATH = DEF(WINDDK_BIN16)\link16.exe
-*_*_*_ASMLINK_FLAGS = /nologo /tiny
+*_*_*_ASM16_FLAGS = /nologo /c /coff
+*_*_*_ASMLINK_PATH = $(DLINK)
+*_*_*_ASMLINK_FLAGS = /NOLOGO /NODEFAULTLIB /IGNORE:4001 /MAP /ALIGN:4 /SECTION:.xdata,D /MACHINE:X86 /DLL /ENTRY:$(IMAGE_ENTRY_POINT) /SUBSYSTEM:EFI_BOOT_SERVICE_DRIVER /SAFESEH:NO /BASE:0 /DRIVER /RELEASE
##################
# VfrCompiler definitions
diff --git a/QuarkPlatformPkg/Override/SecurityPkg/Library/TpmCommLib/TpmAccess.c b/QuarkPlatformPkg/Override/SecurityPkg/Library/TpmCommLib/TpmAccess.c index e1d3ae6..b5643ff 100644 --- a/QuarkPlatformPkg/Override/SecurityPkg/Library/TpmCommLib/TpmAccess.c +++ b/QuarkPlatformPkg/Override/SecurityPkg/Library/TpmCommLib/TpmAccess.c @@ -172,7 +172,8 @@ TpmWriteByte ( );
if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "TpmWriteByte(): I2C Write to TPM address %0x failed\n", TpmAddress));
+ DEBUG ((EFI_D_ERROR, "TpmWriteByte(): I2C Write to TPM address %0x failed (%r)\n", TpmAddress, Status));
+ ASSERT (FALSE); // Writes to TPM should always succeed.
}
mI2CPrevReadTransfer = FALSE;
@@ -184,7 +185,7 @@ TpmWriteByte ( Reads single byte data from TPM specified by MMIO address.
Read access to TPM is via MMIO or I2C (based on platform type).
-
+
Due to stability issues when using I2C combined write/read transfers (with
RESTART) to TPM (specifically read from status register), a single write is
performed followed by single read (with STOP condition in between).
@@ -270,12 +271,11 @@ TpmReadByte ( mI2Cbus,
I2CDeviceAddr,
I2CAddrMode,
- NULL,
&Data
);
if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_INFO, "TpmReadByte(): write to TPM address %0x failed\n", TpmAddress));
+ DEBUG ((EFI_D_INFO, "TpmReadByte(): write to TPM address %0x failed (%r)\n", TpmAddress, Status));
}
mI2CPrevReadTransfer = FALSE;
@@ -288,12 +288,11 @@ TpmReadByte ( mI2Cbus,
I2CDeviceAddr,
I2CAddrMode,
- NULL,
&Data
);
if (EFI_ERROR(Status)) {
- DEBUG ((EFI_D_ERROR, "TpmReadByte(): read from TPM address %0x failed\n", TpmAddress));
+ DEBUG ((EFI_D_INFO, "TpmReadByte(): read from TPM address %0x failed (%r)\n", TpmAddress, Status));
ReadData = 0xFF;
} else {
ReadData = Data[0];
@@ -312,6 +311,16 @@ TpmReadByte ( mI2CPrevReadTransfer = TRUE;
}
+ if (EFI_ERROR(Status)) {
+ //
+ // Only reads to access register allowed to fail.
+ //
+ if (TpmAddress != INFINEON_TPM_ACCESS_0_ADDRESS_DEFAULT) {
+ DEBUG ((EFI_D_ERROR, "TpmReadByte(): read from TPM address %0x failed\n", TpmAddress));
+ ASSERT_EFI_ERROR (Status);
+ }
+ }
+
} else {
//
// Other Quark platforms do not support MMIO access to TPM Device.
diff --git a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c index db76297..7c4ed19 100644 --- a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c +++ b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformConfig.c @@ -59,485 +59,183 @@ Revision History #define SMM_DEFAULT_SMBASE_SIZE_BYTES 0x10000 // Size in bytes of default SMRAM
BOOLEAN mMemCfgDone = FALSE;
-BOOLEAN mPciCfgDone = FALSE;
-BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };
-UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));
UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};
VOID
EFIAPI
-SetLanControllerMacAddr (
- IN CONST UINT8 Bus,
- IN CONST UINT8 Device,
- IN CONST UINT8 Func,
- IN CONST UINT8 *MacAddr
+PlatformInitializeUart0MuxGalileo (
+ VOID
)
/*++
+
Routine Description:
- Set Mac address on chipset ethernet device.
+ This is the routine to initialize UART0 for DBG2 support. The hardware used in this process is a
+ Legacy Bridge (Legacy GPIO), I2C controller, a bi-directional MUX and a Cypress CY8C9540A chip.
Arguments:
- Bus - PCI Bus number of chipset ethernet device.
- Device - PCI Device number of chipset ethernet device.
- Func - PCI Function number of chipset ethernet device.
- MacAddr - MAC Address to set.
-Returns:
None.
---*/
-{
- UINT32 Data32;
- UINT8 PciCmd;
- UINT8 Value8;
- UINT16 PciVid;
- UINT16 PciDid;
- UINT32 Bar0;
- UINT32 Addr;
- UINT32 MacVer;
- volatile UINT8 *Wrote;
-
- PciVid = IohMmPci16(0, Bus, Device, Func, PCI_REG_VID);
- PciDid = IohMmPci16(0, Bus, Device, Func, PCI_REG_DID);
- //
- // Read PCICMD. Bus=0, Dev=0, Func=0, Reg=0x4
- //
- PciCmd = IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD);
-
- if((PciVid == V_IOH_MAC_VENDOR_ID) && (PciDid == V_IOH_MAC_DEVICE_ID)) {
- //
- // Enable MMIO Space(Bit1).
- //
- Value8 = PciCmd | B_IOH_MAC_COMMAND_MSE;
- IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD) = Value8;
-
- //
- // Read BAR0. Bus=0, Dev=0, Func=0, Reg=0x10
- //
- Bar0 = IohMmPci32(0, Bus, Device, Func, R_IOH_MAC_MEMBAR) & B_IOH_MAC_MEMBAR_ADDRESS_MASK;
-
- Addr = Bar0 + R_IOH_MAC_GMAC_REG_8;
- MacVer = *((volatile UINT32 *) (UINTN)(Addr));
-
- DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",
- (UINTN) Bus,
- (UINTN) Device,
- (UINTN) Func,
- (UINTN) MacVer
- ));
-
- //
- // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.
- //
- Addr = Bar0 + R_IOH_MAC_GMAC_REG_17;
- Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
- Wrote = (volatile UINT8 *) (UINTN)(Addr);
- DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",
- (UINTN) Wrote[0],
- (UINTN) Wrote[1],
- (UINTN) Wrote[2],
- (UINTN) Wrote[3]
- ));
-
- //
- // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits
- // and Address Enable (AE) bit.
- //
- Addr = Bar0 + R_IOH_MAC_GMAC_REG_16;
- Data32 =
- ((UINT32) MacAddr[4]) |
- (((UINT32)MacAddr[5]) << 8) |
- B_IOH_MAC_AE;
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
- Wrote = (volatile UINT8 *) (UINTN)(Addr);
-
- DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));
-
- //
- // Return Cmd register to initial value.
- //
- IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD) = PciCmd;
-
- }
-}
-
-EFI_STATUS
-EFIAPI
-PlatformPcal9555Config (
- IN CONST EFI_PLATFORM_TYPE PlatformType
- )
-/*++
-
-Routine Description:
-
-Arguments:
- PlatformType - Set PCAL9555 IO Expander config for this platform.
-
Returns:
- EFI_STATUS
+
+ None.
--*/
{
EFI_STATUS Status;
- UINTN WriteLength;
- UINT8 Data[3];
- EFI_I2C_DEVICE_ADDRESS I2CDeviceAddr;
- EFI_I2C_ADDR_MODE I2CAddrMode;
+ EFI_I2C_DEVICE_ADDRESS I2CSlaveAddress;
+ UINTN Length;
+ UINT8 Buffer[2];
- if (PlatformType != GalileoFabE) {
- return EFI_SUCCESS; // No error if plaform has no Pcal9555 IO Expander.
+ if (PlatformLegacyGpioGetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, GALILEO_DETERMINE_IOEXP_SLA_RESUMEWELL_GPIO)) {
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2HI_7BIT_SLAVE_ADDR;
+ } else {
+ I2CSlaveAddress.I2CDeviceAddress = GALILEO_IOEXP_J2LO_7BIT_SLAVE_ADDR;
}
- I2CDeviceAddr.I2CDeviceAddress = PCAL9555_GALILEO_GEN2_7BIT_SLAVE_ADDR;
- I2CAddrMode = EfiI2CSevenBitAddrMode;
+ //
+ // Set GPIO_SUS<2> as an output, raise voltage to Vdd.
+ //
+ PlatformLegacyGpioSetLevel (R_QNC_GPIO_RGLVL_RESUME_WELL, 2, TRUE);
- WriteLength = 3;
- Data[0] = PCAL9555_REG_CFG_PORT0; // Write to both cfg registers.
- Data[1] = PCAL9555_GALILEO_GEN2_PORT0_CFG;
- Data[2] = PCAL9555_GALILEO_GEN2_PORT1_CFG;
+ //
+ // Select Port 3
+ //
+ Length = 2;
+ Buffer[0] = 0x18; //sub-address
+ Buffer[1] = 0x03; //data
Status = mI2cBus->WriteMultipleByte (
- mI2cBus,
- I2CDeviceAddr,
- I2CAddrMode,
- &WriteLength,
- &Data
- );
+ mI2cBus,
+ I2CSlaveAddress,
+ EfiI2CSevenBitAddrMode,
+ &Length,
+ &Buffer
+ );
ASSERT_EFI_ERROR (Status);
- WriteLength = 3;
- Data[0] = PCAL9555_REG_OUT_PORT0; // Write to both output registers.
- Data[1] = PCAL9555_GALILEO_GEN2_PORT0_DEFAULT_OUT;
- Data[2] = PCAL9555_GALILEO_GEN2_PORT1_DEFAULT_OUT;
+ //
+ // Set "Pin Direction" bit4 and bit5 as outputs
+ //
+ Length = 2;
+ Buffer[0] = 0x1C; //sub-address
+ Buffer[1] = 0xCF; //data
Status = mI2cBus->WriteMultipleByte (
- mI2cBus,
- I2CDeviceAddr,
- I2CAddrMode,
- &WriteLength,
- &Data
- );
+ mI2cBus,
+ I2CSlaveAddress,
+ EfiI2CSevenBitAddrMode,
+ &Length,
+ &Buffer
+ );
ASSERT_EFI_ERROR (Status);
- return EFI_SUCCESS;
-}
-
-VOID
-EFIAPI
-GpioControllerConfig (
- VOID
- )
-/*++
-
-Routine Description:
-
- Perform Gpio controller config.
-
-Arguments:
- None.
-
-Returns:
- None.
-
---*/
-{
- UINT32 IohGpioBase;
- UINT32 Data32;
- UINT8 Value8;
- UINT8 PciCmd;
- UINT16 PciVid;
- UINT16 PciDid;
- UINT32 Addr;
- BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig;
- UINT8 Bus;
- UINT8 Device;
- UINT8 Func;
- EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
-
- PlatformType = &mPrivatePlatformData.PlatformType;
-
- Bus = IOH_I2C_GPIO_BUS_NUMBER;
- Device = IOH_I2C_GPIO_DEVICE_NUMBER;
- Func = IOH_I2C_GPIO_FUNCTION_NUMBER;
-
- PciVid = IohMmPci16(0, Bus, Device, Func, PCI_REG_VID);
- PciDid = IohMmPci16(0, Bus, Device, Func, PCI_REG_DID);
-
- if((PciVid == V_IOH_I2C_GPIO_VENDOR_ID) && (PciDid == V_IOH_I2C_GPIO_DEVICE_ID)) {
- //
- // Read PCICMD. Bus=0, Dev=0, Func=0, Reg=0x4
- //
- PciCmd = IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD);
-
- //
- // Enable Bus Master(Bit2), MMIO Space(Bit1) & I/O Space(Bit0)
- //
- Value8 = PciCmd | 0x7;
- IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD) = Value8;
-
- //
- // Read MEM_BASE. Bus=0, Dev=0, Func=0, Reg=0x14
- //
- IohGpioBase = IohMmPci32(0, Bus, Device, Func, R_IOH_GPIO_MEMBAR);
-
- ASSERT ((UINTN) PlatformType->Type < mBoardGpioControllerConfigTableLen);
- GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType->Type];
- DEBUG ((EFI_D_INFO, "Ioh Gpio Controller Init for PlatType=0x%02x\n", (UINTN) PlatformType->Type));
-
- //
- // IEN- Interrupt Enable Register
- //
- Addr = IohGpioBase + GPIO_INTEN;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->IntEn & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // ISTATUS- Interrupt Status Register
- //
- Addr = IohGpioBase + GPIO_INTSTATUS;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR
- //
- Addr = IohGpioBase + GPIO_SWPORTA_DR;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->PortADR & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input
- //
- Addr = IohGpioBase + GPIO_SWPORTA_DDR;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->PortADir & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked
- //
- Addr = IohGpioBase + GPIO_INTMASK;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->IntMask & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive
- //
- Addr = IohGpioBase + GPIO_INTTYPE_LEVEL;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->IntType & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low
- //
- Addr = IohGpioBase + GPIO_INT_POLARITY;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce
- //
- Addr = IohGpioBase + GPIO_DEBOUNCE;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->Debounce & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- //
- // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)
- //
- Addr = IohGpioBase + GPIO_LS_SYNC;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
- Data32 |= (GpioConfig->LsSync & 0x000FFFFF);
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+ //
+ // Lower GPORT3 bit4 and bit5 to Vss
+ //
+ Length = 2;
+ Buffer[0] = 0x0B; //sub-address
+ Buffer[1] = 0xCF; //data
- }
+ Status = mI2cBus->WriteMultipleByte (
+ mI2cBus,
+ I2CSlaveAddress,
+ EfiI2CSevenBitAddrMode,
+ &Length,
+ &Buffer
+ );
+ ASSERT_EFI_ERROR (Status);
}
VOID
EFIAPI
-PlatformResetDevices (
+PlatformInitializeUart0MuxGalileoGen2 (
VOID
)
/*++
+
Routine Description:
- Performs any platform specific device resets
+ This is the routine to initialize UART0 on GalileoGen2. The hardware used in this process is
+ I2C controller and the configuring the following IO Expander signal.
+
+ EXP1.P1_5 should be configured as an output & driven high.
+ EXP1.P0_0 should be configured as an output & driven high.
+ EXP0.P1_4 should be configured as an output, driven low.
+ EXP1.P0_1 pullup should be disabled.
+ EXP0.P1_5 Pullup should be disabled.
Arguments:
- None.
-Returns:
None.
---*/
-{
- UINT32 IohGpioBase;
- UINT32 Data32;
- UINT8 Value8;
- UINT8 PciCmd;
- UINT16 PciVid;
- UINT16 PciDid;
- UINT32 Addr;
- UINT8 Bus;
- UINT8 Device;
- UINT8 Func;
- EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
-
- PlatformType = &mPrivatePlatformData.PlatformType;
-
- if(PlatformType->Type == (EFI_PLATFORM_TYPE) Galileo) {
-
- DEBUG ((EFI_D_INFO, "Resetting Cypress Expander\n"));
-
- Bus = IOH_I2C_GPIO_BUS_NUMBER;
- Device = IOH_I2C_GPIO_DEVICE_NUMBER;
- Func = IOH_I2C_GPIO_FUNCTION_NUMBER;
-
- PciVid = IohMmPci16(0, Bus, Device, Func, PCI_REG_VID);
- PciDid = IohMmPci16(0, Bus, Device, Func, PCI_REG_DID);
-
- if((PciVid == V_IOH_I2C_GPIO_VENDOR_ID) && (PciDid == V_IOH_I2C_GPIO_DEVICE_ID)) {
- //
- // Read PCICMD. Bus=0, Dev=0, Func=0, Reg=0x4
- //
- PciCmd = IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD);
-
- //
- // Enable Bus Master(Bit2), MMIO Space(Bit1) & I/O Space(Bit0)
- //
- Value8 = PciCmd | 0x7;
- IohMmPci8(0, Bus, Device, Func, PCI_REG_PCICMD) = Value8;
-
- //
- // Read MEM_BASE. Bus=0, Dev=0, Func=0, Reg=0x14
- //
- IohGpioBase = IohMmPci32(0, Bus, Device, Func, R_IOH_GPIO_MEMBAR);
- ASSERT (IohGpioBase != 0xFFFFFFFF);
-
- //
- // Reset Cypress Expander on Galileo Platform
- //
- Addr = IohGpioBase + GPIO_SWPORTA_DR;
- Data32 = *((volatile UINT32 *) (UINTN)(Addr));
- Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4>
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
-
- Data32 = *((volatile UINT32 *) (UINTN)(Addr));
- Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4>
- *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
- }
- }
-}
-
-VOID
-EFIAPI
-PlatformConfigOnPciEnumComplete (
- IN EFI_EVENT Event,
- IN VOID *Context
- )
-/*++
-
-Routine Description:
-
- Function runs in PI-DXE to perform platform specific config when PCI enum
- is complete.
-
-Arguments:
- Event - The event that occured.
- Context - For EFI compatiblity. Not used.
-
Returns:
+
None.
--*/
+
{
- EFI_STATUS Status;
- BOOLEAN SetMacAddr;
- EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
- VOID *PciEnumProt = NULL;
+ //
+ // EXP1.P1_5 should be configured as an output & driven high.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 13, // P1-5.
+ TRUE
+ );
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 13, // P1-5.
+ TRUE
+ );
- PlatformType = &mPrivatePlatformData.PlatformType;
+ //
+ // EXP1.P0_0 should be configured as an output & driven high.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 0, // P0_0.
+ TRUE
+ );
+ PlatformPcal9555GpioSetLevel (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 0, // P0_0.
+ TRUE
+ );
- Status = gBS->LocateProtocol (&gEfiPciEnumerationCompleteProtocolGuid, NULL, &PciEnumProt);
- if (Status != EFI_SUCCESS){
- DEBUG ((DEBUG_INFO, "gEfiPciEnumerationCompleteProtocolGuid triggered but not valid.\n"));
- return;
- }
- if (mPciCfgDone) {
- DEBUG ((DEBUG_INFO, "Platform DXE Pci config already done.\n"));
- return;
- }
+ //
+ // EXP0.P1_4 should be configured as an output, driven low.
+ //
+ PlatformPcal9555GpioSetDir (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 12, // P1-4.
+ FALSE
+ );
+ PlatformPcal9555GpioSetLevel ( // IO Expander 0.
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // P1-4
+ 12,
+ FALSE
+ );
- GpioControllerConfig ();
- PlatformResetDevices ();
-
- //
- // Set chipset MAC0 address if configured.
- //
- SetMacAddr =
- (CompareMem (ChipsetDefaultMac, PlatformType->SysData.IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;
- if (SetMacAddr) {
- if ((*(PlatformType->SysData.IohMac0Address) & BIT0) != 0) {
- DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
- (UINTN) IOH_MAC0_BUS_NUMBER,
- (UINTN) IOH_MAC0_DEVICE_NUMBER,
- (UINTN) IOH_MAC0_FUNCTION_NUMBER
- ));
- ASSERT (FALSE);
- } else {
- SetLanControllerMacAddr (
- IOH_MAC0_BUS_NUMBER,
- IOH_MAC0_DEVICE_NUMBER,
- IOH_MAC0_FUNCTION_NUMBER,
- PlatformType->SysData.IohMac0Address
- );
- }
- } else {
- DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
- (UINTN) IOH_MAC0_BUS_NUMBER,
- (UINTN) IOH_MAC0_DEVICE_NUMBER,
- (UINTN) IOH_MAC0_FUNCTION_NUMBER
- ));
- }
+ //
+ // EXP1.P0_1 pullup should be disabled.
+ //
+ PlatformPcal9555GpioDisablePull (
+ GALILEO_GEN2_IOEXP1_7BIT_SLAVE_ADDR, // IO Expander 1.
+ 1 // P0-1.
+ );
//
- // Set chipset MAC1 address if configured.
- //
- SetMacAddr =
- (CompareMem (ChipsetDefaultMac, PlatformType->SysData.IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;
- if (SetMacAddr) {
- if ((*(PlatformType->SysData.IohMac1Address) & BIT0) != 0) {
- DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
- (UINTN) IOH_MAC1_BUS_NUMBER,
- (UINTN) IOH_MAC1_DEVICE_NUMBER,
- (UINTN) IOH_MAC1_FUNCTION_NUMBER
- ));
- ASSERT (FALSE);
- } else {
- SetLanControllerMacAddr (
- IOH_MAC1_BUS_NUMBER,
- IOH_MAC1_DEVICE_NUMBER,
- IOH_MAC1_FUNCTION_NUMBER,
- PlatformType->SysData.IohMac1Address
- );
- }
- } else {
- DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
- (UINTN) IOH_MAC1_BUS_NUMBER,
- (UINTN) IOH_MAC1_DEVICE_NUMBER,
- (UINTN) IOH_MAC1_FUNCTION_NUMBER
- ));
- }
- mPciCfgDone = TRUE;
+ // EXP0.P1_5 Pullup should be disabled.
+ //
+ PlatformPcal9555GpioDisablePull (
+ GALILEO_GEN2_IOEXP0_7BIT_SLAVE_ADDR, // IO Expander 0.
+ 13 // P1-5.
+ );
}
VOID
@@ -596,52 +294,54 @@ Returns: DEBUG ((EFI_D_INFO,"Locking HMBOUND at: = 0x%8x\n",NewValue));
QNCPortWrite (QUARK_NC_HOST_BRIDGE_SB_PORT_ID, QUARK_NC_HOST_BRIDGE_HMBOUND_REG, (NewValue | HMBOUND_LOCK));
- //
- // Lock IMR5 now that HMBOUND is locked (legacy S3 region)
- //
- NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);
- NewValue |= IMR_LOCK;
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
+ if(FeaturePcdGet (PcdEnableSecureLock)) {
+ //
+ // Lock IMR5 now that HMBOUND is locked (legacy S3 region)
+ //
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL);
+ NewValue |= IMR_LOCK;
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR5+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
- //
- // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)
- //
- NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);
- NewValue |= IMR_LOCK;
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
+ //
+ // Lock IMR6 now that HMBOUND is locked (ACPI Reclaim/ACPI/Runtime services/Reserved)
+ //
+ NewValue = QNCPortRead (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL);
+ NewValue |= IMR_LOCK;
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_IMR6+QUARK_NC_MEMORY_MANAGER_IMRXL, NewValue);
- //
- // Disable IMR2 memory protection (RMU Main Binary)
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR2,
- (UINT32)(IMRL_RESET & ~IMR_EN),
- (UINT32)IMRH_RESET,
- (UINT32)IMRX_ALL_ACCESS,
- (UINT32)IMRX_ALL_ACCESS
- );
+ //
+ // Disable IMR2 memory protection (RMU Main Binary)
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR2,
+ (UINT32)(IMRL_RESET & ~IMR_EN),
+ (UINT32)IMRH_RESET,
+ (UINT32)IMRX_ALL_ACCESS,
+ (UINT32)IMRX_ALL_ACCESS
+ );
- //
- // Disable IMR3 memory protection (Default SMRAM)
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR3,
- (UINT32)(IMRL_RESET & ~IMR_EN),
- (UINT32)IMRH_RESET,
- (UINT32)IMRX_ALL_ACCESS,
- (UINT32)IMRX_ALL_ACCESS
- );
+ //
+ // Disable IMR3 memory protection (Default SMRAM)
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR3,
+ (UINT32)(IMRL_RESET & ~IMR_EN),
+ (UINT32)IMRH_RESET,
+ (UINT32)IMRX_ALL_ACCESS,
+ (UINT32)IMRX_ALL_ACCESS
+ );
- //
- // Disable IMR4 memory protection (eSRAM).
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR4,
- (UINT32)(IMRL_RESET & ~IMR_EN),
- (UINT32)IMRH_RESET,
- (UINT32)IMRX_ALL_ACCESS,
- (UINT32)IMRX_ALL_ACCESS
- );
+ //
+ // Disable IMR4 memory protection (eSRAM).
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR4,
+ (UINT32)(IMRL_RESET & ~IMR_EN),
+ (UINT32)IMRH_RESET,
+ (UINT32)IMRX_ALL_ACCESS,
+ (UINT32)IMRX_ALL_ACCESS
+ );
+ }
//
// RTC:28208 - System hang/crash when entering probe mode(ITP) when relocating SMBASE
@@ -654,7 +354,7 @@ Returns: CpuArchProtocol,
(EFI_PHYSICAL_ADDRESS) SMM_DEFAULT_SMBASE,
SMM_DEFAULT_SMBASE_SIZE_BYTES,
- EFI_MEMORY_WB
+ EFI_MEMORY_WB
);
mMemCfgDone = TRUE;
@@ -684,6 +384,12 @@ Returns: {
EFI_STATUS Status;
VOID *SpiReadyProt = NULL;
+ EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
+ EFI_BOOT_MODE BootMode;
+
+ BootMode = GetBootModeHob ();
+
+ PlatformType = &mPrivatePlatformData.PlatformType;
Status = gBS->LocateProtocol (&gEfiSmmSpiReadyProtocolGuid, NULL, &SpiReadyProt);
if (Status != EFI_SUCCESS){
@@ -696,6 +402,39 @@ Returns: //
PlatformFlashLockPolicy (FALSE);
+ //
+ // Configurations and checks to be done when DXE tracing available.
+ //
+
+ //
+ // Platform specific Signal routing.
+ //
+
+ //
+ // Skip any signal not needed for recovery and flash update.
+ //
+ if (BootMode != BOOT_ON_FLASH_UPDATE && BootMode != BOOT_IN_RECOVERY_MODE) {
+
+ //
+ // Galileo Platform UART0 support.
+ //
+ if (PlatformType->Type == Galileo) {
+ //
+ // Use MUX to connect out UART0 pins.
+ //
+ PlatformInitializeUart0MuxGalileo ();
+ }
+
+ //
+ // GalileoGen2 Platform UART0 support.
+ //
+ if (PlatformType->Type == GalileoGen2) {
+ //
+ // Use route out UART0 pins.
+ //
+ PlatformInitializeUart0MuxGalileoGen2 ();
+ }
+ }
}
EFI_STATUS
@@ -716,10 +455,8 @@ Returns: --*/
{
EFI_EVENT EventSmmCfg;
- EFI_EVENT EventPci;
EFI_EVENT EventSpiReady;
VOID *RegistrationSmmCfg;
- VOID *RegistrationPci;
VOID *RegistrationSpiReady;
//
@@ -735,19 +472,6 @@ Returns: ASSERT (EventSmmCfg != NULL);
//
- // Schedule callback to setup IOH GPIO controller registers when PCI enum
- // complete (MEMBASE assigned).
- //
- EventPci = EfiCreateProtocolNotifyEvent (
- &gEfiPciEnumerationCompleteProtocolGuid,
- TPL_CALLBACK,
- PlatformConfigOnPciEnumComplete,
- NULL,
- &RegistrationPci
- );
- ASSERT (EventPci != NULL);
-
- //
// Schedule callback to setup SPI Flash Policy when SPI interface ready.
//
EventSpiReady = EfiCreateProtocolNotifyEvent (
diff --git a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c index 55e966f..37a1d2d 100644 --- a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c +++ b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.c @@ -180,7 +180,7 @@ Returns: );
mPrivatePlatformData.PlatformType.TypeStringPtr =
- PlatformTypeString ((UINT16) mPrivatePlatformData.PlatformType.Type);
+ PlatformTypeString ((EFI_PLATFORM_TYPE) mPrivatePlatformData.PlatformType.Type);
GetQncName();
GetIioName();
@@ -261,34 +261,19 @@ Returns: --*/
{
EFI_STATUS Status;
+ EFI_PLATFORM_TYPE_PROTOCOL *PlatformType;
//
// Install data protocols whose contents are derived from Hobs.
//
InstallProtocolsFromHobs ();
+ PlatformType = &mPrivatePlatformData.PlatformType;
//
- // GalileoGen2 Platform support.
+ // Locate I2C host controller driver.
//
- if (mPrivatePlatformData.PlatformType.Type == GalileoFabE) {
- //
- // Locate I2C host controller driver.
- //
- Status = gBS->LocateProtocol (&gEfiI2CHcProtocolGuid, NULL, (VOID **) &mI2cBus);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Set Pcal9555 IO Expander config.
- //
- Status = PlatformPcal9555Config ((EFI_PLATFORM_TYPE) mPrivatePlatformData.PlatformType.Type);
- ASSERT_EFI_ERROR (Status);
-
- //
- // Do Early PCIe init if GalileoFabE Platform.
- //
- Status = PlatformPciExpressEarlyInit ((EFI_PLATFORM_TYPE) mPrivatePlatformData.PlatformType.Type);
- ASSERT_EFI_ERROR (Status);
- }
+ Status = gBS->LocateProtocol (&gEfiI2CHcProtocolGuid, NULL, (VOID **) &mI2cBus);
+ ASSERT_EFI_ERROR (Status);
//
// Initialize Firmware Volume security.
@@ -302,6 +287,12 @@ Returns: //
CreateConfigEvents ();
+ //
+ // Init Platform LEDs.
+ //
+ Status = PlatformLedInit ((EFI_PLATFORM_TYPE) PlatformType->Type);
+ ASSERT_EFI_ERROR (Status);
+
return EFI_SUCCESS;
}
diff --git a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf index 7fb3132..1061019 100644 --- a/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf +++ b/QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf @@ -89,6 +89,9 @@ gEfiSmmSpiReadyProtocolGuid
gEfiI2CHcProtocolGuid
+[FeaturePcd]
+ gQuarkPlatformTokenSpaceGuid.PcdEnableSecureLock
+
[FixedPcd]
gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageBase
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c b/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c index 32abe62..9def18f 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c +++ b/QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.c @@ -119,8 +119,8 @@ UpdateDynamicPcds ( UINT32 SecHdrSize;
UINT32 Temp32;
UINT32 SramImageIndex;
- QUARK_EDKII_STAGE1_HEADER *SramEdk2ImageHeader;
- QUARK_EDKII_STAGE1_HEADER *FlashEntryEdk2ImageHeader;
+ QUARK_EDKII_STAGE1_HEADER *SramEdk2ImageHeader;
+ QUARK_EDKII_STAGE1_HEADER *FlashEntryEdk2ImageHeader;
MFH_LIB_FINDCONTEXT MfhFindContext;
UINT32 Stage1Base;
UINT32 Stage1Len;
@@ -128,76 +128,77 @@ UpdateDynamicPcds ( SecHdrSize = FixedPcdGet32 (PcdFvSecurityHeaderSize);
//
- // Setup stage1 base and length PCDs.
- //
-
- //
- // Assume running from fixed recovery area if no match found in MFH.
+ // Init stage1 locals with fixed recovery image constants.
//
Stage1Base = FixedPcdGet32 (PcdFlashFvFixedStage1AreaBase);
Stage1Len = FixedPcdGet32 (PcdFlashFvFixedStage1AreaSize);
//
- // If found in SPI MFH override Stage1Base & Len with MFH values.
+ // Setup PCDs determined from MFH if not running in recovery.
//
- SramEdk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) (FixedPcdGet32 (PcdEsramStage1Base) + SecHdrSize);
- SramImageIndex = (UINT32) SramEdk2ImageHeader->ImageIndex;
- FlashItem = MfhLibFindFirstWithFilter (
- MFH_FIND_ALL_STAGE1_FILTER,
- FALSE,
- &MfhFindContext
- );
- while (FlashItem != NULL) {
- FlashEntryEdk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) (FlashItem->FlashAddress + SecHdrSize);
- if (SramImageIndex == FlashEntryEdk2ImageHeader->ImageIndex) {
- Stage1Base = FlashItem->FlashAddress;
- Stage1Len = FlashItem->LengthBytes;
- break;
- }
- FlashItem = MfhLibFindNextWithFilter (
+ if (!PlatformIsBootWithRecoveryStage1()) {
+ //
+ // If found in SPI MFH override Stage1Base & Len with MFH values.
+ //
+ SramEdk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) (FixedPcdGet32 (PcdEsramStage1Base) + SecHdrSize);
+ SramImageIndex = (UINT32) SramEdk2ImageHeader->ImageIndex;
+ FlashItem = MfhLibFindFirstWithFilter (
MFH_FIND_ALL_STAGE1_FILTER,
+ FALSE,
&MfhFindContext
);
- }
+ while (FlashItem != NULL) {
+ FlashEntryEdk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) (FlashItem->FlashAddress + SecHdrSize);
+ if (SramImageIndex == FlashEntryEdk2ImageHeader->ImageIndex) {
+ Stage1Base = FlashItem->FlashAddress;
+ Stage1Len = FlashItem->LengthBytes;
+ break;
+ }
+ FlashItem = MfhLibFindNextWithFilter (
+ MFH_FIND_ALL_STAGE1_FILTER,
+ &MfhFindContext
+ );
+ }
- Temp32 = PcdSet32 (PcdFlashFvRecoveryBase, (Stage1Base + SecHdrSize));
- ASSERT (Temp32 == (Stage1Base + SecHdrSize));
+ Temp32 = PcdSet32 (PcdFlashFvRecoveryBase, (Stage1Base + SecHdrSize));
+ ASSERT (Temp32 == (Stage1Base + SecHdrSize));
- Temp32 = PcdSet32 (PcdFlashFvRecoverySize, (Stage1Len - SecHdrSize));
- ASSERT (Temp32 == (Stage1Len - SecHdrSize));
+ Temp32 = PcdSet32 (PcdFlashFvRecoverySize, (Stage1Len - SecHdrSize));
+ ASSERT (Temp32 == (Stage1Len - SecHdrSize));
- //
- // Set FvMain base and length PCDs from SPI MFH database.
- //
- FlashItem = MfhLibFindFirstWithFilter (
- MFH_FIND_ALL_STAGE2_FILTER,
- FALSE,
- &FindContext
- );
-
- if (FlashItem != NULL) {
- Temp32 = PcdSet32 (PcdFlashFvMainBase, (FlashItem->FlashAddress + SecHdrSize));
- ASSERT (Temp32 == (FlashItem->FlashAddress + SecHdrSize));
-
- Temp32 = PcdSet32 (PcdFlashFvMainSize, (FlashItem->LengthBytes - SecHdrSize));
- ASSERT (Temp32 == (FlashItem->LengthBytes - SecHdrSize));
- }
+ //
+ // Set FvMain base and length PCDs from SPI MFH database.
+ //
+ FlashItem = MfhLibFindFirstWithFilter (
+ MFH_FIND_ALL_STAGE2_FILTER,
+ FALSE,
+ &FindContext
+ );
- //
- // Set Payload base and length PCDs from SPI MFH database.
- //
- FlashItem = MfhLibFindFirstWithFilter (
- MFH_FIND_ALL_BOOTLOADER_FILTER,
- FALSE,
- &FindContext
- );
-
- if (FlashItem != NULL) {
- Temp32 = PcdSet32 (PcdFlashFvPayloadBase, (FlashItem->FlashAddress + SecHdrSize));
- ASSERT (Temp32 == (FlashItem->FlashAddress + SecHdrSize));
-
- Temp32 = PcdSet32 (PcdFlashFvPayloadSize, FlashItem->LengthBytes);
- ASSERT (Temp32 == FlashItem->LengthBytes);
+ if (FlashItem != NULL) {
+ Temp32 = PcdSet32 (PcdFlashFvMainBase, (FlashItem->FlashAddress + SecHdrSize));
+ ASSERT (Temp32 == (FlashItem->FlashAddress + SecHdrSize));
+
+ Temp32 = PcdSet32 (PcdFlashFvMainSize, (FlashItem->LengthBytes - SecHdrSize));
+ ASSERT (Temp32 == (FlashItem->LengthBytes - SecHdrSize));
+ }
+
+ //
+ // Set Payload base and length PCDs from SPI MFH database.
+ //
+ FlashItem = MfhLibFindFirstWithFilter (
+ MFH_FIND_ALL_BOOTLOADER_FILTER,
+ FALSE,
+ &FindContext
+ );
+
+ if (FlashItem != NULL) {
+ Temp32 = PcdSet32 (PcdFlashFvPayloadBase, (FlashItem->FlashAddress + SecHdrSize));
+ ASSERT (Temp32 == (FlashItem->FlashAddress + SecHdrSize));
+
+ Temp32 = PcdSet32 (PcdFlashFvPayloadSize, FlashItem->LengthBytes);
+ ASSERT (Temp32 == FlashItem->LengthBytes);
+ }
}
}
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.c b/QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.c index b42f058..cccd4db 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.c +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.c @@ -141,13 +141,88 @@ Returns: }
EFI_STATUS
+CheckAndReadCriticalData (
+ IN PDAT_AREA *Area,
+ OUT UINT16 *TypePtr,
+ OUT PDAT_MRC_ITEM *MrcConfig OPTIONAL
+ )
+/*++
+Routine Description:
+
+ Check and read critical platfrom data items.
+
+Arguments:
+
+ Area - Pointer to system platform data area.
+ TypePtr - Store selected platform type at this address.
+ MrcConfig - Store mrc config for platform type at this address.
+
+Returns:
+
+ EFI_SUCCESS - User selected valid file.
+ EFI_NOT_FOUND - Critical item not found in area.
+ EFI_UNSUPPORTED - Unsupported platform type.
+ Other - Unexpected error.
+ TypePtr - Read platform type into this location.
+ MrcConfig - Optionally read mrc config into this buffer.
+
+--*/
+{
+ PDAT_ITEM *Item;
+ PDAT_MRC_ITEM *MrcItemData;
+ EFI_STATUS Status;
+
+ *TypePtr = (EFI_PLATFORM_TYPE) 0;
+ Item = PDatLibFindItem (Area, PDAT_ITEM_ID_PLATFORM_ID, FALSE, TypePtr);
+ if (Item == NULL) {
+ *TypePtr = TypeUnknown;
+ DEBUG ((EFI_D_ERROR, "SPI PDR missing does not contain a Platform ID item!!!!\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ if (!PlatformIsSupportedPlatformType ((EFI_PLATFORM_TYPE) *TypePtr)) {
+ //
+ // Reading from SPI PDR Failed or a unknown platform identified
+ //
+ DEBUG ((EFI_D_WARN, "SPI PDR reports Platform ID as %x. This ID is not supported.\n", *TypePtr));
+ *TypePtr = TypeUnknown;
+ return EFI_UNSUPPORTED;
+ }
+
+ Item = PDatLibFindItem (Area, PDAT_ITEM_ID_MRC_VARS, TRUE, NULL);
+ if (Item == NULL) {
+ DEBUG ((EFI_D_ERROR, "Platform Info: Mrc Vars not found in Platform Data!!!!!\n"));
+ return EFI_NOT_FOUND;
+ }
+
+ Status = CheckMrcParams (*TypePtr, Item);
+ if (!EFI_ERROR (Status) && MrcConfig != NULL) {
+ MrcItemData = (PDAT_MRC_ITEM *) Item->Data;
+
+ CopyMem (
+ (VOID *) MrcConfig,
+ (VOID *) MrcItemData,
+ sizeof (PDAT_MRC_ITEM)
+ );
+
+ DEBUG (
+ (EFI_D_INFO,
+ "Platform Info: Platform Data Mrc Vars found: length %d version = %d\n",
+ (UINTN) Item->Header.Length,
+ (UINTN) Item->Header.Version
+ ));
+ }
+
+ return Status;
+}
+
+EFI_STATUS
FindAndCheckPlatformDataFile (
IN CONST EFI_GUID *FileNameGuid,
OUT PDAT_AREA **AreaPtr,
OUT UINTN *AreaSize,
- OUT PDAT_ITEM **TypeItemPtr,
- OUT PDAT_ITEM **MrcItemPtr,
- OUT UINT16 *TypePtr
+ OUT UINT16 *TypePtr,
+ OUT PDAT_MRC_ITEM *MrcConfig OPTIONAL
)
/*++
Routine Description:
@@ -159,9 +234,8 @@ Arguments: FileNameGuid - Platform data file to find.
AreaPtr - Pointer to be pointed to platform data area.
AreaSize - Update with size of platform data area.
- TypeItemPtr - Update with address of platform type item.
- MrcItemPtr - Update with address of mrc config item.
- TypePtr - Store platform type at this address.
+ TypePtr - Read platform type into this location.
+ MrcConfig - Optionally read mrc config into this buffer.
Returns:
@@ -170,9 +244,8 @@ Returns: EFI_INVALID_PARAMETER - File found but data in file invalid.
AreaPtr - Pointing to platform data area in file.
AreaSize - Updated with size of platform data area.
- TypeItemPtr - Updated with address of platform type item.
- MrcItemPtr - Updated with address of mrc config item.
TypePtr - Updated with platform type.
+ MrcConfig - Optionally read mrc config into this buffer.
--*/
{
@@ -187,22 +260,7 @@ Returns: DEBUG ((EFI_D_INFO, "Platform Info: File %g has bad PDAT area %r\n", FileNameGuid, Status));
return EFI_INVALID_PARAMETER;
}
- *TypeItemPtr = PDatLibFindItem (*AreaPtr, PDAT_ITEM_ID_PLATFORM_ID, FALSE, TypePtr);
- if (*TypeItemPtr == NULL) {
- DEBUG ((EFI_D_INFO, "Platform Info: File %g has no PID item\n", FileNameGuid));
- return EFI_INVALID_PARAMETER;
- }
- if ((*TypePtr > TypeUnknown) && (*TypePtr < TypePlatformMax)) {
- *MrcItemPtr = PDatLibFindItem (*AreaPtr, PDAT_ITEM_ID_MRC_VARS, FALSE, NULL);
- if (*MrcItemPtr == NULL) {
- DEBUG ((EFI_D_INFO, "Platform Info: File %g has no MRCCFG item\n", FileNameGuid));
- return EFI_INVALID_PARAMETER;
- }
- } else {
- DEBUG ((EFI_D_INFO, "Platform Info: Invalid platform type %d\n", (UINTN) *TypePtr));
- return EFI_INVALID_PARAMETER;
- }
- return CheckMrcParams (*TypePtr, *MrcItemPtr);
+ return CheckAndReadCriticalData (*AreaPtr, TypePtr, MrcConfig);
}
VOID
@@ -228,8 +286,6 @@ Returns: EFI_STATUS Status;
PDAT_AREA *CurrArea;
UINTN CurrAreaSize;
- PDAT_ITEM *CurrTypeItem;
- PDAT_ITEM *CurrMrcItem;
UINT16 CurrType;
CHAR8 KeyStrForIndex [4];
@@ -243,9 +299,8 @@ Returns: &mPDatFileNameTable[Index],
&CurrArea,
&CurrAreaSize,
- &CurrTypeItem,
- &CurrMrcItem,
- &CurrType
+ &CurrType,
+ NULL
);
if (EFI_ERROR (Status)) {
@@ -256,7 +311,7 @@ Returns: (EFI_D_ERROR,
"Type %a for '%s' [PID %d]\n",
KeyStrForIndex,
- PlatformTypeString (CurrType),
+ PlatformTypeString ((EFI_PLATFORM_TYPE) CurrType),
(UINTN) CurrType
));
}
@@ -296,8 +351,6 @@ Returns: CHAR8 Key;
EFI_STATUS Status;
UINTN AreaSize;
- PDAT_ITEM *TypeItem;
- PDAT_ITEM *MrcItem;
//
// Return error if no files to search for.
@@ -330,12 +383,10 @@ Returns: &mPDatFileNameTable[Selected],
AreaPtr,
&AreaSize,
- &TypeItem,
- &MrcItem,
- TypePtr
+ TypePtr,
+ MrcConfig
);
if (!EFI_ERROR (Status)) {
-
//
// Valid selection return to caller.
//
@@ -343,17 +394,6 @@ Returns: PlatformDataFile,
&mPDatFileNameTable[Selected]
);
- CopyMem (
- (VOID *) MrcConfig,
- (VOID *) MrcItem->Data,
- sizeof (PDAT_MRC_ITEM)
- );
- // Use EFI_D_ERROR so user on release builds knows data found.
- DEBUG ((EFI_D_ERROR, "Platform Info: Type = %x\n", (UINTN) *TypePtr));
- DEBUG ((EFI_D_ERROR, "Platform Info: Platform Data Mrc Vars found: length %d version = %d\n",
- (UINTN) MrcItem->Header.Length,
- (UINTN) MrcItem->Header.Version
- ));
break;
}
}
@@ -414,8 +454,7 @@ Returns: PDAT_ITEM *Item;
EFI_STATUS Status;
PDAT_AREA *Area;
- PDAT_MRC_ITEM *MrcItemData;
- QUARK_EDKII_STAGE1_HEADER *Edk2ImageHeader;
+ BOOLEAN RecoveryStage1;
//
// Set default values for information derived from platform data area.
@@ -423,96 +462,66 @@ Returns: PlatformInfoHob->Type = (EFI_PLATFORM_TYPE) TypeUnknown;
SetMem (PlatformInfoHob->SysData.IohMac0Address, sizeof(PlatformInfoHob->SysData.IohMac0Address), 0xff);
SetMem (PlatformInfoHob->SysData.IohMac1Address, sizeof(PlatformInfoHob->SysData.IohMac1Address), 0xff);
+ RecoveryStage1 = PlatformIsBootWithRecoveryStage1();
//
- // Return error if platform data CRC error, size error or other unexpected error.
- // For Recovery boot => User selects 'safe embedded' platform data
+ // Get Spi flash platform data area.
//
- Edk2ImageHeader = (QUARK_EDKII_STAGE1_HEADER *) (FixedPcdGet32 (PcdEsramStage1Base) + FixedPcdGet32 (PcdFvSecurityHeaderSize));
- switch ((UINT8)Edk2ImageHeader->ImageIndex & QUARK_STAGE1_IMAGE_TYPE_MASK) {
- case QUARK_STAGE1_RECOVERY_IMAGE_TYPE:
- //
- // Recovery Boot
- //
- Status = UserSelectPlatformDataFile (
- &Area,
- &PlatformInfoHob->BiosPlatformDataFile,
- &PlatformInfoHob->Type,
- &PlatformInfoHob->MemData.MemMrcConfig
- );
- if (EFI_ERROR (Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
+ Status = PDatLibGetSystemAreaPointer (TRUE, &Area);
+ if (EFI_ERROR (Status)) {
+ if (Status == EFI_NOT_FOUND) {
+ DEBUG ((EFI_D_ERROR, "System Platform Data Area Signature not found.\n"));
+ } else if (Status == EFI_CRC_ERROR) {
+ DEBUG ((EFI_D_ERROR, "System Platform Data Area CRC Error.\n"));
+ } else if (Status == EFI_BAD_BUFFER_SIZE) {
+ DEBUG ((EFI_D_ERROR, "System Platform Data Area length too large for this platform.\n"));
+ } else {
+ DEBUG ((EFI_D_ERROR, "System Platform Data Area get failed error = %r.\n", Status));
}
- break;
- default:
- //
- // Normal Boot
- //
- Status = PDatLibGetSystemAreaPointer (TRUE, &Area);
- if (EFI_ERROR (Status)) {
- if (Status == EFI_NOT_FOUND) {
- DEBUG ((EFI_D_ERROR, "System Platform Data Area Signature not found.\n"));
- } else if (Status == EFI_CRC_ERROR) {
- DEBUG ((EFI_D_ERROR, "System Platform Data Area CRC Error.\n"));
- } else if (Status == EFI_BAD_BUFFER_SIZE) {
- DEBUG ((EFI_D_ERROR, "System Platform Data Area length too large for this platform.\n"));
- } else {
- DEBUG ((EFI_D_ERROR, "System Platform Data Area get failed error = %r.\n", Status));
- }
- ASSERT (FeaturePcdGet (PcdEnableSecureLock) == FALSE);
- Status = UserSelectPlatformDataFile (
- &Area,
- &PlatformInfoHob->BiosPlatformDataFile,
- &PlatformInfoHob->Type,
- &PlatformInfoHob->MemData.MemMrcConfig
- );
- if (EFI_ERROR (Status)) {
- ASSERT_EFI_ERROR (Status);
- return Status;
- }
- } else {
- PlatformInfoHob->Type = (EFI_PLATFORM_TYPE) 0;
- Item = PDatLibFindItem (Area, PDAT_ITEM_ID_PLATFORM_ID, FALSE, &PlatformInfoHob->Type);
- if (Item == NULL) {
- PlatformInfoHob->Type = TypeUnknown;
- DEBUG ((EFI_D_ERROR, "SPI PDR missing does not contain a Platform ID item!!!!\n"));
- ASSERT (FALSE);
- }
+ if (FeaturePcdGet (PcdEnableSecureLock)) {
+ //
+ // On secure boot only recovery stage1 can continue if bad platform
+ // data area.
+ //
+ ASSERT (RecoveryStage1);
+ }
- if ((PlatformInfoHob->Type > TypeUnknown) && (PlatformInfoHob->Type < TypePlatformMax)) {
- //
- // Valid Platform Identified
- //
- DEBUG ((EFI_D_INFO, "Platform Info: Type = %x\n", (UINTN) PlatformInfoHob->Type));
- } else {
- //
- // Reading from SPI PDR Failed or a unknown platform identified
- //
- DEBUG ((EFI_D_WARN, "SPI PDR reports Platform ID as %x. This is unknown ID.\n", PlatformInfoHob->Type));
- PlatformInfoHob->Type = TypeUnknown;
- ASSERT (FALSE);
- }
- Item = PDatLibFindItem (Area, PDAT_ITEM_ID_MRC_VARS, TRUE, NULL);
- if (Item == NULL) {
- DEBUG ((EFI_D_ERROR, "Platform Info: Mrc Vars not found in Platform Data!!!!!\n"));
- ASSERT (FALSE);
- } else {
- Status = CheckMrcParams (PlatformInfoHob->Type, Item);
- ASSERT_EFI_ERROR (Status);
- MrcItemData = (PDAT_MRC_ITEM *) Item->Data;
- CopyMem ((VOID *) &PlatformInfoHob->MemData.MemMrcConfig, (VOID *) MrcItemData, sizeof (PlatformInfoHob->MemData.MemMrcConfig));
- DEBUG ((EFI_D_INFO, "Platform Info: Platform Data Mrc Vars found: length %d version = %d\n",
- (UINTN) Item->Header.Length,
- (UINTN) Item->Header.Version
- ));
- }
+ } else {
+ Status = CheckAndReadCriticalData (
+ Area,
+ &PlatformInfoHob->Type,
+ &PlatformInfoHob->MemData.MemMrcConfig
+ );
+
+ if (EFI_ERROR(Status)) {
+ //
+ // Only recovery image can continue if there is a problem with critical
+ // data items within the Spi flash Platform data area.
+ //
+ ASSERT (RecoveryStage1);
}
- break;
}
//
+ // If problem with system data area then loop until user selects
+ // a valid built in platform data file.
+ //
+ while (EFI_ERROR(Status)) {
+ Status = UserSelectPlatformDataFile (
+ &Area,
+ &PlatformInfoHob->BiosPlatformDataFile,
+ &PlatformInfoHob->Type,
+ &PlatformInfoHob->MemData.MemMrcConfig
+ );
+ if (EFI_ERROR (Status)) {
+ DEBUG ((EFI_D_ERROR, "User selection of platform data failed = %r. TRY AGAIN\n", Status));
+ }
+ }
+
+ DEBUG ((EFI_D_INFO, "Platform Info: Type = %x\n", (UINTN) PlatformInfoHob->Type));
+
+ //
// Read mac addresses configured in platform data flash area.
//
Item = PDatLibFindItem (Area, PDAT_ITEM_ID_MAC0, FALSE, PlatformInfoHob->SysData.IohMac0Address);
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c index 1b3df7b..b4465fb 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/BootMode.c @@ -181,7 +181,13 @@ UpdateBootMode ( EFI_BOOT_MODE NewBootMode;
PEI_CAPSULE_PPI *Capsule;
CHAR8 UserSelection;
-
+ UINT32 Straps32;
+
+ //
+ // Read Straps. Used later if recovery boot.
+ //
+ Straps32 = QNCAltPortRead (QUARK_SCSS_SOC_UNIT_SB_PORT_ID, QUARK_SCSS_SOC_UNIT_STPDDRCFG);
+
//
// Check if we need to boot in recovery mode
//
@@ -252,22 +258,31 @@ UpdateBootMode ( // continue with the recovery. Also give the user a chance to retry a normal boot.
//
if (NewBootMode == BOOT_IN_RECOVERY_MODE) {
- DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
- DEBUG ((EFI_D_ERROR, "***** ERROR: System boot failure!!!!!!! *****\n"));
- DEBUG ((EFI_D_ERROR, "***** REMOVE ANY FORCE RECOVERY JUMPERS BEFORE PROCEEDING! *****\n"));
- DEBUG ((EFI_D_ERROR, "***** - Press 'R' if you wish to force system recovery *****\n"));
- DEBUG ((EFI_D_ERROR, "***** (connect USB key with recovery module first) *****\n"));
- DEBUG ((EFI_D_ERROR, "***** - Press any other key to attempt another boot *****\n"));
- DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
- UserSelection = PlatformDebugPortGetChar8 ();
- if ((UserSelection != 'R') && (UserSelection != 'r')) {
- DEBUG ((EFI_D_ERROR, "New boot attempt selected........\n"));
- //
- // Initialte the cold reset
- //
- ResetCold ();
+ if ((Straps32 & B_STPDDRCFG_FORCE_RECOVERY) == 0) {
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ DEBUG ((EFI_D_ERROR, "***** Force Recovery Jumper Detected. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** Attempting auto recovery of system flash. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** Expecting USB key with recovery module connected. *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** PLEASE REMOVE FORCE RECOVERY JUMPER. *****\n"));
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ } else {
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+ DEBUG ((EFI_D_ERROR, "***** ERROR: System boot failure!!!!!!! *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** - Press 'R' if you wish to force system recovery *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** (connect USB key with recovery module first) *****\n"));
+ DEBUG ((EFI_D_ERROR, "***** - Press any other key to attempt another boot *****\n"));
+ DEBUG ((EFI_D_ERROR, "*****************************************************************\n"));
+
+ UserSelection = PlatformDebugPortGetChar8 ();
+ if ((UserSelection != 'R') && (UserSelection != 'r')) {
+ DEBUG ((EFI_D_ERROR, "New boot attempt selected........\n"));
+ //
+ // Initialte the cold reset
+ //
+ ResetCold ();
+ }
+ DEBUG ((EFI_D_ERROR, "Recovery boot selected..........\n"));
}
- DEBUG ((EFI_D_ERROR, "Recovery boot selected..........\n"));
}
return EFI_SUCCESS;
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c index 0c25942..fd50783 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/MrcWrapper.c @@ -28,7 +28,6 @@ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
Module Name:
MrcWrapper.c
@@ -40,7 +39,6 @@ Abstract: --*/
-
#include "CommonHeader.h"
#include "MrcWrapper.h"
#include "IioUniversalData.h"
@@ -52,8 +50,8 @@ Abstract: #include <Library/PlatformDataLib.h>
//
-// ------------------------ TSEG Base
-// ...............
+// ------------------------ TSEG Base
+//
// ------------------------ RESERVED_CPU_S3_SAVE_OFFSET
// CPU S3 data
// ------------------------ RESERVED_ACPI_S3_RANGE_OFFSET
@@ -79,57 +77,6 @@ EFI_MEMORY_TYPE_INFORMATION mDefaultCltMemoryTypeInformation[] = { };
/**
- Read south cluster GPIO input from Port A
-
-**/
-static UINT32
-ScGpioRead(
- VOID
- )
-{
- UINT32 GipMmioBase = 0xC1000000;
- UINT32 GipData;
- UINT32 GipAddr;
- UINT8 Cmd;
-
- GipAddr = PCI_LIB_ADDRESS(
- IOH_I2C_GPIO_BUS_NUMBER,
- IOH_I2C_GPIO_DEVICE_NUMBER,
- IOH_I2C_GPIO_FUNCTION_NUMBER, 0);
-
- Cmd = PciRead8 ( GipAddr + PCI_COMMAND_OFFSET);
-
- if( Cmd & EFI_PCI_COMMAND_MEMORY_SPACE) {
- // Someone already enabled mmio decoding
- GipMmioBase = PciRead32 ( GipAddr + PCI_BASE_ADDRESSREG_OFFSET);
-
- // Interested in address bits only
- GipMmioBase &= 0xFFFFFF00;
- DEBUG ((EFI_D_INFO, "SC GPIO already enabled at %08X\n", GipMmioBase));
-
- // Assume default configuration all input
- GipData = MmioRead32( GipMmioBase + GPIO_EXT_PORTA);
- }
- else {
- DEBUG ((EFI_D_INFO, "SC GPIO temporary enable at %08X\n", GipMmioBase));
-
- // Use predefined tempory memory resource
- PciWrite32 ( GipAddr + PCI_BASE_ADDRESSREG_OFFSET, GipMmioBase);
- PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
-
- // Assume default configuration all input
- GipData = MmioRead32( GipMmioBase + GPIO_EXT_PORTA);
-
- // Disable mmio decoding
- PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, 0);
- }
-
- // Only 20 bits valid
- return GipData & 0x000FFFFF;
-}
-
-
-/**
Configure Uart mmio base for MRC serial log purpose
@param MrcData - MRC configuration data updated
@@ -140,17 +87,17 @@ MrcUartConfig( MRC_PARAMS *MrcData
)
{
- UINT8 UartIdx;
- UINT32 RegData32;
- UINT8 IohUartBus;
- UINT8 IohUartDev;
+ UINT8 UartIdx;
+ UINT32 RegData32;
+ UINT8 IohUartBus;
+ UINT8 IohUartDev;
- UartIdx = PcdGet8(PcdIohUartFunctionNumber);
- IohUartBus = PcdGet8(PcdIohUartBusNumber);
- IohUartDev = PcdGet8(PcdIohUartDevNumber);
+ UartIdx = PcdGet8(PcdIohUartFunctionNumber);
+ IohUartBus = PcdGet8(PcdIohUartBusNumber);
+ IohUartDev = PcdGet8(PcdIohUartDevNumber);
- RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET));
- MrcData->uart_mmio_base = RegData32 & 0xFFFFFFF0;
+ RegData32 = PciRead32 (PCI_LIB_ADDRESS(IohUartBus, IohUartDev, UartIdx, PCI_BASE_ADDRESSREG_OFFSET));
+ MrcData->uart_mmio_base = RegData32 & 0xFFFFFFF0;
}
/**
@@ -254,7 +201,6 @@ MrcConfigureFromInfoHob ( return EFI_SUCCESS;
}
-
/**
Configure ECC scrub
@@ -267,27 +213,27 @@ EccScrubSetup( const MRC_PARAMS *MrcData
)
{
- UINT32 BgnAdr = 0;
- UINT32 EndAdr = MrcData->mem_size;
- UINT32 BlkSize = PcdGet8(PcdEccScrubBlkSize) & SCRUB_CFG_BLOCKSIZE_MASK;
- UINT32 Interval = PcdGet8(PcdEccScrubInterval) & SCRUB_CFG_INTERVAL_MASK;
-
- if( MrcData->ecc_enables == 0 || MrcData->boot_mode == bmS3 || Interval == 0) {
- // No scrub configuration needed if ECC not enabled
- // On S3 resume reconfiguration is done as part of resume
- // script, see SNCS3Save.c ==> SaveRuntimeScriptTable()
- // Also if PCD disables scrub, then we do nothing.
- return;
- }
-
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, EndAdr);
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, BgnAdr);
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, BgnAdr);
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG,
- Interval << SCRUB_CFG_INTERVAL_SHIFT |
- BlkSize << SCRUB_CFG_BLOCKSIZE_SHIFT);
-
- McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = SCRUB_RESUME_MSG();
+ UINT32 BgnAdr = 0;
+ UINT32 EndAdr = MrcData->mem_size;
+ UINT32 BlkSize = PcdGet8(PcdEccScrubBlkSize) & SCRUB_CFG_BLOCKSIZE_MASK;
+ UINT32 Interval = PcdGet8(PcdEccScrubInterval) & SCRUB_CFG_INTERVAL_MASK;
+
+ if( MrcData->ecc_enables == 0 || MrcData->boot_mode == bmS3 || Interval == 0) {
+ // No scrub configuration needed if ECC not enabled
+ // On S3 resume reconfiguration is done as part of resume
+ // script, see SNCS3Save.c ==> SaveRuntimeScriptTable()
+ // Also if PCD disables scrub, then we do nothing.
+ return;
+ }
+
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_END_MEM_REG, EndAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_START_MEM_REG, BgnAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_NEXT_READ_REG, BgnAdr);
+ QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_ECC_SCRUB_CONFIG_REG,
+ Interval << SCRUB_CFG_INTERVAL_SHIFT |
+ BlkSize << SCRUB_CFG_BLOCKSIZE_SHIFT);
+
+ McD0PciCfg32 (QNC_ACCESS_PORT_MCR) = SCRUB_RESUME_MSG();
}
/** Post InstallS3Memory / InstallEfiMemory tasks given MrcData context.
@@ -479,8 +425,8 @@ MemoryInit ( PmswAdr = (UINT16)(LpcPciCfg32 (R_QNC_LPC_GPE0BLK) & 0xFFFF) + R_QNC_GPE0BLK_PMSW;
if( IoRead32 (PmswAdr) & B_QNC_GPE0BLK_PMSW_DRAM_INIT) {
- // MRC did not complete last execution, force cold boot path
- MrcData.boot_mode = bmCold;
+ // MRC did not complete last execution, force cold boot path
+ MrcData.boot_mode = bmCold;
}
// Mark MRC pending
@@ -679,7 +625,6 @@ LoadConfig ( IN OUT MRC_PARAMS *MrcData
)
{
-
EFI_STATUS Status;
UINTN BufferSize;
PLATFORM_VARIABLE_MEMORY_CONFIG_DATA VarData;
@@ -700,7 +645,6 @@ LoadConfig ( return Status;
}
-
/**
This function installs memory.
@@ -1044,7 +988,7 @@ InstallEfiMemory ( &DescriptorAcpiVariable,
sizeof (EFI_SMRAM_DESCRIPTOR)
);
-
+
//
// Build a HOB describing memory layout and state
//
@@ -1185,7 +1129,7 @@ InstallS3Memory ( SmramIndex++;
}
}
-
+
//
// Build a HOB with the location of the reserved memory range.
//
@@ -1196,16 +1140,16 @@ InstallS3Memory ( &DescriptorAcpiVariable,
sizeof (EFI_SMRAM_DESCRIPTOR)
);
-
+
//
// Get the location and size of the S3 memory range in the reserved page and
// install it as PEI Memory.
//
-
+
DEBUG ((EFI_D_INFO, "TSEG Base = 0x%08x\n", SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart));
S3MemoryRangeData = (RESERVED_ACPI_S3_RANGE*)(UINTN)
(SmramHobDescriptorBlock->Descriptor[SmramRanges-1].PhysicalStart + RESERVED_ACPI_S3_RANGE_OFFSET);
-
+
S3MemoryBase = (UINTN) (S3MemoryRangeData->AcpiReservedMemoryBase);
DEBUG ((EFI_D_INFO, "S3MemoryBase = 0x%08x\n", S3MemoryBase));
S3MemorySize = (UINTN) (S3MemoryRangeData->AcpiReservedMemorySize);
@@ -1237,8 +1181,6 @@ InstallS3Memory ( return EFI_SUCCESS;
}
-
-
/**
Fix me
@@ -1637,7 +1579,7 @@ BaseMemoryTest ( TempAddress += SpanSize;
}
-
+
Done:
return EFI_SUCCESS;
}
@@ -1682,78 +1624,80 @@ SetPlatformImrPolicy ( }
}
- //
- // Add IMR0 protection for the 'PeiMemory'
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR0,
- (UINT32)(((RShiftU64(PeiMemoryBaseAddress, 8)) & IMRL_MASK) | IMR_EN),
- (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize + EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1) - 1), 8)) & IMRL_MASK),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
- );
+ if(FeaturePcdGet (PcdEnableSecureLock)) {
+ //
+ // Add IMR0 protection for the 'PeiMemory'
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR0,
+ (UINT32)(((RShiftU64(PeiMemoryBaseAddress, 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize + EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1) - 1), 8)) & IMRL_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
- //
- // Add IMR2 protection for shadowed RMU binary.
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR2,
- (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength), 8)) & IMRH_MASK) | IMR_EN),
- (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength+PcdGet32(PcdFlashQNCMicrocodeSize)-1), 8)) & IMRH_MASK),
- (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM)
- );
+ //
+ // Add IMR2 protection for shadowed RMU binary.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR2,
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength), 8)) & IMRH_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength+PcdGet32(PcdFlashQNCMicrocodeSize)-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + RMU + CPU0_NON_SMM)
+ );
- //
- // Add IMR3 protection for the default SMRAM.
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR3,
- (UINT32)(((RShiftU64((SMM_DEFAULT_SMBASE), 8)) & IMRL_MASK) | IMR_EN),
- (UINT32)((RShiftU64((SMM_DEFAULT_SMBASE+SMM_DEFAULT_SMBASE_SIZE_BYTES-1), 8)) & IMRH_MASK),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
- );
+ //
+ // Add IMR3 protection for the default SMRAM.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR3,
+ (UINT32)(((RShiftU64((SMM_DEFAULT_SMBASE), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((SMM_DEFAULT_SMBASE+SMM_DEFAULT_SMBASE_SIZE_BYTES-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
- //
- // Add IMR5 protection for the legacy S3 and AP Startup Vector region (below 1MB).
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR5,
- (UINT32)(((RShiftU64(AP_STARTUP_VECTOR, 8)) & IMRL_MASK) | IMR_EN),
- (UINT32)((RShiftU64((AP_STARTUP_VECTOR + EFI_PAGE_SIZE - 1), 8)) & IMRH_MASK),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
- );
+ //
+ // Add IMR5 protection for the legacy S3 and AP Startup Vector region (below 1MB).
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR5,
+ (UINT32)(((RShiftU64(AP_STARTUP_VECTOR, 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((AP_STARTUP_VECTOR + EFI_PAGE_SIZE - 1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
- //
- // Add IMR6 protection for the ACPI Reclaim/ACPI/Runtime Services.
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR6,
- (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize+EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1)), 8)) & IMRL_MASK) | IMR_EN),
- (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-EFI_PAGE_SIZE-1), 8)) & IMRH_MASK),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
- );
+ //
+ // Add IMR6 protection for the ACPI Reclaim/ACPI/Runtime Services.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR6,
+ (UINT32)(((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-RequiredMemSize+EFI_PAGES_TO_SIZE(EDKII_DXE_MEM_SIZE_PAGES-1)), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64((PeiMemoryBaseAddress+PeiMemoryLength-EFI_PAGE_SIZE-1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
- //
- // Enable IMR4 protection of eSRAM.
- //
- QncImrWrite (
- QUARK_NC_MEMORY_MANAGER_IMR4,
- (UINT32)(((RShiftU64((UINTN)FixedPcdGet32 (PcdEsramStage1Base), 8)) & IMRL_MASK) | IMR_EN),
- (UINT32)((RShiftU64(((UINTN)FixedPcdGet32 (PcdEsramStage1Base) + (UINTN)FixedPcdGet32 (PcdESramMemorySize) - 1), 8)) & IMRH_MASK),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
- (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
- );
+ //
+ // Enable IMR4 protection of eSRAM.
+ //
+ QncImrWrite (
+ QUARK_NC_MEMORY_MANAGER_IMR4,
+ (UINT32)(((RShiftU64((UINTN)FixedPcdGet32 (PcdEsramStage1Base), 8)) & IMRL_MASK) | IMR_EN),
+ (UINT32)((RShiftU64(((UINTN)FixedPcdGet32 (PcdEsramStage1Base) + (UINTN)FixedPcdGet32 (PcdESramMemorySize) - 1), 8)) & IMRH_MASK),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM),
+ (UINT32)(CPU_SNOOP + CPU0_NON_SMM)
+ );
- //
- // Enable Interrupt on IMR/SMM Violation
- //
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BIMRVCTL, (UINT32)(EnableIMRInt));
- if (DeviceId == QUARK2_MC_DEVICE_ID) {
- QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BSMMVCTL, (UINT32)(EnableSMMInt));
+ //
+ // Enable Interrupt on IMR/SMM Violation
+ //
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BIMRVCTL, (UINT32)(EnableIMRInt));
+ if (DeviceId == QUARK2_MC_DEVICE_ID) {
+ QNCPortWrite (QUARK_NC_MEMORY_MANAGER_SB_PORT_ID, QUARK_NC_MEMORY_MANAGER_BSMMVCTL, (UINT32)(EnableSMMInt));
+ }
}
//
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c index 4d5ad75..0abc671 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.c @@ -67,6 +67,9 @@ BOOLEAN ImageInMemory = FALSE; BOARD_LEGACY_GPIO_CONFIG mBoardLegacyGpioConfigTable[] = { PLATFORM_LEGACY_GPIO_TABLE_DEFINITION };
UINTN mBoardLegacyGpioConfigTableLen = (sizeof(mBoardLegacyGpioConfigTable) / sizeof(BOARD_LEGACY_GPIO_CONFIG));
+BOARD_GPIO_CONTROLLER_CONFIG mBoardGpioControllerConfigTable[] = { PLATFORM_GPIO_CONTROLLER_CONFIG_DEFINITION };
+UINTN mBoardGpioControllerConfigTableLen = (sizeof(mBoardGpioControllerConfigTable) / sizeof(BOARD_GPIO_CONTROLLER_CONFIG));
+UINT8 ChipsetDefaultMac [6] = {0xff,0xff,0xff,0xff,0xff,0xff};
STATIC EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = {
{
@@ -74,7 +77,7 @@ STATIC EFI_PEI_PPI_DESCRIPTOR mPpiBootMode[1] = { &gEfiPeiMasterBootModePpiGuid,
NULL
}
-};
+};
EFI_PEI_NOTIFY_DESCRIPTOR mMemoryDiscoveredNotifyList[1] = {
{
@@ -106,8 +109,110 @@ EFI_PEI_PPI_DESCRIPTOR mPpiStall[1] = { };
/**
+ Set Mac address on chipset ethernet device.
+
+ @param Bus PCI Bus number of chipset ethernet device.
+ @param Device Device number of chipset ethernet device.
+ @param Func PCI Function number of chipset ethernet device.
+ @param MacAddr MAC Address to set.
+
+**/
+VOID
+EFIAPI
+SetLanControllerMacAddr (
+ IN CONST UINT8 Bus,
+ IN CONST UINT8 Device,
+ IN CONST UINT8 Func,
+ IN CONST UINT8 *MacAddr,
+ IN CONST UINT32 Bar0
+ )
+{
+ UINT32 Data32;
+ UINT16 PciVid;
+ UINT16 PciDid;
+ UINT32 Addr;
+ UINT32 MacVer;
+ volatile UINT8 *Wrote;
+ UINT32 DevPcieAddr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBarReg;
+
+ DevPcieAddr = PCI_LIB_ADDRESS (
+ Bus,
+ Device,
+ Func,
+ 0
+ );
+
+ //
+ // Do nothing if not a supported device.
+ //
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
+ if((PciVid != V_IOH_MAC_VENDOR_ID) || (PciDid != V_IOH_MAC_DEVICE_ID)) {
+ return;
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR registers
+ //
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
+ SaveBarReg = PciRead32 (DevPcieAddr + R_IOH_MAC_MEMBAR);
+
+ //
+ // Use predefined tempory memory resource
+ //
+ PciWrite32 ( DevPcieAddr + R_IOH_MAC_MEMBAR, Bar0);
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_8;
+ MacVer = *((volatile UINT32 *) (UINTN)(Addr));
+
+ DEBUG ((EFI_D_INFO, "Ioh MAC [B:%d, D:%d, F:%d] VER:%04x ADDR:",
+ (UINTN) Bus,
+ (UINTN) Device,
+ (UINTN) Func,
+ (UINTN) MacVer
+ ));
+
+ //
+ // Set MAC Address0 Low Register (GMAC_REG_17) ADDRLO bits.
+ //
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_17;
+ Data32 = *((UINT32 *) (UINTN)(&MacAddr[0]));
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);
+ DEBUG ((EFI_D_INFO, "%02x-%02x-%02x-%02x-",
+ (UINTN) Wrote[0],
+ (UINTN) Wrote[1],
+ (UINTN) Wrote[2],
+ (UINTN) Wrote[3]
+ ));
+
+ //
+ // Set MAC Address0 High Register (GMAC_REG_16) ADDRHI bits
+ // and Address Enable (AE) bit.
+ //
+ Addr = Bar0 + R_IOH_MAC_GMAC_REG_16;
+ Data32 =
+ ((UINT32) MacAddr[4]) |
+ (((UINT32)MacAddr[5]) << 8) |
+ B_IOH_MAC_AE;
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+ Wrote = (volatile UINT8 *) (UINTN)(Addr);
+
+ DEBUG ((EFI_D_INFO, "%02x-%02x\n", (UINTN) Wrote[0], (UINTN) Wrote[1]));
+
+ //
+ // Restore settings for PCI CMD/BAR registers
+ //
+ PciWrite32 ((DevPcieAddr + R_IOH_MAC_MEMBAR), SaveBarReg);
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
+}
+
+/**
This is the entrypoint of PEIM
-
+
@param FileHandle Handle of the file being invoked.
@param PeiServices Describes the list of possible PEI Services.
@@ -149,9 +254,9 @@ PeiInitPlatform ( );
//
- // Do any early platform specific initialisation
+ // Do any early platform specific initialisation.
//
- EarlyPlatformInit (PlatformType);
+ EarlyPlatformInit (PlatformInfo);
//
// This is a second path on entry, in recovery boot path the Stall PPI need to be memory-based
@@ -229,12 +334,11 @@ PeiInitPlatform ( MemoryInit ((EFI_PEI_SERVICES**)PeiServices);
//
- // Do Early PCIe init if not GalileoFabE Platform.
+ // Do Early PCIe init.
//
- if (PlatformType != GalileoFabE) {
- DEBUG ((EFI_D_INFO, "Early PCIe controller initialisation\n"));
- PlatformPciExpressEarlyInit (PlatformType);
- }
+ DEBUG ((EFI_D_INFO, "Early PCIe controller initialisation\n"));
+ PlatformPciExpressEarlyInit (PlatformType);
+
DEBUG ((EFI_D_INFO, "Platform Erratas After MRC\n"));
PlatformErratasPostMrc ();
@@ -282,7 +386,7 @@ EndOfPeiSignalPpiNotifyCallback ( WriteBackInvalidateDataCacheRange (
(VOID *) (UINTN) PcdGet32 (PcdFlashAreaBaseAddress),
PcdGet32 (PcdFlashAreaSize)
- );
+ );
Status = MtrrSetMemoryAttribute (PcdGet32 (PcdFlashAreaBaseAddress), PcdGet32 (PcdFlashAreaSize), CacheUncacheable);
ASSERT_EFI_ERROR (Status);
@@ -452,33 +556,34 @@ EarlyPlatformInfoMessages ( DEBUG ((EFI_D_INFO, "************************************************************\n\n"));
- DEBUG ((EFI_D_INFO, "MFH Flash Item List:\n"));
- FlashItem = MfhLibFindFirstWithFilter (
- MFH_FIND_ANY_FIT_FILTER,
- FALSE,
- &MfhFindContext
- );
- while (FlashItem != NULL) {
- DEBUG ((EFI_D_INFO, "**** Quark 0x%08X:0x%08X %s ****\n", FlashItem->FlashAddress, FlashItem->LengthBytes, MfhLibFlashItemTypePrintString(FlashItem->Type)));
- FlashItem = MfhLibFindNextWithFilter (
+ if (!PlatformIsBootWithRecoveryStage1()) {
+ DEBUG ((EFI_D_INFO, "MFH Flash Item List:\n"));
+ FlashItem = MfhLibFindFirstWithFilter (
MFH_FIND_ANY_FIT_FILTER,
+ FALSE,
&MfhFindContext
);
- }
- DEBUG ((EFI_D_INFO, "MFH Boot Priority List:\n"));
- FlashItem = MfhLibFindFirstWithFilter (
- MFH_FIND_ALL_STAGE1_FILTER,
- TRUE,
- &MfhFindContext
- );
- while (FlashItem != NULL) {
- DEBUG ((EFI_D_INFO, "**** Quark 0x%08X:0x%08X %s ****\n", FlashItem->FlashAddress, FlashItem->LengthBytes, MfhLibFlashItemTypePrintString(FlashItem->Type)));
- FlashItem = MfhLibFindNextWithFilter (
+ while (FlashItem != NULL) {
+ DEBUG ((EFI_D_INFO, "**** Quark 0x%08X:0x%08X %s ****\n", FlashItem->FlashAddress, FlashItem->LengthBytes, MfhLibFlashItemTypePrintString(FlashItem->Type)));
+ FlashItem = MfhLibFindNextWithFilter (
+ MFH_FIND_ANY_FIT_FILTER,
+ &MfhFindContext
+ );
+ }
+ DEBUG ((EFI_D_INFO, "MFH Boot Priority List:\n"));
+ FlashItem = MfhLibFindFirstWithFilter (
MFH_FIND_ALL_STAGE1_FILTER,
+ TRUE,
&MfhFindContext
);
+ while (FlashItem != NULL) {
+ DEBUG ((EFI_D_INFO, "**** Quark 0x%08X:0x%08X %s ****\n", FlashItem->FlashAddress, FlashItem->LengthBytes, MfhLibFlashItemTypePrintString(FlashItem->Type)));
+ FlashItem = MfhLibFindNextWithFilter (
+ MFH_FIND_ALL_STAGE1_FILTER,
+ &MfhFindContext
+ );
+ }
}
-
DEBUG ((EFI_D_INFO, "\nPlatform Data Item List in System Area:\n"));
Item = PDatLibFindFirstWithFilter (NULL, PDAT_FIND_ANY_ITEM_FILTER, &PDatFindContext, NULL);
if (Item != NULL) {
@@ -544,15 +649,20 @@ CheckForResetDueToErrors ( /**
This function provides early platform initialisation.
- @param PlatformType Platform type to init.
+ @param PlatformInfo Pointer to platform Info structure.
**/
VOID
EFIAPI
EarlyPlatformInit (
- IN CONST EFI_PLATFORM_TYPE PlatformType
+ IN CONST EFI_PLATFORM_INFO *PlatformInfo
)
{
+ EFI_PLATFORM_TYPE PlatformType;
+
+ PlatformType = (EFI_PLATFORM_TYPE) PlatformInfo->Type;
+
+ DEBUG ((EFI_D_INFO, "EarlyPlatformInit for PlatType=0x%02x\n", (UINTN) PlatformType));
//
// Check if system reset due to error condition.
@@ -570,15 +680,21 @@ EarlyPlatformInit ( EarlyPlatformInfoMessages ();
//
- // Early Gpio Init.
+ // Early Legacy Gpio Init.
//
- EarlyPlatformGpioInit (PlatformType);
+ EarlyPlatformLegacyGpioInit (PlatformType);
//
- // Early platform GPIO manipulation depending on GPIOs
- // setup by EarlyPlatformGpioInit.
+ // Early platform Legacy GPIO manipulation depending on GPIOs
+ // setup by EarlyPlatformLegacyGpioInit.
//
- EarlyPlatformGpioManipulation (PlatformType);
+ EarlyPlatformLegacyGpioManipulation (PlatformType);
+
+ //
+ // Early platform specific GPIO Controller init & manipulation.
+ // Combined for sharing of temp. memory bar.
+ //
+ EarlyPlatformGpioCtrlerInitAndManipulation (PlatformType);
//
// Early Thermal Sensor Init.
@@ -586,21 +702,30 @@ EarlyPlatformInit ( EarlyPlatformThermalSensorInit ();
//
+ // Early Lan Ethernet Mac Init.
+ //
+ EarlyPlatformMacInit (
+ PlatformInfo->SysData.IohMac0Address,
+ PlatformInfo->SysData.IohMac1Address
+ );
+
+ //
// Init Redirect PEI services.
//
RedirectServicesInit ();
+
}
/**
- This function provides early platform GPIO initialisation.
+ This function provides early platform Legacy GPIO initialisation.
@param PlatformType Platform type for GPIO init.
**/
VOID
EFIAPI
-EarlyPlatformGpioInit (
+EarlyPlatformLegacyGpioInit (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
@@ -612,9 +737,7 @@ EarlyPlatformGpioInit ( // Assert if platform type outside table range.
//
ASSERT ((UINTN) PlatformType < mBoardLegacyGpioConfigTableLen);
-
LegacyGpioConfig = &mBoardLegacyGpioConfigTable[(UINTN) PlatformType];
- DEBUG ((EFI_D_INFO, "EarlyPlatformGpioInit for PlatType=0x%02x\n", (UINTN) PlatformType));
GpioBaseAddress = (UINT32)PcdGet16 (PcdGbaIoBaseAddress);
@@ -662,14 +785,14 @@ EarlyPlatformGpioInit ( }
/**
- Performs any early platform specific GPIO manipulation.
+ Performs any early platform specific Legacy GPIO manipulation.
@param PlatformType Platform type GPIO manipulation.
**/
VOID
EFIAPI
-EarlyPlatformGpioManipulation (
+EarlyPlatformLegacyGpioManipulation (
IN CONST EFI_PLATFORM_TYPE PlatformType
)
{
@@ -701,3 +824,236 @@ EarlyPlatformGpioManipulation ( }
+/**
+ Performs any early platform specific GPIO Controller init & manipulation.
+
+ @param PlatformType Platform type for GPIO init & manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformGpioCtrlerInitAndManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ )
+{
+ UINT32 IohGpioBase;
+ UINT32 Data32;
+ UINT32 Addr;
+ BOARD_GPIO_CONTROLLER_CONFIG *GpioConfig;
+ UINT32 DevPcieAddr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBarReg;
+ UINT16 PciVid;
+ UINT16 PciDid;
+
+ ASSERT ((UINTN) PlatformType < mBoardGpioControllerConfigTableLen);
+ GpioConfig = &mBoardGpioControllerConfigTable[(UINTN) PlatformType];
+
+ IohGpioBase = (UINT32) FixedPcdGet64 (PcdIohGpioMmioBase);
+
+ DevPcieAddr = PCI_LIB_ADDRESS (
+ FixedPcdGet8 (PcdIohGpioBusNumber),
+ FixedPcdGet8 (PcdIohGpioDevNumber),
+ FixedPcdGet8 (PcdIohGpioFunctionNumber),
+ 0
+ );
+
+ //
+ // Do nothing if not a supported device.
+ //
+ PciVid = PciRead16 (DevPcieAddr + PCI_VENDOR_ID_OFFSET);
+ PciDid = PciRead16 (DevPcieAddr + PCI_DEVICE_ID_OFFSET);
+ if((PciVid != V_IOH_I2C_GPIO_VENDOR_ID) || (PciDid != V_IOH_I2C_GPIO_DEVICE_ID)) {
+ return;
+ }
+
+ //
+ // Save current settings for PCI CMD/BAR registers.
+ //
+ SaveCmdReg = PciRead16 (DevPcieAddr + PCI_COMMAND_OFFSET);
+ SaveBarReg = PciRead32 (DevPcieAddr + FixedPcdGet8 (PcdIohGpioBarRegister));
+
+ //
+ // Use predefined tempory memory resource.
+ //
+ PciWrite32 ( DevPcieAddr + FixedPcdGet8 (PcdIohGpioBarRegister), IohGpioBase);
+ PciWrite8 ( DevPcieAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ //
+ // Gpio Controller Init Tasks.
+ //
+
+ //
+ // IEN- Interrupt Enable Register
+ //
+ Addr = IohGpioBase + GPIO_INTEN;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntEn & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // ISTATUS- Interrupt Status Register
+ //
+ Addr = IohGpioBase + GPIO_INTSTATUS;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // GPIO SWPORTA Direction Register - GPIO_SWPORTA_DR
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->PortADR & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // GPIO SWPORTA Data Direction Register - GPIO_SWPORTA_DDR - default input
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DDR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->PortADir & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Mask Register - GPIO_INTMASK - default interrupts unmasked
+ //
+ Addr = IohGpioBase + GPIO_INTMASK;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntMask & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Level Type Register - GPIO_INTTYPE_LEVEL - default is level sensitive
+ //
+ Addr = IohGpioBase + GPIO_INTTYPE_LEVEL;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntType & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Polarity Type Register - GPIO_INT_POLARITY - default is active low
+ //
+ Addr = IohGpioBase + GPIO_INT_POLARITY;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->IntPolarity & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Debounce Type Register - GPIO_DEBOUNCE - default no debounce
+ //
+ Addr = IohGpioBase + GPIO_DEBOUNCE;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->Debounce & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Interrupt Clock Synchronisation Register - GPIO_LS_SYNC - default no sync with pclk_intr(APB bus clk)
+ //
+ Addr = IohGpioBase + GPIO_LS_SYNC;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr)) & 0xFFFFFF00; // Keep reserved bits [31:8]
+ Data32 |= (GpioConfig->LsSync & 0x000FFFFF);
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ //
+ // Gpio Controller Manipulation Tasks.
+ //
+
+ if (PlatformType == (EFI_PLATFORM_TYPE) Galileo) {
+ //
+ // Reset Cypress Expander on Galileo Platform
+ //
+ Addr = IohGpioBase + GPIO_SWPORTA_DR;
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));
+ Data32 |= BIT4; // Cypress Reset line controlled by GPIO<4>
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ Data32 = *((volatile UINT32 *) (UINTN)(Addr));
+ Data32 &= ~BIT4; // Cypress Reset line controlled by GPIO<4>
+ *((volatile UINT32 *) (UINTN)(Addr)) = Data32;
+
+ }
+
+ //
+ // Restore settings for PCI CMD/BAR registers
+ //
+ PciWrite32 ((DevPcieAddr + FixedPcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
+ PciWrite16 (DevPcieAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
+}
+
+/**
+ Performs any early platform init of SoC Ethernet Mac devices.
+
+ @param IohMac0Address Mac address to program into Mac0 device.
+ @param IohMac1Address Mac address to program into Mac1 device.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformMacInit (
+ IN CONST UINT8 *IohMac0Address,
+ IN CONST UINT8 *IohMac1Address
+ )
+{
+ BOOLEAN SetMacAddr;
+
+ //
+ // Set chipset MAC0 address if configured.
+ //
+ SetMacAddr =
+ (CompareMem (ChipsetDefaultMac, IohMac0Address, sizeof (ChipsetDefaultMac))) != 0;
+ if (SetMacAddr) {
+ if ((*(IohMac0Address) & BIT0) != 0) {
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
+ (UINTN) IOH_MAC0_BUS_NUMBER,
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER
+ ));
+ ASSERT (FALSE);
+ } else {
+ SetLanControllerMacAddr (
+ IOH_MAC0_BUS_NUMBER,
+ IOH_MAC0_DEVICE_NUMBER,
+ IOH_MAC0_FUNCTION_NUMBER,
+ IohMac0Address,
+ (UINT32) FixedPcdGet64(PcdIohMac0MmioBase)
+ );
+ }
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
+ (UINTN) IOH_MAC0_BUS_NUMBER,
+ (UINTN) IOH_MAC0_DEVICE_NUMBER,
+ (UINTN) IOH_MAC0_FUNCTION_NUMBER
+ ));
+ }
+
+ //
+ // Set chipset MAC1 address if configured.
+ //
+ SetMacAddr =
+ (CompareMem (ChipsetDefaultMac, IohMac1Address, sizeof (ChipsetDefaultMac))) != 0;
+ if (SetMacAddr) {
+ if ((*(IohMac1Address) & BIT0) != 0) {
+ DEBUG ((EFI_D_ERROR, "HALT: Multicast Mac Address configured for Ioh MAC [B:%d, D:%d, F:%d]\n",
+ (UINTN) IOH_MAC1_BUS_NUMBER,
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER
+ ));
+ ASSERT (FALSE);
+ } else {
+ SetLanControllerMacAddr (
+ IOH_MAC1_BUS_NUMBER,
+ IOH_MAC1_DEVICE_NUMBER,
+ IOH_MAC1_FUNCTION_NUMBER,
+ IohMac1Address,
+ (UINT32) FixedPcdGet64(PcdIohMac1MmioBase)
+ );
+ }
+ } else {
+ DEBUG ((EFI_D_WARN, "WARNING: Ioh MAC [B:%d, D:%d, F:%d] NO HW ADDR CONFIGURED!!!\n",
+ (UINTN) IOH_MAC1_BUS_NUMBER,
+ (UINTN) IOH_MAC1_DEVICE_NUMBER,
+ (UINTN) IOH_MAC1_FUNCTION_NUMBER
+ ));
+ }
+}
+
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h index 367e0c4..7ca95f1 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.h @@ -247,13 +247,13 @@ InitializeUSBPhy ( /**
This function provides early platform initialisation.
- @param PlatformType Platform type to init.
+ @param PlatformInfo Pointer to platform Info structure.
**/
VOID
EFIAPI
EarlyPlatformInit (
- IN CONST EFI_PLATFORM_TYPE PlatformType
+ IN CONST EFI_PLATFORM_INFO *PlatformInfo
);
/**
@@ -264,7 +264,7 @@ EarlyPlatformInit ( **/
VOID
EFIAPI
-EarlyPlatformGpioInit (
+EarlyPlatformLegacyGpioInit (
IN CONST EFI_PLATFORM_TYPE PlatformType
);
@@ -276,11 +276,37 @@ EarlyPlatformGpioInit ( **/
VOID
EFIAPI
-EarlyPlatformGpioManipulation (
+EarlyPlatformLegacyGpioManipulation (
+ IN CONST EFI_PLATFORM_TYPE PlatformType
+ );
+
+/**
+ Performs any early platform specific GPIO Controller init & manipulation.
+
+ @param PlatformType Platform type for GPIO init & manipulation.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformGpioCtrlerInitAndManipulation (
IN CONST EFI_PLATFORM_TYPE PlatformType
);
/**
+ Performs any early platform init of SoC Ethernet Mac devices.
+
+ @param IohMac0Address Mac address to program into Mac0 device.
+ @param IohMac1Address Mac address to program into Mac1 device.
+
+**/
+VOID
+EFIAPI
+EarlyPlatformMacInit (
+ IN CONST UINT8 *IohMac0Address,
+ IN CONST UINT8 *IohMac1Address
+ );
+
+/**
Find security headers using EFI_CAPSULE_VARIABLE_NAME variables and build Hobs.
@param PeiServices General purpose services available to every PEIM.
diff --git a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf index c83d773..81a038f 100755 --- a/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf +++ b/QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf @@ -113,7 +113,6 @@ RecoveryOemHookLib
PcdLib
IntelQNCLib
- IohLib
ReportStatusCodeLib
PciLib
PciExpressLib
@@ -208,6 +207,13 @@ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber
gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber
gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase
gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPciHostBridgeMemory32Base
diff --git a/QuarkPlatformPkg/QuarkPlatformPkg.dec b/QuarkPlatformPkg/QuarkPlatformPkg.dec index 30eacab..2f4d82d 100755 --- a/QuarkPlatformPkg/QuarkPlatformPkg.dec +++ b/QuarkPlatformPkg/QuarkPlatformPkg.dec @@ -51,7 +51,7 @@ # Include Section - list of Include Paths that are provided by this package.
# Comments are used for Keywords and Module Types.
#
-# Supported Module Types:
+# Supported Module Types:
# SEC PEIM DXE_DRIVER DXE_RUNTIME_DRIVER DXE_SMM_DRIVER DXE_SAL_DRIVER UEFI_DRIVER
#
################################################################################
@@ -84,7 +84,7 @@ gEfiMemoryConfigDataGuid = { 0x80dbd530, 0xb74c, 0x4f11, { 0x8c, 0x03, 0x41, 0x86, 0x65, 0x53, 0x28, 0x31 }}
gPowerManagementAcpiTableStorageGuid = { 0xc0cc43bd, 0xc920, 0x4064, { 0x93, 0x5b, 0x93, 0xb4, 0x47, 0x37, 0x94, 0x70 }}
gSignalBeforeEnterSetupGuid = { 0xd9f1669a, 0xf505, 0x48bd, { 0xa8, 0x92, 0x94, 0xb7, 0xca, 0x90, 0x30, 0x31 }}
- gEfiSetupVariableGuid = {0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }}
+ gEfiSetupVariableGuid = {0xec87d643, 0xeba4, 0x4bb5, {0xa1, 0xe5, 0x3f, 0x3e, 0x36, 0xb2, 0xd, 0xa9 }}
gEfiFlashMapHobGuid = {0xb091e7d2, 0x5a0, 0x4198, {0x94, 0xf0, 0x74, 0xb7, 0xb8, 0xc5, 0x54, 0x59}}
gPeiCapsuleOnFatFloppyDiskGuid = {0x2e3d2e75, 0x9b2e, 0x412d, {0xb4, 0xb1, 0x70, 0x41, 0x6b, 0x87, 0x0, 0xff }}
gPeiCapsuleOnFatIdeDiskGuid = {0xb38573b6, 0x6200, 0x4ac5, {0xb5, 0x1d, 0x82, 0xe6, 0x59, 0x38, 0xd7, 0x83 }}
@@ -143,8 +143,8 @@ gQuarkPlatformTokenSpaceGuid.PcdShortformBootSupport|TRUE|BOOLEAN|0x00000002
[PcdsFixedAtBuild]
- gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFFC00000|UINT32|0x20000001
- gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize|0x400000|UINT32|0x20000002
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress|0xFF800000|UINT32|0x20000001
+ gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize|0x800000|UINT32|0x20000002
gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageBase|0xFFF30000|UINT32|0x20000003
gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageSize|0x00020000|UINT32|0x20000004
gQuarkPlatformTokenSpaceGuid.PcdFlashFvRecovery2Base|0xFFEF0400|UINT32|0x2000001C
@@ -153,10 +153,10 @@ gQuarkPlatformTokenSpaceGuid.PcdPlatformDataBaseAddress|0xFFF10000|UINT32|0x2000001E
gQuarkPlatformTokenSpaceGuid.PcdPlatformDataMaxLen|0x20000|UINT32|0x2000001F
gQuarkPlatformTokenSpaceGuid.PcdHpetEnable|TRUE|BOOLEAN|0x20000018
- gQuarkPlatformTokenSpaceGuid.PcdMemorySize|0x80000000|UINT32|0x20000032
- gQuarkPlatformTokenSpaceGuid.PcdFvSecurityHeaderSize|0x400|UINT32|0x20000036
- # ECC scrub interval in miliseconds 1..255 (0 works as feature disable)
- gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval|0x00|UINT8|0x20000037
+ gQuarkPlatformTokenSpaceGuid.PcdMemorySize|0x80000000|UINT32|0x20000032
+ gQuarkPlatformTokenSpaceGuid.PcdFvSecurityHeaderSize|0x400|UINT32|0x20000036
+ # ECC scrub interval in miliseconds 1..255 (0 works as feature disable)
+ gQuarkPlatformTokenSpaceGuid.PcdEccScrubInterval|0x00|UINT8|0x20000037
# Number of 32B blocks read for ECC scrub 2..16
gQuarkPlatformTokenSpaceGuid.PcdEccScrubBlkSize|0x02|UINT8|0x20000038
gQuarkPlatformTokenSpaceGuid.PcdFlashNvMfh|0xFFF08000|UINT32|0x20000039
@@ -183,7 +183,7 @@ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0SourceIrq|0x00|UINT8|0xA0000101
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0Polarity|0x00|UINT8|0xA0000102
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0TrigerMode|0x00|UINT8|0xA0000103
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq|0x02|UINT32|0xA0000104
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable0GlobalIrq|0x02|UINT32|0xA0000104
# Madt Table Initialize settings.
# Defines a flag to Enable/Disable interrupt override setting table1,
@@ -201,7 +201,7 @@ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2SourceIrq|0x0|UINT8|0xA0000110
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2Polarity|0x0|UINT8|0xA0000111
gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2TrigerMode|0x0|UINT8|0xA0000112
- gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq|0x0|UINT32|0xA0000113
+ gQuarkPlatformTokenSpaceGuid.PcdInterruptOverrideSettingTable2GlobalIrq|0x0|UINT32|0xA0000113
# Madt Table Initialize settings.
# Defines a flag to Enable/Disable interrupt override setting table3,
@@ -340,7 +340,7 @@ gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingTrigerMode|0x01|UINT8|0xA000017A
gQuarkPlatformTokenSpaceGuid.PcdLocalApicSettingLocalApicLint|0x01|UINT8|0xA000017B
gQuarkPlatformTokenSpaceGuid.PcdLocalApicAddressOverride|0x00|UINT64|0xA000017C
-
+
# PCDs for auto provisioning of UEFI 2.3.1 SecureBoot.
gQuarkPlatformTokenSpaceGuid.PcdPkX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA000017D
gQuarkPlatformTokenSpaceGuid.PcdKekX509File |{ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }|VOID*|0xA000017E
@@ -358,9 +358,9 @@ # String number of the BIOS Vendors Name
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosVendor|"Intel Corp."|VOID*|0xA0000033
# String number of the BIOS Release Data
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate|"01/01/2014"|VOID*|0xA0000035
- # Segment location of BIOS starting address.
- # Note: The size of the runtime BIOS image can be computed by subtracting the Starting Address Segment from 10000h and multiplying the result by 16.
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosReleaseDate|"01/01/2014"|VOID*|0xA0000035
+ # Segment location of BIOS starting address.
+ # Note: The size of the runtime BIOS image can be computed by subtracting the Starting Address Segment from 10000h and multiplying the result by 16.
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosStartAddress|0xE000|UINT16|0xA0000036
#Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc. See 3.3.1.1.
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSBiosChar|0x03037C099880|UINT64|0xA0000037
@@ -375,10 +375,10 @@ # System Product String
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemProductName|"QUARK"|VOID*|0xA000003B
# System Version
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion|"1.0"|VOID*|0xA000003C
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemVersion|"1.0"|VOID*|0xA000003C
# System SerialNumber String
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"Unknown"|VOID*|0xA000003D
- # System UUID
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSerialNumber|"Unknown"|VOID*|0xA000003D
+ # System UUID
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemUuid|{0x23, 0xef, 0xff, 0x13,0x54, 0x86, 0xda, 0x46, 0xa4, 0x7, 0x39, 0xc9, 0x12, 0x2, 0xd3, 0x56}|VOID*|0xA000003E
# Manufacturer String
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSKUNumber|"System SKUNumber"|VOID*|0xA000003F
@@ -418,12 +418,12 @@ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisHeight|0x0|UINT8|0xA000004D
# Identifies the number of power cords associated with the enclosure or chassis. A value of 00h indicates that the number is unspecified.
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisNumberPowerCords|0x0|UINT8|0xA000004E
- # Identifies the number of Contained Element records that follow, in the range 0 to 255.
- # Each Contained Element group comprises m bytes, as specified by the Contained Element Record Length field that follows.
+ # Identifies the number of Contained Element records that follow, in the range 0 to 255.
+ # Each Contained Element group comprises m bytes, as specified by the Contained Element Record Length field that follows.
# If no Contained Elements are included, this field is set to 0.
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementCount|0x0|UINT8|0xA000004F
# Identifies the byte length of each Contained Element record that follow, in the range 0 to 255.
- # If no Contained Elements are included, this field is set to 0. For v2.3.2 and later of this specification,
+ # If no Contained Elements are included, this field is set to 0. For v2.3.2 and later of this specification,
# this field is set to at least 03h when Contained Elements are specified.
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSChassisElementRecordLength|0x0|UINT8|0xA0000050
@@ -657,24 +657,24 @@ # Defines the number of the slots existent on board
# The valid range is between 0 and 14
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber|5|UINT8|0xA000023F
- # Defines the designation of system slot1
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation|"PCI SLOT1"|VOID*|0xA0000240
- # Defines the type of system slot1
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlotNumber|5|UINT8|0xA000023F
+ # Defines the designation of system slot1
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Designation|"PCI SLOT1"|VOID*|0xA0000240
+ # Defines the type of system slot1
# The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type|0x6|UINT8|0xA0000241
- # Defines the data bus width of system slot1
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Type|0x6|UINT8|0xA0000241
+ # Defines the data bus width of system slot1
# The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth|0x5|UINT8|0xA0000242
- # Defines the usage of system slot1
- # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1DataBusWidth|0x5|UINT8|0xA0000242
+ # Defines the usage of system slot1
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Usage|0x3|UINT8|0xA0000243
- # Defines the length of system slot1
- # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length|0x4|UINT8|0xA0000244
- # Defines the ID of system slot1, a number of UINT16
+ # Defines the length of system slot1
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Length|0x4|UINT8|0xA0000244
+ # Defines the ID of system slot1, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Id|0x01|UINT16|0xA0000245
- # Defines the characteristics of system slot1 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot1 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
# typedef struct {
# UINT32 CharacteristicsUnknown :1;
# UINT32 Provides50Volts :1;
@@ -691,252 +691,252 @@ # } EFI_MISC_SLOT_CHARACTERISTICS;
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot1Characteristics|0x504|UINT32|0xA0000246
- # Defines the designation of system slot2
+ # Defines the designation of system slot2
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Designation|"PCI-Express 1"|VOID*|0xA0000247
- # Defines the type of system slot2
+ # Defines the type of system slot2
# The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Type|0xA5|UINT8|0xA0000248
- # Defines the data bus width of system slot2
+ # Defines the data bus width of system slot2
# The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2DataBusWidth|0x5|UINT8|0xA0000249
- # Defines the usage of system slot2
- # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage|0x3|UINT8|0xA000024A
- # Defines the length of system slot2
- # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
+ # Defines the usage of system slot2
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Usage|0x3|UINT8|0xA000024A
+ # Defines the length of system slot2
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Length|0x4|UINT8|0xA000024B
- # Defines the ID of system slot2, a number of UINT16
+ # Defines the ID of system slot2, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Id|0x02|UINT16|0xA000024C
- # Defines the characteristics of system slot2 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot2 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot2Characteristics|0x504|UINT32|0xA000024D
- # Defines the designation of system slot3
+ # Defines the designation of system slot3
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Designation|"PCI-Express 2"|VOID*|0xA000024E
- # Defines the type of system slot3
+ # Defines the type of system slot3
# The valid range is between 0x01 to 0xA5, and 0x06 here means EfiSlotTypePci
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type|0xA5|UINT8|0xA000024F
- # Defines the data bus width of system slot3
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Type|0xA5|UINT8|0xA000024F
+ # Defines the data bus width of system slot3
# The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3DataBusWidth|0x5|UINT8|0xA0000250
- # Defines the usage of system slot3
- # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage|0x3|UINT8|0xA0000251
- # Defines the length of system slot3
- # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length|0x4|UINT8|0xA0000252
- # Defines the ID of system slot3, a number of UINT16
+ # Defines the usage of system slot3
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Usage|0x3|UINT8|0xA0000251
+ # Defines the length of system slot3
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Length|0x4|UINT8|0xA0000252
+ # Defines the ID of system slot3, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Id|0x03|UINT16|0xA0000253
- # Defines the characteristics of system slot3 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot3 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot3Characteristics|0x504|UINT32|0xA000254
- # Defines the designation of system slot4
+ # Defines the designation of system slot4
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Designation|"PCI-Express 3"|VOID*|0xA0000255
# Defines the type of system slot4
# The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type|0xA5|UINT8|0xA0000256
- # Defines the data bus width of system slot4
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Type|0xA5|UINT8|0xA0000256
+ # Defines the data bus width of system slot4
# The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4DataBusWidth|0x5|UINT8|0xA0000257
- # Defines the usage of system slot4
- # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage|0x3|UINT8|0xA0000258
+ # Defines the usage of system slot4
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Usage|0x3|UINT8|0xA0000258
# Defines the length of system slot4
- # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length|0x4|UINT8|0xA0000259
- # Defines the ID of system slot4, a number of UINT16
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Length|0x4|UINT8|0xA0000259
+ # Defines the ID of system slot4, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Id|0x04|UINT16|0xA0000260
- # Defines the characteristics of system slot4 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot4 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot4Characteristics|0x504|UINT32|0xA0000261
- # Defines the designation of system slot5
+ # Defines the designation of system slot5
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Designation|"Mini PCI-E"|VOID*|0xA0000262
- # Defines the type of system slot5
+ # Defines the type of system slot5
# The valid range is between 0x01 to 0xA5, and 0xA5 here means EfiSlotTypePciExpress
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type|0xA5|UINT8|0xA0000263
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Type|0xA5|UINT8|0xA0000263
# Defines the data bus width of system slot5
# The valid range is between 0x01 to 0x07, and 0x05 here means EfiSlotDataBusWidth32Bit
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5DataBusWidth|0x5|UINT8|0xA0000264
- # Defines the usage of system slot5
- # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage|0x3|UINT8|0xA0000265
- # Defines the length of system slot5
- # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length|0x4|UINT8|0xA0000266
- # Defines the ID of system slot5, a number of UINT16
+ # Defines the usage of system slot5
+ # The valid range is between 0x01 to 0x04, and 0x03 here means EfiSlotUsageAvailable
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Usage|0x3|UINT8|0xA0000265
+ # Defines the length of system slot5
+ # The valid range is between 0x01 to 0x04, and 0x04 here means EfiSlotLengthLong
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Length|0x4|UINT8|0xA0000266
+ # Defines the ID of system slot5, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Id|0x05|UINT16|0xA0000267
- # Defines the characteristics of system slot5 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot5 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot5Characteristics|0x504|UINT32|0xA0000268
- # Defines the designation of system slot6
+ # Defines the designation of system slot6
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Designation|"NONE"|VOID*|0xA0000269
- # Defines the type of system slot6
+ # Defines the type of system slot6
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Type|0x2|UINT8|0xA000026A
- # Defines the data bus width of system slot6
+ # Defines the data bus width of system slot6
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth|0x2|UINT8|0xA000026B
- # Defines the usage of system slot6
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage|0x2|UINT8|0xA000026C
- # Defines the length of system slot6
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length|0x2|UINT8|0xA000026D
- # Defines the ID of system slot6, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6DataBusWidth|0x2|UINT8|0xA000026B
+ # Defines the usage of system slot6
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Usage|0x2|UINT8|0xA000026C
+ # Defines the length of system slot6
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Length|0x2|UINT8|0xA000026D
+ # Defines the ID of system slot6, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Id|0x0|UINT16|0xA000026E
- # Defines the characteristics of system slot6 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics|0x0|UINT32|0xA000026F
+ # Defines the characteristics of system slot6 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot6Characteristics|0x0|UINT32|0xA000026F
- # Defines the designation of system slot7
+ # Defines the designation of system slot7
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Designation|"NONE"|VOID*|0xA0000270
- # Defines the type of system slot7
+ # Defines the type of system slot7
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type|0x2|UINT8|0xA0000271
- # Defines the data bus width of system slot7
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Type|0x2|UINT8|0xA0000271
+ # Defines the data bus width of system slot7
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth|0x2|UINT8|0xA0000272
- # Defines the usage of system slot7
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage|0x2|UINT8|0xA0000273
- # Defines the length of system slot7
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length|0x2|UINT8|0xA0000274
- # Defines the ID of system slot7, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7DataBusWidth|0x2|UINT8|0xA0000272
+ # Defines the usage of system slot7
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Usage|0x2|UINT8|0xA0000273
+ # Defines the length of system slot7
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Length|0x2|UINT8|0xA0000274
+ # Defines the ID of system slot7, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Id|0x0|UINT16|0xA0000275
- # Defines the characteristics of system slot7 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot7 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot7Characteristics|0x0|UINT32|0xA0000276
- # Defines the designation of system slot8
+ # Defines the designation of system slot8
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Designation|"NONE"|VOID*|0xA0000277
- # Defines the type of system slot8
+ # Defines the type of system slot8
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type|0x2|UINT8|0xA0000278
- # Defines the data bus width of system slot8
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Type|0x2|UINT8|0xA0000278
+ # Defines the data bus width of system slot8
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth|0x2|UINT8|0xA0000279
- # Defines the usage of system slot8
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8DataBusWidth|0x2|UINT8|0xA0000279
+ # Defines the usage of system slot8
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Usage|0x2|UINT8|0xA000027A
- # Defines the length of system slot8
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length|0x2|UINT8|0xA000027B
- # Defines the ID of system slot8, a number of UINT16
+ # Defines the length of system slot8
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Length|0x2|UINT8|0xA000027B
+ # Defines the ID of system slot8, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Id|0x0|UINT16|0xA000027C
- # Defines the characteristics of system slot8 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot8 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot8Characteristics|0x0|UINT32|0xA000027D
- # Defines the designation of system slot9
+ # Defines the designation of system slot9
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Designation|"NONE"|VOID*|0xA000027E
- # Defines the type of system slot9
+ # Defines the type of system slot9
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type|0x2|UINT8|0xA000027F
- # Defines the data bus width of system slot9
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Type|0x2|UINT8|0xA000027F
+ # Defines the data bus width of system slot9
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth|0x2|UINT8|0xA0000280
- # Defines the usage of system slot9
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage|0x2|UINT8|0xA0000281
- # Defines the length of system slot9
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length|0x2|UINT8|0xA0000282
- # Defines the ID of system slot9, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9DataBusWidth|0x2|UINT8|0xA0000280
+ # Defines the usage of system slot9
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Usage|0x2|UINT8|0xA0000281
+ # Defines the length of system slot9
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Length|0x2|UINT8|0xA0000282
+ # Defines the ID of system slot9, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Id|0x0|UINT16|0xA0000283
- # Defines the characteristics of system slot9 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics|0x0|UINT32|0xA0000284
+ # Defines the characteristics of system slot9 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot9Characteristics|0x0|UINT32|0xA0000284
- # Defines the designation of system slot10
+ # Defines the designation of system slot10
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Designation|"None"|VOID*|0xA0000285
- # Defines the type of system slot10
+ # Defines the type of system slot10
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type|0x2|UINT8|0xA0000286
- # Defines the data bus width of system slot10
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Type|0x2|UINT8|0xA0000286
+ # Defines the data bus width of system slot10
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth|0x2|UINT8|0xA0000287
- # Defines the usage of system slot10
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage|0x2|UINT8|0xA0000288
- # Defines the length of system slot10
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length|0x2|UINT8|0xA0000289
- # Defines the ID of system slot10, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10DataBusWidth|0x2|UINT8|0xA0000287
+ # Defines the usage of system slot10
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Usage|0x2|UINT8|0xA0000288
+ # Defines the length of system slot10
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Length|0x2|UINT8|0xA0000289
+ # Defines the ID of system slot10, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Id|0x0|UINT16|0xA000028A
- # Defines the characteristics of system slot10 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics|0x0|UINT32|0xA000028B
+ # Defines the characteristics of system slot10 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot10Characteristics|0x0|UINT32|0xA000028B
- # Defines the designation of system slot11
+ # Defines the designation of system slot11
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Designation|"None"|VOID*|0xA000028C
- # Defines the type of system slot11
+ # Defines the type of system slot11
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type|0x2|UINT8|0xA000028D
- # Defines the data bus width of system slot11
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Type|0x2|UINT8|0xA000028D
+ # Defines the data bus width of system slot11
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth|0x2|UINT8|0xA000028E
- # Defines the usage of system slot11
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage|0x2|UINT8|0xA000028F
- # Defines the length of system slot11
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length|0x2|UINT8|0xA0000290
- # Defines the ID of system slot11, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11DataBusWidth|0x2|UINT8|0xA000028E
+ # Defines the usage of system slot11
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Usage|0x2|UINT8|0xA000028F
+ # Defines the length of system slot11
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Length|0x2|UINT8|0xA0000290
+ # Defines the ID of system slot11, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Id|0x0|UINT16|0xA00000EE
- # Defines the characteristics of system slot11 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics|0x0|UINT32|0xA0000291
+ # Defines the characteristics of system slot11 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot11Characteristics|0x0|UINT32|0xA0000291
- # Defines the designation of system slot12
+ # Defines the designation of system slot12
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Designation|"None"|VOID*|0xA0000292
- # Defines the type of system slot12
+ # Defines the type of system slot12
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type|0x2|UINT8|0xA0000293
- # Defines the data bus width of system slot12
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Type|0x2|UINT8|0xA0000293
+ # Defines the data bus width of system slot12
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth|0x2|UINT8|0xA0000294
- # Defines the usage of system slot12
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage|0x2|UINT8|0xA0000295
- # Defines the length of system slot12
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length|0x2|UINT8|0xA0000296
- # Defines the ID of system slot12, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12DataBusWidth|0x2|UINT8|0xA0000294
+ # Defines the usage of system slot12
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Usage|0x2|UINT8|0xA0000295
+ # Defines the length of system slot12
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Length|0x2|UINT8|0xA0000296
+ # Defines the ID of system slot12, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Id|0x0|UINT16|0xA0000297
- # Defines the characteristics of system slot12 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics|0x0|UINT32|0xA0000298
+ # Defines the characteristics of system slot12 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot12Characteristics|0x0|UINT32|0xA0000298
- # Defines the designation of system slot13
+ # Defines the designation of system slot13
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Designation|"None"|VOID*|0xA0000299
- # Defines the type of system slot13
+ # Defines the type of system slot13
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type|0x2|UINT8|0xA000029A
- # Defines the data bus width of system slot13
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Type|0x2|UINT8|0xA000029A
+ # Defines the data bus width of system slot13
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth|0x2|UINT8|0xA000029B
- # Defines the usage of system slot13
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage|0x2|UINT8|0xA000029C
- # Defines the length of system slot13
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length|0x2|UINT8|0xA000029D
- # Defines the ID of system slot13, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13DataBusWidth|0x2|UINT8|0xA000029B
+ # Defines the usage of system slot13
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Usage|0x2|UINT8|0xA000029C
+ # Defines the length of system slot13
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Length|0x2|UINT8|0xA000029D
+ # Defines the ID of system slot13, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Id|0x0|UINT16|0xA000029E
- # Defines the characteristics of system slot13 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot13 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot13Characteristics|0x0|UINT32|0xA000029F
- # Defines the designation of system slot14
+ # Defines the designation of system slot14
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Designation|"None"|VOID*|0xA00002A0
- # Defines the type of system slot14
+ # Defines the type of system slot14
# The valid range is between 0x01 to 0xA5, and 0x02 here means EfiSlotTypeUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type|0x2|UINT8|0xA00002A1
- # Defines the data bus width of system slot14
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Type|0x2|UINT8|0xA00002A1
+ # Defines the data bus width of system slot14
# The valid range is between 0x01 to 0x07, and 0x02 here means EfiSlotDataBusWidthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth|0x2|UINT8|0xA00002A2
- # Defines the usage of system slot14
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage|0x2|UINT8|0xA00002A3
- # Defines the length of system slot14
- # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
- gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length|0x2|UINT8|0xA00002A4
- # Defines the ID of system slot14, a number of UINT16
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14DataBusWidth|0x2|UINT8|0xA00002A2
+ # Defines the usage of system slot14
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotUsageUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Usage|0x2|UINT8|0xA00002A3
+ # Defines the length of system slot14
+ # The valid range is between 0x01 to 0x04, and 0x02 here means EfiSlotLengthUnknown
+ gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Length|0x2|UINT8|0xA00002A4
+ # Defines the ID of system slot14, a number of UINT16
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Id|0x0|UINT16|0xA00002A5
- # Defines the characteristics of system slot14 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
+ # Defines the characteristics of system slot14 , a bit mask of EFI_MISC_SLOT_CHARACTERISTICS
gQuarkPlatformTokenSpaceGuid.PcdSMBIOSSystemSlot14Characteristics|0x0|UINT32|0xA00002A6
[PcdsDynamic, PcdsDynamicEx]
diff --git a/QuarkPlatformPkg/QuarkPlatformPkg.dsc b/QuarkPlatformPkg/QuarkPlatformPkg.dsc index 215231b..a2fb5b6 100755 --- a/QuarkPlatformPkg/QuarkPlatformPkg.dsc +++ b/QuarkPlatformPkg/QuarkPlatformPkg.dsc @@ -52,122 +52,122 @@ # Set the global variables
#
EDK_GLOBAL PLATFORM_PKG = QuarkPlatformPkg
-
+
#
# Platform On/Off features are defined here
#
- !include $(PLATFORM_PKG)/QuarkPlatformPkgConfig.dsc
-
+ !include $(PLATFORM_PKG)/QuarkPlatformPkgConfig.dsc
+
FLASH_DEFINITION = $(PLATFORM_PKG)/QuarkPlatformPkg.fdf
-
-################################################################################
-#
-# SKU Identification section - list of all SKU IDs supported by this
-# Platform.
-#
-################################################################################
-[SkuIds]
- 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
-
-################################################################################
-#
-# Library Class section - list of all Library Classes needed by this Platform.
-#
-################################################################################
-[LibraryClasses]
- #
- # Entry point
- #
- PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
- PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
- DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
- UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
- UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
- #
- # Basic
- #
- BaseLib|QuarkSocPkg/Override/MdePkg/Library/BaseLib/BaseLib.inf
+
+################################################################################
+#
+# SKU Identification section - list of all SKU IDs supported by this
+# Platform.
+#
+################################################################################
+[SkuIds]
+ 0|DEFAULT # The entry: 0|DEFAULT is reserved and always required.
+
+################################################################################
+#
+# Library Class section - list of all Library Classes needed by this Platform.
+#
+################################################################################
+[LibraryClasses]
+ #
+ # Entry point
+ #
+ PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf
+ PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf
+ DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf
+ UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntryPoint.inf
+ UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiApplicationEntryPoint.inf
+ #
+ # Basic
+ #
+ BaseLib|QuarkSocPkg/Override/MdePkg/Library/BaseLib/BaseLib.inf
BaseMemoryLib|QuarkSocPkg/Override/MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf
- PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
- CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
- PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
- PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
- CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
- PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
+ PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+ CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ PciLib|MdePkg/Library/BasePciLibCf8/BasePciLibCf8.inf
+ PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMaintenanceLib.inf
+ PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf
!if $(CFG_SOURCE_DEBUG) == TRUE
- PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
-!else
- PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
-!endif
- PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
- #
- # UEFI & PI
- #
- UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
- UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
- UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
- UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
- HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
- UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
- DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
- UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
- PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
- PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
- DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
- DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
- UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
- #
- # Framework
- #
+ PeCoffExtraActionLib|SourceLevelDebugPkg/Library/PeCoffExtraActionLibDebug/PeCoffExtraActionLibDebug.inf
+!else
+ PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeCoffExtraActionLibNull.inf
+!endif
+ PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeCoffGetEntryPointLib.inf
+ #
+ # UEFI & PI
+ #
+ UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBootServicesTableLib.inf
+ UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/UefiRuntimeServicesTableLib.inf
+ UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf
+ UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
+ HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+ UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+ DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf
+ UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
+ PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/PeiServicesTablePointerLibIdt.inf
+ PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf
+ DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
+ DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableLib.inf
+ UefiCpuLib|UefiCpuPkg/Library/BaseUefiCpuLib/BaseUefiCpuLib.inf
+ #
+ # Framework
+ #
S3BootScriptLib|MdeModulePkg/Library/PiDxeS3BootScriptLib/DxeS3BootScriptLib.inf
S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf
S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf
- #
- # Generic Modules
- #
- UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
- UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
- NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
- IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
- UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
- DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
- OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
- SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
+ #
+ # Generic Modules
+ #
+ UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf
+ NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+ IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+ UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+ DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+ OemHookStatusCodeLib|MdeModulePkg/Library/OemHookStatusCodeLibNull/OemHookStatusCodeLibNull.inf
+ SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchronizationLib.inf
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
SmmCorePlatformHookLib|MdeModulePkg/Library/SmmCorePlatformHookLibNull/SmmCorePlatformHookLibNull.inf
- #
- # CPU
- #
+ #
+ # CPU
+ #
MtrrLib|QuarkSocPkg/Override/UefiCpuPkg/Library/MtrrLib/MtrrLib.inf
LocalApicLib|UefiCpuPkg/Library/BaseXApicLib/BaseXApicLib.inf
- CpuConfigLib|IA32FamilyCpuBasePkg/Library/CpuConfigLib/CpuConfigLib.inf
- CpuOnlyResetLib|IA32FamilyCpuBasePkg/Library/CpuOnlyResetLibNull/CpuOnlyResetLibNull.inf
- #
+ CpuConfigLib|IA32FamilyCpuBasePkg/Library/CpuConfigLib/CpuConfigLib.inf
+ CpuOnlyResetLib|IA32FamilyCpuBasePkg/Library/CpuOnlyResetLibNull/CpuOnlyResetLibNull.inf
+ #
# Quark North Cluster
- #
- SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf
- SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf
- TimerLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCAcpiTimerLib/IntelQNCAcpiTimerLib.inf
- ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf
- IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf
- QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf
+ #
+ SmmLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCSmmLib/QNCSmmLib.inf
+ SmbusLib|QuarkSocPkg/QuarkNorthCluster/Library/SmbusLib/SmbusLib.inf
+ TimerLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCAcpiTimerLib/IntelQNCAcpiTimerLib.inf
+ ResetSystemLib|QuarkSocPkg/QuarkNorthCluster/Library/ResetSystemLib/ResetSystemLib.inf
+ IntelQNCLib|QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf
+ QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/QNCAccessLib.inf
RedirectPeiServicesLib|QuarkSocPkg/QuarkNorthCluster/Library/RedirectPeiServicesLib/RedirectPeiServicesLib.inf
- #
+ #
# Quark South Cluster
- #
- IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf
+ #
+ IohLib|QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf
SerialPortLib|QuarkSocPkg/QuarkSouthCluster/Library/IohSerialPortLib/IohSerialPortLib.inf
- #
- # Platform
- #
+ #
+ # Platform
+ #
PlatformSecServicesLib|QuarkPlatformPkg/Library/PlatformSecServicesLib/PlatformSecServicesLib.inf
UefiBootManagerLib|QuarkPlatformPkg/Bds/Library/UefiBootManagerLib/UefiBootManagerLib.inf
LogoLib|QuarkPlatformPkg/Library/LogoLib/LogoLib.inf
PlatformBootManagerLib|QuarkPlatformPkg/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
- RecoveryOemHookLib|QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf
- PlatformSecLib|QuarkPlatformPkg/Library/QuarkSecLib/QuarkSecLib.inf
+ RecoveryOemHookLib|QuarkPlatformPkg/Library/RecoveryOemHookLib/RecoveryOemHookLib.inf
+ PlatformSecLib|QuarkPlatformPkg/Library/QuarkSecLib/QuarkSecLib.inf
SecurityAuthenticationLib|QuarkPlatformPkg/Library/QuarkBootRomLib/QuarkBootRomLib.inf
SmmScriptLib|QuarkPlatformPkg/Library/SmmScriptLib/SmmScriptLib.inf
CapsuleLib|QuarkPlatformPkg/Library/PlatformCapsuleLib/PlatformCapsuleLib.inf
@@ -175,37 +175,38 @@ PlatformDataLib|QuarkPlatformPkg/Library/PlatformDataLib/PlatformDataLib.inf
SmmCpuPlatformHookLib|QuarkPlatformPkg/Library/SmmCpuPlatformHookLib/SmmCpuPlatformHookLib.inf
PlatformSecureLib|QuarkPlatformPkg/Library/PlatformSecureLib/PlatformSecureLib.inf
- #
- # Misc
- #
+ PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PlatformPcieHelperLib.inf
+ #
+ # Misc
+ #
DebugLib|IntelFrameworkModulePkg/Library/PeiDxeDebugLibReportStatusCode/PeiDxeDebugLibReportStatusCode.inf
DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseDebugPrintErrorLevelLib.inf
PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibNull.inf
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
!if $(CFG_SOURCE_DEBUG) == TRUE
- DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
-!else
- DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
-!endif
+ DebugCommunicationLib|SourceLevelDebugPkg/Library/DebugCommunicationLibSerialPort/DebugCommunicationLibSerialPort.inf
+!else
+ DebugAgentLib|MdeModulePkg/Library/DebugAgentLibNull/DebugAgentLibNull.inf
+!endif
#
# Crypto
#
IntrinsicLib|CryptoPkg/Library/IntrinsicLib/IntrinsicLib.inf
- OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
-
-[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE]
- #
- # SEC and PEI phase common
- #
- PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
- HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
- MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
+ OpensslLib|CryptoPkg/Library/OpensslLib/OpensslLib.inf
+
+[LibraryClasses.IA32.PEIM,LibraryClasses.IA32.PEI_CORE]
+ #
+ # SEC and PEI phase common
+ #
+ PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf
+ HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/PeiReportStatusCodeLib/PeiReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExtractGuidedSectionLib.inf
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxPeiLib.inf
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
!if $(CFG_SOURCE_DEBUG) == TRUE
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SecPeiDebugAgentLib.inf
!endif
SwBpeLib|QuarkPlatformPkg/Library/SwBpeLib/SwBpeLib.inf
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/PeiCryptLib.inf
@@ -214,28 +215,27 @@ # Platform SEC and PEI phase common.
#
PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/PeiPlatformHelperLib.inf
- PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/PeiPlatformPcieHelperLib.inf
-[LibraryClasses.IA32.SEC]
- #
- # SEC specific phase
- #
+[LibraryClasses.IA32.SEC]
+ #
+ # SEC specific phase
+ #
ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseReportStatusCodeLibNull.inf
- DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
-
-[LibraryClasses.IA32]
- #
- # DXE phase common
- #
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
- MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
- ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
+ DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+
+[LibraryClasses.IA32]
+ #
+ # DXE phase common
+ #
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf
+ MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
+ ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExtractGuidedSectionLib.inf
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxDxeLib.inf
!if $(CFG_SOURCE_DEBUG) == TRUE
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/DxeDebugAgentLib.inf
!endif
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/BaseCryptLib.inf
@@ -243,52 +243,51 @@ # Platform DXE phase common.
#
PlatformHelperLib|QuarkPlatformPkg/Library/PlatformHelperLib/DxePlatformHelperLib.inf
- PlatformPcieHelperLib|QuarkPlatformPkg/Library/PlatformPcieHelperLib/DxePlatformPcieHelperLib.inf
-[LibraryClasses.IA32.DXE_CORE]
- HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
- MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
- PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
-
-[LibraryClasses.IA32.DXE_SMM_DRIVER]
- SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
- MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
+[LibraryClasses.IA32.DXE_CORE]
+ HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf
+ MemoryAllocationLib|MdeModulePkg/Library/DxeCoreMemoryAllocationLib/DxeCoreMemoryAllocationLib.inf
+ PerformanceLib|MdeModulePkg/Library/DxeCorePerformanceLib/DxeCorePerformanceLib.inf
+
+[LibraryClasses.IA32.DXE_SMM_DRIVER]
+ SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+ MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAllocationLib.inf
LockBoxLib|MdeModulePkg/Library/SmmLockBoxLib/SmmLockBoxSmmLib.inf
!if $(CFG_SOURCE_DEBUG) == TRUE
- DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
+ DebugAgentLib|SourceLevelDebugPkg/Library/DebugAgent/SmmDebugAgentLib.inf
!endif
!if $(PERFORMANCE_ENABLE) == TRUE
PerformanceLib|MdeModulePkg/Library/SmmPerformanceLib/SmmPerformanceLib.inf
!endif
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
-
-[LibraryClasses.IA32.SMM_CORE]
- SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
- ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
+
+[LibraryClasses.IA32.SMM_CORE]
+ SmmServicesTableLib|MdeModulePkg/Library/PiSmmCoreSmmServicesTableLib/PiSmmCoreSmmServicesTableLib.inf
+ ReportStatusCodeLib|MdeModulePkg/Library/SmmReportStatusCodeLib/SmmReportStatusCodeLib.inf
MemoryAllocationLib|MdeModulePkg/Library/PiSmmCoreMemoryAllocationLib/PiSmmCoreMemoryAllocationLib.inf
!if $(PERFORMANCE_ENABLE) == TRUE
PerformanceLib|MdeModulePkg/Library/SmmCorePerformanceLib/SmmCorePerformanceLib.inf
-!endif
+!endif
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/SmmCryptLib.inf
-
-[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]
- ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
+
+[LibraryClasses.IA32.DXE_RUNTIME_DRIVER]
+ ReportStatusCodeLib|MdeModulePkg/Library/RuntimeDxeReportStatusCodeLib/RuntimeDxeReportStatusCodeLib.inf
BaseCryptLib|CryptoPkg/Library/BaseCryptLib/RuntimeCryptLib.inf
QNCAccessLib|QuarkSocPkg/QuarkNorthCluster/Library/QNCAccessLib/RuntimeQNCAccessLib.inf
-[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION]
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+[LibraryClasses.IA32.UEFI_DRIVER,LibraryClasses.IA32.UEFI_APPLICATION]
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
!if $(PERFORMANCE_ENABLE) == TRUE
PerformanceLib|MdeModulePkg/Library/DxeSmmPerformanceLib/DxeSmmPerformanceLib.inf
-!endif
+!endif
################################################################################
#
# Pcd Section - list of all EDK II PCD Entries defined by this Platform
#
################################################################################
-[PcdsFeatureFlag]
+[PcdsFeatureFlag]
gEfiMdeModulePkgTokenSpaceGuid.PcdSupportUpdateCapsuleReset|TRUE
gEfiMdeModulePkgTokenSpaceGuid.PcdDxeIplSwitchToLongMode|FALSE
gEfiMdeModulePkgTokenSpaceGuid.PcdPciBusHotplugDeviceSupport|FALSE
@@ -323,10 +322,10 @@ !endif
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareRevision| 0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVendor|"EDK II"
- gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06
- gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18
+ gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x06
+ gEfiMdePkgTokenSpaceGuid.PcdPostCodePropertyMask|0x18
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x00
- gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xE0000000
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
@@ -334,26 +333,26 @@ gEfiMdePkgTokenSpaceGuid.PcdDefaultTerminalType|0
!if $(PERFORMANCE_ENABLE) == TRUE
gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1
-!endif
+!endif
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40
- gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
- gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000
- gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|40
+ gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|0
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00002000
+ gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x1000
## RTC Update Timeout Value, need to increase timeout since also
# waiting for RTC to be busy.
gEfiMdeModulePkgTokenSpaceGuid.PcdRealTimeClockUpdateTimeout|500000
- gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x4000
- gEfiCpuTokenSpaceGuid.PcdPlatformType|1
- gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|3800
- gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066
+ gEfiCpuTokenSpaceGuid.PcdTemporaryRamSize|0x4000
+ gEfiCpuTokenSpaceGuid.PcdPlatformType|1
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxCoreFrequency|3800
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuMaxFsbFrequency|1066
gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000
gPcAtChipsetPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdLegacyBiosCacheLegacyRegion|FALSE
!ifdef SECURE_BOOT
gEfiSecurityPkgTokenSpaceGuid.PcdOptionRomImageVerificationPolicy|0x01|UINT32|0x00000001
gEfiSecurityPkgTokenSpaceGuid.PcdRemovableMediaImageVerificationPolicy|0x04|UINT32|0x00000002
@@ -366,133 +365,133 @@ gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|$(DEBUG_PRINT_ERROR_LEVEL)
!endif
-[PcdsDynamicExHii.common.DEFAULT]
+[PcdsDynamicExHii.common.DEFAULT]
gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVariableGuid|0x0|5
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdBootState|L"BootState"|gQuarkPlatformTokenSpaceGuid|0x0|TRUE
-[PcdsDynamicExDefault.common.DEFAULT]
- gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
+[PcdsDynamicExDefault.common.DEFAULT]
+ gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0
gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE
- # IntelFrameworkModulePkg.dec
- gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|0
+ # IntelFrameworkModulePkg.dec
+ gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|0
- # IA32FamilyCpuBasePkg
+ # IA32FamilyCpuBasePkg
gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureUserConfiguration|0xffffffff
- gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset|FALSE
- gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags|0x0
- gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames|0x0
- gEfiCpuTokenSpaceGuid.PcdPlatformCpuFrequencyLists|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuMtrrTableAddress|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuPageTableAddress|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSetting|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapability|0x0
- gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0
-
-###################################################################################################
-#
-# Components Section - list of the modules and components that will be processed by compilation
-# tools and the EDK II tools to generate PE32/PE32+/Coff image files.
-#
-# Note: The EDK II DSC file is not used to specify how compiled binary images get placed
-# into firmware volume images. This section is just a list of modules to compile from
-# source into UEFI-compliant binaries.
-# It is the FDF file that contains information on combining binary files into firmware
-# volume images, whose concept is beyond UEFI and is described in PI specification.
-# Binary modules do not need to be listed in this section, as they should be
-# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT binary (Fat.efi),
-# Logo (Logo.bmp), and etc.
-# There may also be modules listed in this section that are not required in the FDF file,
-# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be
-# generated for it, but the binary will not be put into any firmware volume.
-#
-###################################################################################################
-
-[Components.IA32]
- #
- # SEC Core
- #
- IA32FamilyCpuBasePkg/SecCore/SecCore.inf
+ gEfiCpuTokenSpaceGuid.PcdIsPowerOnReset|FALSE
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuAssetTags|0x0
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuSocketNames|0x0
+ gEfiCpuTokenSpaceGuid.PcdPlatformCpuFrequencyLists|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuConfigContextBuffer|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuMtrrTableAddress|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuPageTableAddress|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureSetting|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuProcessorFeatureCapability|0x0
+ gEfiCpuTokenSpaceGuid.PcdCpuCallbackSignal|0x0
+
+###################################################################################################
+#
+# Components Section - list of the modules and components that will be processed by compilation
+# tools and the EDK II tools to generate PE32/PE32+/Coff image files.
+#
+# Note: The EDK II DSC file is not used to specify how compiled binary images get placed
+# into firmware volume images. This section is just a list of modules to compile from
+# source into UEFI-compliant binaries.
+# It is the FDF file that contains information on combining binary files into firmware
+# volume images, whose concept is beyond UEFI and is described in PI specification.
+# Binary modules do not need to be listed in this section, as they should be
+# specified in the FDF file. For example: Shell binary (Shell_Full.efi), FAT binary (Fat.efi),
+# Logo (Logo.bmp), and etc.
+# There may also be modules listed in this section that are not required in the FDF file,
+# When a module listed here is excluded from FDF file, then UEFI-compliant binary will be
+# generated for it, but the binary will not be put into any firmware volume.
+#
+###################################################################################################
+
+[Components.IA32]
+ #
+ # SEC Core
+ #
+ IA32FamilyCpuBasePkg/SecCore/SecCore.inf
QuarkPlatformPkg/Cpu/Sec/ResetVector/QuarkResetVector.inf
-
- #
- # PEI Core
- #
+
+ #
+ # PEI Core
+ #
MdeModulePkg/Core/Pei/PeiMain.inf
- #
- # PEIM
- #
- MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- }
+ #
+ # PEIM
+ #
+ MdeModulePkg/Universal/PCD/Pei/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
!ifdef SECURE_BOOT
SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
!else
MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
- !endif
- MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf
- IA32FamilyCpuBasePkg/CpuPei/CpuPei.inf
+ !endif
+ MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf
+ IA32FamilyCpuBasePkg/CpuPei/CpuPei.inf
MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
-
- QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf
- QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf {
- <LibraryClasses>
- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
- }
+
+ QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf
+ QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf {
+ <LibraryClasses>
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ }
QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf
IA32FamilyCpuBasePkg/PiSmmCommunication/PiSmmCommunicationPei.inf
-
- QuarkPlatformPkg/Override/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
- <LibraryClasses>
- NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- }
-
- #
- # S3
- #
- QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf
+
+ QuarkPlatformPkg/Override/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+ <LibraryClasses>
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ }
+
+ #
+ # S3
+ #
+ QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf
QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmControlPei/SmmControlPei.inf
QuarkPlatformPkg/Override/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf {
<LibraryClasses>
!if $(PERFORMANCE_ENABLE) == TRUE
- PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
+ PerformanceLib|MdeModulePkg/Library/PeiPerformanceLib/PeiPerformanceLib.inf
TimerLib|IA32FamilyCpuBasePkg/Library/CpuLocalApicTimerLib/CpuLocalApicTimerLib.inf
!endif
- }
-
+ }
+
#
# Recovery
- #
- QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf
+ #
+ QuarkSocPkg/QuarkSouthCluster/Usb/Common/Pei/UsbPei.inf
MdeModulePkg/Bus/Pci/EhciPei/EhciPei.inf
- QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf
+ QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Pei/OhciPei.inf
MdeModulePkg/Bus/Usb/UsbBotPei/UsbBotPei.inf
MdeModulePkg/Bus/Usb/UsbBusPei/UsbBusPei.inf
FatPkg/FatPei/FatPei.inf
MdeModulePkg/Universal/Disk/CdExpressPei/CdExpressPei.inf
-
-[Components.IA32]
- #
- # DXE Core
- #
- MdeModulePkg/Core/Dxe/DxeMain.inf {
- <LibraryClasses>
+
+[Components.IA32]
+ #
+ # DXE Core
+ #
+ MdeModulePkg/Core/Dxe/DxeMain.inf {
+ <LibraryClasses>
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
- NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
- }
+ NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+ NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+ }
QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf
- #
- # Components that produce the architectural protocols
- #
+ #
+ # Components that produce the architectural protocols
+ #
MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
<LibraryClasses>
NULL|QuarkPlatformPkg/Library/PlatformUnProvisionedHandlerLib/PlatformUnProvisionedHandlerLib.inf
@@ -502,11 +501,11 @@ !endif
}
- IA32FamilyCpuBasePkg/CpuArchDxe/CpuArchDxe.inf
- IA32FamilyCpuBasePkg/CpuMpDxe/CpuMpDxe.inf
- MdeModulePkg/Universal/Metronome/Metronome.inf
- MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
- MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ IA32FamilyCpuBasePkg/CpuArchDxe/CpuArchDxe.inf
+ IA32FamilyCpuBasePkg/CpuMpDxe/CpuMpDxe.inf
+ MdeModulePkg/Universal/Metronome/Metronome.inf
+ MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
+ MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
QuarkPlatformPkg/Override/MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteSmm.inf
MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
@@ -524,38 +523,38 @@ QuarkPlatformPkg/Override/PcAtChipsetPkg/PcatRealTimeClockRuntimeDxe/PcatRealTimeClockRuntimeDxe.inf
#
- # Following are the DXE drivers (alphabetical order)
- #
- MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
- MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
- }
-
+ # Following are the DXE drivers (alphabetical order)
+ #
+ MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+ MdeModulePkg/Universal/PCD/Dxe/Pcd.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
+ }
+
$(PLATFORM_PKG)/Pci/Dxe/PciHostBridge/PciHostBridge.inf
$(PLATFORM_PKG)/Platform/SpiFvbServices/PlatformSpi.inf
$(PLATFORM_PKG)/Platform/SpiFvbServices/PlatformSmmSpi.inf
-
- IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
- UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf {
- <LibraryClasses>
- IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
- }
-
- #
- # Platform
- #
+
+ IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
+ UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf {
+ <LibraryClasses>
+ IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
+ }
+
+ #
+ # Platform
+ #
QuarkPlatformPkg/Bds/BootManagerMenuApp/BootManagerMenuApp.inf
QuarkPlatformPkg/Bds/BdsDxe/BdsDxe.inf
- QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf
+ QuarkSocPkg/QuarkNorthCluster/QNCInit/Dxe/QNCInitDxe.inf
QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf
- QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf {
- <LibraryClasses>
+ QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf {
+ <LibraryClasses>
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- }
+ }
QuarkSocPkg/QuarkNorthCluster/Spi/RuntimeDxe/PchSpiRuntime.inf {
<LibraryClasses>
PciExpressLib|MdePkg/Library/DxeRuntimePciExpressLib/DxeRuntimePciExpressLib.inf
@@ -566,81 +565,80 @@ DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
}
- IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
- IntelFrameworkModulePkg/Universal/DataHubStdErrDxe/DataHubStdErrDxe.inf
- IntelFrameworkModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
- MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
- MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
- MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
- MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
- MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
- #
- # ACPI
- #
+ IntelFrameworkModulePkg/Universal/DataHubDxe/DataHubDxe.inf
+ IntelFrameworkModulePkg/Universal/DataHubStdErrDxe/DataHubStdErrDxe.inf
+ IntelFrameworkModulePkg/Universal/SectionExtractionDxe/SectionExtractionDxe.inf
+ MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+ MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
+ MdeModulePkg/Universal/StatusCodeHandler/RuntimeDxe/StatusCodeHandlerRuntimeDxe.inf
+ MdeModulePkg/Universal/ReportStatusCodeRouter/Smm/ReportStatusCodeRouterSmm.inf
+ MdeModulePkg/Universal/StatusCodeHandler/Smm/StatusCodeHandlerSmm.inf
+ #
+ # ACPI
+ #
QuarkPlatformPkg/Platform/Dxe/SaveMemoryConfig/SaveMemoryConfig.inf
MdeModulePkg/Universal/Acpi/S3SaveStateDxe/S3SaveStateDxe.inf
QuarkPlatformPkg/Acpi/Dxe/BootScriptExecutorDxe/BootScriptExecutorDxe.inf {
- <LibraryClasses>
+ <LibraryClasses>
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- }
- MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+ }
+ MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
IntelFrameworkModulePkg/Universal/Acpi/AcpiS3SaveDxe/AcpiS3SaveDxe.inf
- QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
- QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf
-
- #
- # SMM
- #
- MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
+ QuarkPlatformPkg/Acpi/AcpiTables/AcpiTables.inf
+ QuarkPlatformPkg/Acpi/Dxe/AcpiPlatform/AcpiPlatform.inf
+
+ #
+ # SMM
+ #
+ MdeModulePkg/Core/PiSmmCore/PiSmmIpl.inf
MdeModulePkg/Core/PiSmmCore/PiSmmCore.inf {
<LibraryClasses>
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- }
+ }
IA32FamilyCpuBasePkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {
<LibraryClasses>
DebugLib|MdePkg/Library/BaseDebugLibSerialPort/BaseDebugLibSerialPort.inf
- }
- UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
- QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf
- QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmRuntime/SmmRuntime.inf
- QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf
+ }
+ UefiCpuPkg/CpuIo2Smm/CpuIo2Smm.inf
+ QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmControlDxe/SmmControlDxe.inf
+ QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmRuntime/SmmRuntime.inf
+ QuarkSocPkg/QuarkNorthCluster/Smm/DxeSmm/QncSmmDispatcher/QNCSmmDispatcher.inf
QuarkPlatformPkg/Acpi/DxeSmm/AcpiSmm/AcpiSmmPlatform.inf {
<LibraryClasses>
IoLib|MdePkg/Library/SmmIoLibSmmCpuIo2/SmmIoLibSmmCpuIo2.inf
}
- QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf
+ QuarkPlatformPkg/Acpi/DxeSmm/SmmPowerManagement/SmmPowerManagement.inf
QuarkPlatformPkg/Override/MdeModulePkg/Universal/LockBox/SmmLockBox/SmmLockBox.inf
IA32FamilyCpuBasePkg/PiSmmCommunication/PiSmmCommunicationSmm.inf
-
- #
- # SMBIOS
- #
- MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
- QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf
- QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf
- #
- # PCI
- #
- QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf
- MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
- QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf
- QuarkSocPkg/QuarkSouthCluster/Uart/Dxe/SerialDxe.inf
-
- #
- # USB
- #
- QuarkPlatformPkg/Override/MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
- QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
- QuarkPlatformPkg/Override/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
- MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
- MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
- MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
-
- #
- # SDIO
- #
- QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf
+ #
+ # SMBIOS
+ #
+ MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+ QuarkPlatformPkg/Platform/Dxe/SmbiosMiscDxe/SmbiosMiscDxe.inf
+ QuarkPlatformPkg/Platform/Dxe/MemorySubClass/MemorySubClass.inf
+ #
+ # PCI
+ #
+ QuarkPlatformPkg/Pci/Dxe/PciPlatform/PciPlatform.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ QuarkSocPkg/QuarkSouthCluster/IohInit/Dxe/IohInitDxe.inf
+ QuarkSocPkg/QuarkSouthCluster/Uart/Dxe/SerialDxe.inf
+
+ #
+ # USB
+ #
+ QuarkPlatformPkg/Override/MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+ QuarkSocPkg/QuarkSouthCluster/Usb/Ohci/Dxe/OhciDxe.inf
+ QuarkPlatformPkg/Override/MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+ MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+ MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+ #
+ # SDIO
+ #
+ QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDControllerDxe/SDControllerDxe.inf
QuarkSocPkg/QuarkSouthCluster/Sdio/Dxe/SDMediaDeviceDxe/SDMediaDeviceDxe.inf
#
@@ -649,46 +647,45 @@ QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2CDxe.inf
#
- # IDE/SCSI
- #
- MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
- MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
-
-
- #
- # Console
+ # IDE/SCSI
+ #
+ MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+ MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+
#
- MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
- MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf {
- <LibraryClasses>
- PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
- }
+ # Console
+ #
+ MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+ MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf {
+ <LibraryClasses>
+ PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ }
MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
- MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
- MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
- MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
- MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+ MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+ MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+ MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+ MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
- #
- # Legacy Modules
- #
- PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
-
- #
+ #
+ # Legacy Modules
+ #
+ PcAtChipsetPkg/8259InterruptControllerDxe/8259.inf
+
+ #
# File System Modules
- #
+ #
FatPkg/EnhancedFatDxe/Fat.inf
-
- #
+
+ #
# Capsule related drivers
- #
+ #
IntelFrameworkModulePkg/Universal/FirmwareVolume/FwVolDxe/FwVolDxe.inf
IntelFrameworkModulePkg/Universal/FirmwareVolume/UpdateDriverDxe/UpdateDriverDxe.inf
QuarkPlatformPkg/Platform/DxeSmm/SMIFlashDxe/SMIFlashDxe.inf
-
+
#
# Capsule Application
- #
+ #
QuarkPlatformPkg/Applications/CapsuleApp/CapsuleApp.inf {
<LibraryClasses>
ShellLib|ShellPkg/Library/UefiShellLib/UefiShellLib.inf
@@ -718,14 +715,14 @@ SortLib|ShellPkg/Library/UefiSortLib/UefiSortLib.inf
PerformanceLib|MdeModulePkg/Library/DxeSmmPerformanceLib/DxeSmmPerformanceLib.inf
}
-!endif
+!endif
###################################################################################################
#
# BuildOptions Section - Define the module specific tool chain flags that should be used as
-# the default flags for a module. These flags are appended to any
-# standard flags that are defined by the build process. They can be
-# applied for any modules or only those modules with the specific
+# the default flags for a module. These flags are appended to any
+# standard flags that are defined by the build process. They can be
+# applied for any modules or only those modules with the specific
# module style (EDK or EDKII) specified in [Components] section.
#
###################################################################################################
diff --git a/QuarkPlatformPkg/QuarkPlatformPkg.fdf b/QuarkPlatformPkg/QuarkPlatformPkg.fdf index cb6985b..75861a9 100755 --- a/QuarkPlatformPkg/QuarkPlatformPkg.fdf +++ b/QuarkPlatformPkg/QuarkPlatformPkg.fdf @@ -46,17 +46,17 @@ #
################################################################################
[FD.Quark]
-BaseAddress = 0xFFC00000 #The base address of the 4MB FLASH Device.
-Size = 0x400000 #The size in bytes of the 4MB FLASH Device.
+BaseAddress = 0xFF800000 #The base address of the the FLASH Device.
+Size = 0x800000 #The size in bytes of the the FLASH Device.
ErasePolarity = 1
BlockSize = 0x1000
-NumBlocks = 0x400 #The number of blocks for 4MB FLASH Device.
+NumBlocks = 0x800 #The number of blocks for the FLASH Device.
#
#Flash location override based on actual flash map
#
-SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFFC00000
-SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = 0x400000
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaBaseAddress = 0xFF800000
+SET gQuarkPlatformTokenSpaceGuid.PcdFlashAreaSize = 0x800000
SET gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageBase = 0xFFF30000
SET gQuarkPlatformTokenSpaceGuid.PcdFlashNvStorageSize = 0x20000
@@ -85,14 +85,14 @@ SET gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize = 0x00120000 ########################################################
# Quark EDKII Payload Image.
########################################################
-0x00000400|0x000F0000
+0x00400400|0x000F0000
gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvPayloadSize
FV = EDKII_PAYLOAD_IMAGE
########################################################
# Quark EDKII Stage2 Image (Compressed)
########################################################
-0x00100400|0x00120000
+0x00500400|0x00120000
gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainBase|gQuarkPlatformTokenSpaceGuid.PcdFlashFvMainSize
FV = EDKII_BOOT_STAGE2_COMPACT
@@ -100,20 +100,20 @@ FV = EDKII_BOOT_STAGE2_COMPACT # Quark EDKII Stage1 Backup Image
# Quark EDKII Stage1 contains: Stage1 FV + Remote Management Unit Binary
#########################################################
-0x00280400|0x0003f000
+0x00680400|0x0003f000
FV = EDKII_BOOT_STAGE1_IMAGE2
#########################################################
# Quark EDKII Stage1 Primary Image
# Quark EDKII Stage1 contains: Stage1 FV + Remote Management Unit Binary
#########################################################
-0x002C0400|0x0003f000
+0x006C0400|0x0003f000
FV = EDKII_BOOT_STAGE1_IMAGE1
#########################################################
# Quark Remote Management Unit Binary
#########################################################
-0x00300000|0x00008000
+0x00700000|0x00008000
!ifdef QUARK2
FILE = QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin
!else
@@ -123,7 +123,7 @@ FV = EDKII_BOOT_STAGE1_IMAGE1 #########################################################
# Master Flash Header Data.
#########################################################
-0x00308000|0x00001000
+0x00708000|0x00001000
DATA = {
## This is the MFH_HEADER struct.
# MFH_HEADER.QuarkMFHIdentifier.
@@ -131,50 +131,48 @@ DATA = { # MFH_HEADER.Version, MFH_HEADER.RsvdFlags & MFH_HEADER.NextHeaderBlock.
0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
# MFH_HEADER.FlashItemCount UINT32 LSB - MSB.
- 0x07, 0x00, 0x00, 0x00,
+ 0x06, 0x00, 0x00, 0x00,
# MFH_HEADER.BootPriorityListCount UINT32 LSB - MSB.
0x03, 0x00, 0x00, 0x00,
## This is the BootPriorityList.
# 1st , 2nd , 3rd.
- 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00,
+ 0x01, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
## This is Flash Item [0] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF9, 0xFF, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
## This is Flash Item [1] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5, 0xFF, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is Flash Item [2] desc. 4xUINT32 LSB - MSB.
- # Type , FlashAddress , LengthBytes, ,Reserved.
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEC, 0xFF, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is Flash Item [3] desc. 4xUINT32 LSB - MSB.
+ ## This is Flash Item [2] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE8, 0xFF, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is Flash Item [4] desc. 4xUINT32 LSB - MSB.
+ ## This is Flash Item [3] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0xD0, 0xFF, 0x00, 0x00, 0x12, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is Flash Item [5] desc. 4xUINT32 LSB - MSB.
+ ## This is Flash Item [4] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
0x0B, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00,
- ## This is Flash Item [6] desc. 4xUINT32 LSB - MSB.
+ ## This is Flash Item [5] desc. 4xUINT32 LSB - MSB.
# Type , FlashAddress , LengthBytes, ,Reserved.
- 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x08, 0x00
+ 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x99, 0x02, 0x00, 0x01
}
#########################################################
# PlatformData Binary, default for standalone is none built-in so user selects.
#########################################################
-#0x00310000|0x00001000
+#0x00710000|0x00001000
#FILE = QuarkPlatformPkg/Binary/PlatformData/svp-platform-data.bin
#FILE = QuarkPlatformPkg/Binary/PlatformData/kipsbay-platform-data.bin
#FILE = QuarkPlatformPkg/Binary/PlatformData/crosshill-platform-data.bin
#FILE = QuarkPlatformPkg/Binary/PlatformData/clantonhill-platform-data.bin
#FILE = QuarkPlatformPkg/Binary/PlatformData/galileo-platform-data.bin
+#FILE = QuarkPlatformPkg/Binary/PlatformData/galileo-gen2-platform-data.bin
#############################################################################
# Quark EDKII NVRAM Area
# Quark EDKII NVRAM Area contains: Variable + FTW Working + FTW Spare
#############################################################################
-0x00330000|0x0000E000
+0x00730000|0x0000E000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
#NV_VARIABLE_STORE
DATA = {
@@ -213,7 +211,7 @@ DATA = { 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x0033E000|0x00002000
+0x0073E000|0x00002000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
#NV_FTW_WORKING
DATA = {
@@ -227,34 +225,24 @@ DATA = { 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
}
-0x00340000|0x00010000
+0x00740000|0x00010000
gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
#NV_FTW_SPARE
#########################################################################################
-# Quark EDKII Recovery Backup Image
-# Quark EDKII Recovery contains: Recovery Stage1 FV + Recovery Stage2 FV + Remote Management Unit Binary
-#########################################################################################
-0x00350400|0x00038000
-FV = EDKII_RECOVERY_STAGE1_IMAGE2
-
-0x00388400|0x00007000
-FV = EDKII_RECOVERY_STAGE2_IMAGE2
-
-#########################################################################################
# Quark EDKII Recovery Primary Image
# Quark EDKII Recovery contains: Recovery Stage1 FV + Recovery Stage2 FV + Remote Management Unit Binary
#########################################################################################
-0x00390400|0x00038000
+0x00790400|0x00038000
FV = EDKII_RECOVERY_STAGE1_IMAGE1
-0x003C8400|0x00007000
+0x007C8400|0x00007000
FV = EDKII_RECOVERY_STAGE2_IMAGE1
#######################
# Quark BootRom Image
#######################
-0x003E0000|0x00020000
+0x007E0000|0x00020000
FV = EDKII_BOOTROM_OVERRIDE
################################################################################
@@ -399,9 +387,6 @@ FILE FREEFORM = EE84C5E7-9412-42cc-B755-A915A7B68536 { FILE FREEFORM = E4AD87C8-D20E-40ce-97F5-9756FD0E81D4 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-platform-data.bin
}
-FILE FREEFORM = E27ADA6A-9F8A-4f2e-B09E-4CCDD82C2F54 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin
- }
FILE FREEFORM = 23B3C10D-46E3-4a78-8AAA-217B6A39EF04 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-gen2-platform-data.bin
}
@@ -481,167 +466,7 @@ FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 { # module statements.
#
################################################################################
-[FV.EDKII_RECOVERY_STAGE1_IMAGE2]
-BlockSize = 0x1000
-FvBaseAddress = 0x80000400
-FvForceRebase = TRUE
-FvAlignment = 16 #FV alignment and FV attributes setting.
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-FvNameGuid = 18D6D9F4-2EEF-4913-AEE6-BE61C6DA6CC8
-
-################################################################################
-#
-# The INF statements point to EDK component and EDK II module INF files, which will be placed into this FV image.
-# Parsing tools will scan the INF file to determine the type of component or module.
-# The component or module type is used to reference the standard rules
-# defined elsewhere in the FDF file.
-#
-# The format for INF statements is:
-# INF $(PathAndInfFileName)
-#
-################################################################################
- ##
- # PEI Apriori file example, more PEIM module added later.
- ##
-APRIORI PEI {
- INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
- # PlatformConfigPei should be immediately after Pcd driver.
- INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf
- INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf
- INF MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
- INF MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
- INF QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
- }
-
- ##
- # PEI Phase RAW Data files.
- ##
-FILE FREEFORM = PCD(gEfiQuarkNcSocIdTokenSpaceGuid.PcdQuarkMicrocodeFile) {
-!ifdef QUARK2
- SECTION RAW = QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin
-!else
- SECTION RAW = QuarkSocPkg/QuarkNorthCluster/Binary/QuarkMicrocode/RMU.bin
-!endif
- }
-
- ##
- # Platform data files see QuarkPlatformPkg/Include/Guid/PlatformDataFileNameGuids.h
- # for steps to add new platform.
- ##
-FILE FREEFORM = 0A975562-DF47-4dc3-8AB0-3BA2C3522302 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/svp-platform-data.bin
- }
-FILE FREEFORM = 956EDAD3-8440-45cb-89AC-D1930C004E34 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/kipsbay-platform-data.bin
- }
-FILE FREEFORM = 095B3C16-6D67-4c85-B528-339D9FF6222C {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/crosshill-platform-data.bin
- }
-FILE FREEFORM = EE84C5E7-9412-42cc-B755-A915A7B68536 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/clantonhill-platform-data.bin
- }
-FILE FREEFORM = E4AD87C8-D20E-40ce-97F5-9756FD0E81D4 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-platform-data.bin
- }
-FILE FREEFORM = E27ADA6A-9F8A-4f2e-B09E-4CCDD82C2F54 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin
- }
-FILE FREEFORM = 23B3C10D-46E3-4a78-8AAA-217B6A39EF04 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-gen2-platform-data.bin
- }
-
-
- ##
- # PEI Phase modules
- ##
-INF IA32FamilyCpuBasePkg/SecCore/SecCore.inf
-INF MdeModulePkg/Core/Pei/PeiMain.inf
-INF RuleOverride = NORELOC MdeModulePkg/Universal/PCD/Pei/Pcd.inf
-# PlatformConfigPei should be immediately after Pcd driver.
-INF QuarkPlatformPkg/Platform/Pei/PlatformConfig/PlatformConfigPei.inf
-INF RuleOverride = NORELOC MdeModulePkg/Universal/ReportStatusCodeRouter/Pei/ReportStatusCodeRouterPei.inf
-INF RuleOverride = NORELOC MdeModulePkg/Universal/StatusCodeHandler/Pei/StatusCodeHandlerPei.inf
-!ifdef SECURE_BOOT
- INF RuleOverride = NORELOC SecurityPkg/VariableAuthenticated/Pei/VariablePei.inf
-!else
- INF RuleOverride = NORELOC MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
-!endif
-INF RuleOverride = NORELOC IA32FamilyCpuBasePkg/CpuPei/CpuPei.inf
-INF RuleOverride = NORELOC MdeModulePkg/Universal/CapsulePei/CapsulePei.inf
-INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/MemoryInit/Pei/MemoryInitPei.inf
-INF RuleOverride = NORELOC QuarkSocPkg/QuarkNorthCluster/Smm/Pei/SmmAccessPei/SmmAccessPei.inf
-INF QuarkPlatformPkg/Platform/Pei/PlatformInit/PlatformEarlyInit.inf
-INF QuarkPlatformPkg/Platform/Pei/PlatformInfo/PlatformInfo.inf
-INF MdeModulePkg/Universal/PcatSingleSegmentPciCfg2Pei/PcatSingleSegmentPciCfg2Pei.inf
-INF QuarkPlatformPkg/Override/MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file. This section also defines order the components and modules are positioned
-# within the image. The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-[FV.EDKII_RECOVERY_STAGE2_IMAGE2]
-BlockSize = 0x1000
-FvBaseAddress = 0x80030000
-FvForceRebase = TRUE
-FvAlignment = 16 #FV alignment and FV attributes setting.
-ERASE_POLARITY = 1
-MEMORY_MAPPED = TRUE
-STICKY_WRITE = TRUE
-LOCK_CAP = TRUE
-LOCK_STATUS = TRUE
-WRITE_DISABLED_CAP = TRUE
-WRITE_ENABLED_CAP = TRUE
-WRITE_STATUS = TRUE
-WRITE_LOCK_CAP = TRUE
-WRITE_LOCK_STATUS = TRUE
-READ_DISABLED_CAP = TRUE
-READ_ENABLED_CAP = TRUE
-READ_STATUS = TRUE
-READ_LOCK_CAP = TRUE
-READ_LOCK_STATUS = TRUE
-
-!if $(CFG_SOURCE_DEBUG) == TRUE
- INF QuarkPlatformPkg/Override/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume2Pei.inf
-!endif
-FILE FV_IMAGE = 1E9D7604-EF45-46a0-BD8A-71AC78C17AC1 {
- SECTION PEI_DEPEX_EXP = {gEfiPeiMemoryDiscoveredPpiGuid AND gEfiPeiBootInRecoveryModePpiGuid}
- SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF {
- SECTION FV_IMAGE = FVRECOVERY_COMPONENTS
- }
- }
-
-
-################################################################################
-#
-# FV Section
-#
-# [FV] section is used to define what components or modules are placed within a flash
-# device file. This section also defines order the components and modules are positioned
-# within the image. The [FV] section consists of define statements, set statements and
-# module statements.
-#
-################################################################################
-[FV.FVRECOVERY_COMPONENTS]
+[FV.FVRECOVERY_COMPONENTS]
BlockSize = 0x1000
FvAlignment = 16 #FV alignment and FV attributes setting.
ERASE_POLARITY = 1
@@ -753,9 +578,6 @@ FILE FREEFORM = EE84C5E7-9412-42cc-B755-A915A7B68536 { FILE FREEFORM = E4AD87C8-D20E-40ce-97F5-9756FD0E81D4 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-platform-data.bin
}
-FILE FREEFORM = E27ADA6A-9F8A-4f2e-B09E-4CCDD82C2F54 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin
- }
FILE FREEFORM = 23B3C10D-46E3-4a78-8AAA-217B6A39EF04 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-gen2-platform-data.bin
}
@@ -878,9 +700,6 @@ FILE FREEFORM = EE84C5E7-9412-42cc-B755-A915A7B68536 { FILE FREEFORM = E4AD87C8-D20E-40ce-97F5-9756FD0E81D4 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-platform-data.bin
}
-FILE FREEFORM = E27ADA6A-9F8A-4f2e-B09E-4CCDD82C2F54 {
- SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-fabe-platform-data.bin
- }
FILE FREEFORM = 23B3C10D-46E3-4a78-8AAA-217B6A39EF04 {
SECTION RAW = QuarkPlatformPkg/Binary/PlatformData/galileo-gen2-platform-data.bin
}
@@ -1154,8 +973,17 @@ FvNameGuid = 30D9ED01-38D2-418a-90D5-C561750BF80F # DXE Phase modules
##
INF MdeModulePkg/Core/Dxe/DxeMain.inf
-
INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+#
+# Early SoC / Platform modules. I2C must be loaded before platform init.
+#
+INF QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2CDxe.inf
+INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf
+
+#
+# EDK Core modules.
+#
INF IntelFrameworkModulePkg/Universal/CpuIoDxe/CpuIoDxe.inf
INF UefiCpuPkg/CpuIo2Dxe/CpuIo2Dxe.inf
INF MdeModulePkg/Universal/ReportStatusCodeRouter/RuntimeDxe/ReportStatusCodeRouterRuntimeDxe.inf
@@ -1200,7 +1028,6 @@ INF QuarkSocPkg/QuarkNorthCluster/Smm/Dxe/SmmAccessDxe/SmmAccess.inf INF QuarkSocPkg/QuarkNorthCluster/S3Support/Dxe/QncS3Support.inf
INF QuarkSocPkg/QuarkNorthCluster/Spi/RuntimeDxe/PchSpiRuntime.inf
INF QuarkSocPkg/QuarkNorthCluster/Spi/Smm/PchSpiSmm.inf
-INF QuarkPlatformPkg/Platform/Dxe/PlatformInit/PlatformInitDxe.inf
INF QuarkPlatformPkg/Platform/Dxe/Setup/DxePlatform.inf
#
diff --git a/QuarkPlatformPkg/Tools/CapsuleCreate/QuarkPlatformPkgCapsuleComponents.inf b/QuarkPlatformPkg/Tools/CapsuleCreate/QuarkPlatformPkgCapsuleComponents.inf index a5cd3dc..69ab5c9 100755 --- a/QuarkPlatformPkg/Tools/CapsuleCreate/QuarkPlatformPkgCapsuleComponents.inf +++ b/QuarkPlatformPkg/Tools/CapsuleCreate/QuarkPlatformPkgCapsuleComponents.inf @@ -53,24 +53,19 @@ [Components]
#BEGIN
-# FILE_NAME=CLANTONPEAKCRB.fd
-# START_ADDRESS=0xFFC00000
+# FILE_NAME=QUARK.fd
+# START_ADDRESS=0xFF800000
#END
-#BEGIN
-# FILE_NAME=EDKII_BOOTROM_OVERRIDE.Fv
-# START_ADDRESS=0xFFFE0000
-#END
-
-#BEGIN
-# FILE_NAME=EDKII_RECOVERY_IMAGE1.Fv.signed
-# START_ADDRESS=0xFFF90000
-#END
+BEGIN
+ FILE_NAME=EDKII_RECOVERY_IMAGE1.Fv.signed
+ START_ADDRESS=0xFFF90000
+END
-#BEGIN
-# FILE_NAME=EDKII_RECOVERY_IMAGE2.Fv.signed
-# START_ADDRESS=0xFFF50000
-#END
+BEGIN
+ FILE_NAME=EDKII_BOOTROM_OVERRIDE.Fv
+ START_ADDRESS=0xFFFE0000
+END
BEGIN
FILE_NAME=FlashModules/EDKII_NVRAM.bin
diff --git a/QuarkPlatformPkg/Tools/QuarkSpiFixup/QuarkSpiFixup.py b/QuarkPlatformPkg/Tools/QuarkSpiFixup/QuarkSpiFixup.py index 33db8c1..3d61756 100755 --- a/QuarkPlatformPkg/Tools/QuarkSpiFixup/QuarkSpiFixup.py +++ b/QuarkPlatformPkg/Tools/QuarkSpiFixup/QuarkSpiFixup.py @@ -55,7 +55,7 @@ buildOptionRelease = "RELEASE" QuarkRomBaseAddress = 4294836224 #NVRAM definitions -nvramLocation = 0x330000 +nvramLocation = 0x730000 nvramSize = 0x20000 # Root Directory diff --git a/QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin b/QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin Binary files differindex 4e5c0db..769b138 100755 --- a/QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin +++ b/QuarkSocPkg/QuarkNorthCluster/Binary/Quark2Microcode/RMU.bin diff --git a/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h b/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h index 4f99ed7..d496843 100755 --- a/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h +++ b/QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h @@ -120,7 +120,7 @@ Abstract: #define QUARK_ECC_SCRUB_PAUSE 0xC3 // Quark Remote Management Unit "scrub pause" opcode
//
-// QNC Message Ports and Registers
+// QNC Message Ports and Registers
//
// Start of SB Port IDs
#define QUARK_NC_MEMORY_ARBITER_SB_PORT_ID 0x00
@@ -178,7 +178,6 @@ Abstract: #define V_WDT_CONTROL_DBL_ECC_BIT_ERR_WARM (0x2 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
#define V_WDT_CONTROL_DBL_ECC_BIT_ERR_SERR (0x3 << B_WDT_CONTROL_DBL_ECC_BIT_ERR_BP)
-#define QUARK_NC_RMU_REG_SDMA 0x7A // Remote Management Unit SPI DMA config register
#define QUARK_NC_RMU_REG_TS_MODE 0xB0 // Remote Management Unit Thermal sensor mode register.
#define TS_ENABLE (BIT15)
#define QUARK_NC_RMU_REG_TS_TRIP 0xB2 // Remote Management Unit Thermal sensor programmable trip point register.
@@ -495,7 +494,7 @@ Abstract: #define R_QNC_LPC_GPE0BLK 0x4C
#define B_QNC_LPC_GPE0BLK_MASK 0x0000FFC0
-// Suggested Value for GPE0BLK = 0x10C0
+// Suggested Value for GPE0BLK = 0x10C0
//
#define R_QNC_GPE0BLK_GPE0S 0x00 // General Purpose Event 0 Status
#define S_QNC_GPE0BLK_GPE0S 4
@@ -632,7 +631,7 @@ Abstract: #define R_APM_CNT 0xB2
//
-// Reset Generator I/O Port
+// Reset Generator I/O Port
//
#define RST_CNT 0xCF9
#define B_RST_CNT_COLD_RST (BIT3) // Cold reset
diff --git a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.c b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.c index 5877299..0ecf6b2 100755 --- a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.c +++ b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.c @@ -59,9 +59,6 @@ PeiQNCPreMemInit ( // Sideband register write to Remote Management Unit
QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QNC_MSG_TMPM_REG_PMBA, (BIT31 | PcdGet16 (PcdPmbaIoBaseAddress)));
-
- // Sideband register write to Remote Management Unit
- QNCPortWrite (QUARK_NC_RMU_SB_PORT_ID, QUARK_NC_RMU_REG_SDMA, (BIT31 | PcdGet16 (PcdSpiDmaIoBaseAddress)));
// Configurable I/O address in iLB (legacy block)
diff --git a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf index fb85f1d..6045e94 100755 --- a/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf +++ b/QuarkSocPkg/QuarkNorthCluster/Library/IntelQNCLib/IntelQNCLib.inf @@ -79,7 +79,6 @@ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdPmbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress
- gEfiQuarkNcSocIdTokenSpaceGuid.PcdSpiDmaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress
gEfiQuarkNcSocIdTokenSpaceGuid.PcdDeviceEnables
diff --git a/QuarkSocPkg/QuarkSocPkg.dec b/QuarkSocPkg/QuarkSocPkg.dec index dcb469f..2038a69 100755 --- a/QuarkSocPkg/QuarkSocPkg.dec +++ b/QuarkSocPkg/QuarkSocPkg.dec @@ -188,7 +188,6 @@ gEfiQuarkNcSocIdTokenSpaceGuid.PcdGbaIoBaseAddress|0x1080|UINT16|0x10000205
gEfiQuarkNcSocIdTokenSpaceGuid.PcdGpe0blkIoBaseAddress|0x1100|UINT16|0x10000206
gEfiQuarkNcSocIdTokenSpaceGuid.PcdSmbaIoBaseAddress|0x1040|UINT16|0x10000207
- gEfiQuarkNcSocIdTokenSpaceGuid.PcdSpiDmaIoBaseAddress|0x1020|UINT16|0x10000208
gEfiQuarkNcSocIdTokenSpaceGuid.PcdWdtbaIoBaseAddress|0x1140|UINT16|0x10000209
gEfiQuarkNcSocIdTokenSpaceGuid.PcdRcbaMmioBaseAddress|0xFED1C000|UINT64|0x1000020B
@@ -238,6 +237,9 @@ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohI2cMmioBase|0xA001F000|UINT64|0x20000005
gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiP2PMemoryBaseAddress|0xA0000000|UINT32|0x20000006
gEfiQuarkSCSocIdTokenSpaceGuid.PcdPeiQNCUsbControllerMemoryBaseAddress|0xA0010000|UINT32|0x20000007
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase|0xA0020000|UINT64|0x20000008
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac0MmioBase|0xA0024000|UINT64|0x20000009
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohMac1MmioBase|0xA0028000|UINT64|0x2000000A
# IOH Uart Clock Frequency 44.2368Mhz.
gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartClkFreq|44236800|UINT32|0x20000012
@@ -245,6 +247,10 @@ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartBusNumber|0x00|UINT8|0x20000013
gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartDevNumber|0x14|UINT8|0x20000014
gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohUartFunctionNumber|0x5|UINT8|0x20000001
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber|0x00|UINT8|0x20000029
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber|0x15|UINT8|0x2000002A
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber|0x2|UINT8|0x2000002B
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister|0x14|UINT8|0x2000002D
[PcdsDynamic]
#
diff --git a/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.c b/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.c index c8d13f7..6ad2c41 100644 --- a/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.c +++ b/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.c @@ -152,23 +152,19 @@ EnableI2CMmioSpace ( }
-
/**
The DisableI2CController() functions disables I2C Controller.
- @retval EFI_SUCCESS I2C Controller disabled successfully.
-
- @retval EFI_DEVICE_ERROR I2C Controller could not be disabled.
-
**/
-EFI_STATUS
+VOID
DisableI2CController (
+ VOID
)
{
- UINTN I2CIoPortBaseAddress;
- UINT32 Addr;
- UINT32 Data;
- UINT8 PollCount;
+ UINTN I2CIoPortBaseAddress;
+ UINT32 Addr;
+ UINT32 Data;
+ UINT8 PollCount;
PollCount = 0;
@@ -191,29 +187,31 @@ DisableI2CController ( Data = 0xFF;
Addr = I2CIoPortBaseAddress + I2C_REG_ENABLE_STATUS;
Data = *((volatile UINT32 *) (UINTN)(Addr)) & I2C_REG_ENABLE_STATUS;
-
- if (Data == 0) {
- return EFI_SUCCESS;
- }
-
- //
- // Poll the IC_ENABLE_STATUS.IC_EN Bit to check if Controller is disabled, until timeout (TI2C_POLL*MAX_T_POLL_COUNT).
- //
-PollIcEn:
- PollCount++;
- if (PollCount >= MAX_T_POLL_COUNT) {
- return EFI_DEVICE_ERROR;
- } else {
+ while (Data != 0) {
+ //
+ // Poll the IC_ENABLE_STATUS.IC_EN Bit to check if Controller is disabled, until timeout (TI2C_POLL*MAX_T_POLL_COUNT).
+ //
+ PollCount++;
+ if (PollCount >= MAX_T_POLL_COUNT) {
+ break;
+ }
gBS->Stall(TI2C_POLL);
Data = *((volatile UINT32 *) (UINTN)(Addr));
Data &= I2C_REG_ENABLE_STATUS;
- if (Data == 0) {
- return EFI_SUCCESS;
- } else {
- goto PollIcEn;
- }
}
+ //
+ // Asset if controller does not enter Disabled state.
+ //
+ ASSERT (PollCount < MAX_T_POLL_COUNT);
+
+ //
+ // Read IC_CLR_INTR register to automatically clear the combined interrupt,
+ // all individual interrupts and the IC_TX_ABRT_SOURCE register.
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_INT;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+
}
/**
@@ -222,6 +220,7 @@ PollIcEn: **/
VOID
EnableI2CController (
+ VOID
)
{
UINTN I2CIoPortBaseAddress;
@@ -235,26 +234,48 @@ EnableI2CController ( //
// Enable the I2C Controller by setting IC_ENABLE.ENABLE to 1
- //
+ //
Addr = I2CIoPortBaseAddress + I2C_REG_ENABLE;
Data = *((volatile UINT32 *) (UINTN)(Addr));
Data |= B_I2C_REG_ENABLE;
*((volatile UINT32 *) (UINTN)(Addr)) = Data;
+ //
+ // Clear overflow and abort error status bits before transactions.
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_RX_OVER;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_TX_OVER;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_TX_ABRT;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+
}
/**
The WaitForStopDet() function waits until I2C STOP Condition occurs,
indicating transfer completion.
+ @retval EFI_SUCCESS Stop detected.
+ @retval EFI_TIMEOUT Timeout while waiting for stop condition.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Tx or Rx overflow detected.
+
**/
-VOID
+EFI_STATUS
WaitForStopDet (
+ VOID
)
{
- UINTN I2CIoPortBaseAddress;
- UINT32 Addr;
- UINT32 Data;
+ UINTN I2CIoPortBaseAddress;
+ UINT32 Addr;
+ UINT32 Data;
+ UINT8 PollCount;
+ EFI_STATUS Status;
+
+ Status = EFI_SUCCESS;
+
+ PollCount = 0;
//
// Get I2C Memory Mapped registers base address.
@@ -266,14 +287,34 @@ WaitForStopDet ( //
Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;
-PollStopDet:
- Data = *((volatile UINT32 *) (UINTN)(Addr));
- Data &= I2C_REG_RAW_INTR_STAT_STOP_DET;
- if (Data == 0) {
+ do {
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ if ((Data & I2C_REG_RAW_INTR_STAT_TX_ABRT) != 0) {
+ Status = EFI_ABORTED;
+ break;
+ }
+ if ((Data & I2C_REG_RAW_INTR_STAT_TX_OVER) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+ if ((Data & I2C_REG_RAW_INTR_STAT_RX_OVER) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ break;
+ }
+ if ((Data & I2C_REG_RAW_INTR_STAT_STOP_DET) != 0) {
+ Status = EFI_SUCCESS;
+ break;
+ }
gBS->Stall(TI2C_POLL);
- goto PollStopDet;
- }
+ PollCount++;
+ if (PollCount >= MAX_STOP_DET_POLL_COUNT) {
+ Status = EFI_TIMEOUT;
+ break;
+ }
+
+ } while (TRUE);
+ return Status;
}
/**
@@ -285,9 +326,6 @@ PollStopDet: @retval EFI_SUCCESS I2C Operation completed successfully.
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
-
**/
EFI_STATUS
InitializeInternal (
@@ -309,10 +347,7 @@ InitializeInternal ( //
// Disable I2C Controller initially
//
- Status = DisableI2CController ();
- if (EFI_ERROR (Status)) {
- return Status;
- }
+ DisableI2CController ();
//
// Get I2C Memory Mapped registers base address.
@@ -370,24 +405,25 @@ InitializeInternal ( @param I2CAddress I2C Slave device address
@param Value The 8-bit value to write.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
- @return Data written to I2C Slave device, as read from I2C Data CMD register.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
-UINT8
+EFI_STATUS
EFIAPI
WriteByte (
IN UINTN I2CAddress,
- IN UINT8 Value,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINT8 Value
)
{
- UINTN I2CIoPortBaseAddress;
- UINTN Addr;
- UINT32 Data;
- UINT8 ReturnData;
+ UINTN I2CIoPortBaseAddress;
+ UINTN Addr;
+ UINT32 Data;
+ EFI_STATUS Status;
//
// Get I2C Memory Mapped registers base address
@@ -423,17 +459,14 @@ WriteByte ( //
// Wait for transfer completion.
//
- WaitForStopDet ();
+ Status = WaitForStopDet ();
//
- // Return write data byte from TX/RX buffer (IC_DATA_CMD[7:0]).
- //
- Data = *((volatile UINT32 *) (UINTN)(Addr));
- Data &= 0x000000FF;
- ReturnData = (UINT8)Data;
-
- return ReturnData;
+ // Ensure I2C Controller disabled.
+ //
+ DisableI2CController();
+ return Status;
}
/**
@@ -443,23 +476,26 @@ WriteByte ( sub-addresses), as defined in the I2C Specification.
@param I2CAddress I2C Slave device address
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @param ReturnDataPtr Pointer to location to receive read byte.
- @return Data read from the I2C Slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
-**/
-UINT8
+**/
+EFI_STATUS
EFIAPI
ReadByte (
IN UINTN I2CAddress,
- OUT RETURN_STATUS *Status OPTIONAL
+ OUT UINT8 *ReturnDataPtr
)
{
- UINTN I2CIoPortBaseAddress;
- UINTN Addr;
- UINT32 Data;
- UINT8 ReturnData;
+ UINTN I2CIoPortBaseAddress;
+ UINTN Addr;
+ UINT32 Data;
+ EFI_STATUS Status;
//
// Get I2C Memory Mapped registers base address.
@@ -494,17 +530,37 @@ ReadByte ( //
// Wait for transfer completion
//
- WaitForStopDet ();
+ Status = WaitForStopDet ();
+ if (!EFI_ERROR(Status)) {
+
+ //
+ // Clear RX underflow before reading IC_DATA_CMD.
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_RX_UNDER;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+
+ //
+ // Obtain and return read data byte from RX buffer (IC_DATA_CMD[7:0]).
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Data &= 0x000000FF;
+ *ReturnDataPtr = (UINT8) Data;
+
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Data &= I2C_REG_RAW_INTR_STAT_RX_UNDER;
+ if (Data != 0) {
+ Status = EFI_DEVICE_ERROR;
+ }
+ }
//
- // Obtain and return read data byte from RX buffer (IC_DATA_CMD[7:0]).
+ // Ensure I2C Controller disabled.
//
- Data = *((volatile UINT32 *) (UINTN)(Addr));
- Data &= 0x000000FF;
- ReturnData = (UINT8)Data;
-
- return ReturnData;
+ DisableI2CController ();
+ return Status;
}
/**
@@ -521,23 +577,30 @@ ReadByte ( @param Length No. of bytes to be written.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Tx overflow detected.
**/
-VOID
+EFI_STATUS
EFIAPI
WriteMultipleByte (
IN UINTN I2CAddress,
IN UINT8 *WriteBuffer,
- IN UINTN Length,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN Length
)
{
- UINTN I2CIoPortBaseAddress;
- UINTN Index;
- UINTN Addr;
- UINT32 Data;
+ UINTN I2CIoPortBaseAddress;
+ UINTN Index;
+ UINTN Addr;
+ UINT32 Data;
+ EFI_STATUS Status;
+
+ if (Length > I2C_FIFO_SIZE) {
+ return EFI_UNSUPPORTED; // Routine does not handle xfers > fifo size.
+ }
I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();
@@ -574,15 +637,20 @@ WriteMultipleByte ( //
// Wait for transfer completion
//
- WaitForStopDet ();
+ Status = WaitForStopDet ();
+ //
+ // Ensure I2C Controller disabled.
+ //
+ DisableI2CController ();
+ return Status;
}
/**
The ReadMultipleByte() function provides a standard way to execute
multiple byte writes to an IC2 device (e.g. when accessing sub-addresses or
- when reading block of data), as defined in the I2C Specification (I2C combined
+ when reading block of data), as defined in the I2C Specification (I2C combined
write/read protocol).
@param SlaveAddress The I2C slave address of the device
@@ -593,7 +661,7 @@ WriteMultipleByte ( @param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
- in Hi-Lo format, that need to be read (I2C combined
+ in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
@param ReadLength No. of bytes to be read. I
@@ -604,25 +672,32 @@ WriteMultipleByte ( @param Buffer Contains the value of byte data read from the
I2C slave device.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Rx underflow or Rx/Tx overflow detected.
**/
-VOID
+EFI_STATUS
EFIAPI
ReadMultipleByte (
IN UINTN I2CAddress,
IN OUT UINT8 *Buffer,
IN UINTN WriteLength,
- IN UINTN ReadLength,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN ReadLength
)
{
- UINTN I2CIoPortBaseAddress;
- UINTN Index;
- UINTN Addr;
- UINT32 Data;
- UINT8 PollCount;
+ UINTN I2CIoPortBaseAddress;
+ UINTN Index;
+ UINTN Addr;
+ UINT32 Data;
+ UINT8 PollCount;
+ EFI_STATUS Status;
+
+ if (WriteLength > I2C_FIFO_SIZE || ReadLength > I2C_FIFO_SIZE) {
+ return EFI_UNSUPPORTED; // Routine does not handle xfers > fifo size.
+ }
I2CIoPortBaseAddress = GetI2CIoPortBaseAddress ();
@@ -664,47 +739,76 @@ ReadMultipleByte ( }
*((volatile UINT32 *) (UINTN)(Addr)) = Data;
}
-
+
//
// Wait for STOP condition.
//
- WaitForStopDet ();
+ Status = WaitForStopDet ();
+ if (!EFI_ERROR(Status)) {
- //
- // Poll Receive FIFO Buffer Level register until valid (upto MAX_T_POLL_COUNT times).
- //
- Data = 0;
- PollCount = 0;
- Addr = I2CIoPortBaseAddress + I2C_REG_RXFLR;
- Data = *((volatile UINT32 *) (UINTN)(Addr));
- while ((Data != ReadLength) && (PollCount < MAX_T_POLL_COUNT)) {
- gBS->Stall(TI2C_POLL);
- PollCount++;
+ //
+ // Poll Receive FIFO Buffer Level register until valid (upto MAX_T_POLL_COUNT times).
+ //
+ Data = 0;
+ PollCount = 0;
+ Addr = I2CIoPortBaseAddress + I2C_REG_RXFLR;
Data = *((volatile UINT32 *) (UINTN)(Addr));
- }
-
- //
- // If receive buffer valid output data, otherwise return device error.
- //
- if (PollCount == MAX_T_POLL_COUNT) {
- *Status = EFI_DEVICE_ERROR;
- } else {
- *Status = EFI_SUCCESS;
- Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;
- for (Index = 0; Index < ReadLength; Index++) {
+ while ((Data != ReadLength) && (PollCount < MAX_T_POLL_COUNT)) {
+ gBS->Stall(TI2C_POLL);
+ PollCount++;
Data = *((volatile UINT32 *) (UINTN)(Addr));
- Data &= 0x000000FF;
- *(Buffer+Index) = (UINT8)Data;
+ }
+
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+
+ //
+ // If no timeout or device error then read rx data.
+ //
+ if (PollCount == MAX_T_POLL_COUNT) {
+ Status = EFI_TIMEOUT;
+ } else if ((Data & I2C_REG_RAW_INTR_STAT_RX_OVER) != 0) {
+ Status = EFI_DEVICE_ERROR;
+ } else {
+
+ //
+ // Clear RX underflow before reading IC_DATA_CMD.
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_CLR_RX_UNDER;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+
+ //
+ // Read data.
+ //
+ Addr = I2CIoPortBaseAddress + I2C_REG_DATA_CMD;
+ for (Index = 0; Index < ReadLength; Index++) {
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Data &= 0x000000FF;
+ *(Buffer+Index) = (UINT8)Data;
+ }
+ Addr = I2CIoPortBaseAddress + I2C_REG_RAW_INTR_STAT;
+ Data = *((volatile UINT32 *) (UINTN)(Addr));
+ Data &= I2C_REG_RAW_INTR_STAT_RX_UNDER;
+ if (Data != 0) {
+ Status = EFI_DEVICE_ERROR;
+ } else {
+ Status = EFI_SUCCESS;
+ }
}
}
-}
+ //
+ // Ensure I2C Controller disabled.
+ //
+ DisableI2CController ();
+ return Status;
+}
/**
The I2CWriteByte() function is a wrapper function for the WriteByte function.
- Provides a standard way to execute a standard single byte write to an IC2 device
+ Provides a standard way to execute a standard single byte write to an IC2 device
(without accessing sub-addresses), as defined in the I2C Specification.
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -720,10 +824,12 @@ ReadMultipleByte ( I2C slave device.
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -732,13 +838,16 @@ I2CWriteByte ( IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINTN I2CAddress;
+ if (This != &mI2CbusHc || Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
ServiceEntry ();
Status = EFI_SUCCESS;
@@ -746,12 +855,10 @@ I2CWriteByte ( I2CAddress = SlaveAddress.I2CDeviceAddress;
Status = InitializeInternal (AddrMode);
- if (EFI_ERROR(Status)) {
- return Status;
+ if (!EFI_ERROR(Status)) {
+ Status = WriteByte (I2CAddress, *(UINT8 *) Buffer);
}
- WriteByte (I2CAddress, *(UINT8 *) Buffer, &Status);
-
ServiceExit ();
return Status;
}
@@ -759,7 +866,7 @@ I2CWriteByte ( /**
The I2CReadByte() function is a wrapper function for the ReadByte function.
- Provides a standard way to execute a standard single byte read to an IC2 device
+ Provides a standard way to execute a standard single byte read to an IC2 device
(without accessing sub-addresses), as defined in the I2C Specification.
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -769,16 +876,16 @@ I2CWriteByte ( @param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
- @param Length No. of bytes to be read.
-
@param Buffer Contains the value of byte data read from the
I2C slave device.
- @retval EFI_SUCCESS I2C Operation completed successfully.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
**/
EFI_STATUS
@@ -787,13 +894,16 @@ I2CReadByte ( IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
)
{
EFI_STATUS Status;
UINTN I2CAddress;
+ if (This != &mI2CbusHc || Buffer == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
ServiceEntry ();
Status = EFI_SUCCESS;
@@ -801,12 +911,9 @@ I2CReadByte ( I2CAddress = SlaveAddress.I2CDeviceAddress;
Status = InitializeInternal (AddrMode);
- if (EFI_ERROR(Status)) {
- return Status;
+ if (!EFI_ERROR(Status)) {
+ Status = ReadByte (I2CAddress, (UINT8 *) Buffer);
}
-
- *(UINT8 *) Buffer = ReadByte (I2CAddress, &Status);
-
ServiceExit ();
return Status;
}
@@ -814,8 +921,8 @@ I2CReadByte ( /**
The I2CWriteMultipleByte() function is a wrapper function for the WriteMultipleByte() function.
- Provides a standard way to execute multiple byte writes to an IC2 device
- (e.g. when accessing sub-addresses or writing block of data), as defined
+ Provides a standard way to execute multiple byte writes to an IC2 device
+ (e.g. when accessing sub-addresses or writing block of data), as defined
in the I2C Specification.
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -830,11 +937,12 @@ I2CReadByte ( @param Buffer Contains the value of byte to be written to the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, Length or Buffer pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -850,18 +958,20 @@ I2CWriteMultipleByte ( EFI_STATUS Status;
UINTN I2CAddress;
+ if (This != &mI2CbusHc || Buffer == NULL || Length == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
ServiceEntry ();
Status = EFI_SUCCESS;
I2CAddress = SlaveAddress.I2CDeviceAddress;
Status = InitializeInternal (AddrMode);
- if (EFI_ERROR(Status)) {
- return Status;
+ if (!EFI_ERROR(Status)) {
+ Status = WriteMultipleByte (I2CAddress, Buffer, (*Length));
}
- WriteMultipleByte (I2CAddress, Buffer, (*Length), &Status);
-
ServiceExit ();
return Status;
}
@@ -869,8 +979,8 @@ I2CWriteMultipleByte ( /**
The I2CReadMultipleByte() function is a wrapper function for the ReadMultipleByte() function.
- Provides a standard way to execute multiple byte writes to an IC2 device
- (e.g. when accessing sub-addresses or when reading block of data), as defined
+ Provides a standard way to execute multiple byte writes to an IC2 device
+ (e.g. when accessing sub-addresses or when reading block of data), as defined
in the I2C Specification (I2C combined write/read protocol).
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -882,20 +992,22 @@ I2CWriteMultipleByte ( @param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
- in Hi-Lo format, that need to be read (I2C combined
+ in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
- @param ReadLength No. of bytes to be read from I2C slave device.
+ @param ReadLength No. of bytes to be read from I2C slave device.
need to be read.
@param Buffer Contains the value of byte data read from the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, WriteLength, ReadLength or Buffer
+ pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -912,19 +1024,22 @@ I2CReadMultipleByte ( EFI_STATUS Status;
UINTN I2CAddress;
+ if (This != &mI2CbusHc) {
+ return EFI_INVALID_PARAMETER;
+ }
+ if (Buffer == NULL || WriteLength == NULL || ReadLength == NULL) {
+ return EFI_INVALID_PARAMETER;
+ }
+
ServiceEntry ();
Status = EFI_SUCCESS;
I2CAddress = SlaveAddress.I2CDeviceAddress;
-
Status = InitializeInternal (AddrMode);
- if (EFI_ERROR(Status)) {
- return Status;
+ if (!EFI_ERROR(Status)) {
+ Status = ReadMultipleByte (I2CAddress, Buffer, (*WriteLength), (*ReadLength));
}
-
- ReadMultipleByte(I2CAddress, Buffer, (*WriteLength), (*ReadLength), &Status);
-
ServiceExit ();
return Status;
}
diff --git a/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.h b/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.h index a8ddda3..b1f9878 100644 --- a/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.h +++ b/QuarkSocPkg/QuarkSouthCluster/I2C/Dxe/I2C.h @@ -1,6 +1,7 @@ /** @file
- Provides definition of entry point to the DXE Driver that produces the
- I2C Controller Protocol and definition of protocol functions.
+
+ Provides definition of entry point to the DXE Driver that produces the
+ I2C Controller Protocol and definition of protocol functions.
Copyright (c) 2013 Intel Corporation.
@@ -32,7 +33,6 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. **/
-
#ifndef _I2C_H_
#define _I2C_H_
@@ -44,8 +44,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //
// Constants that define I2C Controller timeout and max. polling time.
//
-#define MAX_T_POLL_COUNT 100
-#define TI2C_POLL 25 // microseconds
+#define MAX_T_POLL_COUNT 100
+#define TI2C_POLL 25 // microseconds
+#define MAX_STOP_DET_POLL_COUNT ((1000 * 1000) / TI2C_POLL) // Extreme for expected Stop detect.
/**
The GetI2CIoPortBaseAddress() function gets IO port base address of I2C Controller.
@@ -60,7 +61,6 @@ GetI2CIoPortBaseAddress ( VOID
);
-
/**
The EnableI2CMmioSpace() function enables access to I2C MMIO space.
@@ -70,21 +70,15 @@ EnableI2CMmioSpace ( VOID
);
-
/**
The DisableI2CController() functions disables I2C Controller.
- @retval EFI_SUCCESS I2C Controller disabled successfully.
-
- @retval EFI_DEVICE_ERROR I2C Controller could not be disabled.
-
**/
-EFI_STATUS
+VOID
DisableI2CController (
VOID
);
-
/**
The EnableI2CController() function enables the I2C Controller.
@@ -94,17 +88,21 @@ EnableI2CController ( VOID
);
-
/**
The WaitForStopDet() function waits until I2C STOP Condition occurs,
indicating transfer completion.
+ @retval EFI_SUCCESS Stop detected.
+ @retval EFI_TIMEOUT Timeout while waiting for stop condition.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Tx or Rx overflow detected.
+
**/
-VOID
+EFI_STATUS
WaitForStopDet (
+ VOID
);
-
/**
The InitializeInternal() function initialises internal I2C Controller
@@ -114,16 +112,12 @@ WaitForStopDet ( @retval EFI_SUCCESS I2C Operation completed successfully.
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
-
**/
EFI_STATUS
InitializeInternal (
IN EFI_I2C_ADDR_MODE AddrMode
);
-
/**
The WriteByte() function provides a standard way to execute a
@@ -132,21 +126,21 @@ InitializeInternal ( @param I2CAddress I2C Slave device address
@param Value The 8-bit value to write.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
- @return Data written to I2C Slave device, as read from I2C Data CMD register.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
-UINT8
+EFI_STATUS
EFIAPI
WriteByte (
IN UINTN I2CAddress,
- IN UINT8 Value,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINT8 Value
);
-
/**
The ReadByte() function provides a standard way to execute a
@@ -154,20 +148,22 @@ WriteByte ( sub-addresses), as defined in the I2C Specification.
@param I2CAddress I2C Slave device address
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @param ReturnDataPtr Pointer to location to receive read byte.
- @return Data read from the I2C Slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
-**/
-UINT8
+**/
+EFI_STATUS
EFIAPI
ReadByte (
IN UINTN I2CAddress,
- OUT RETURN_STATUS *Status OPTIONAL
+ OUT UINT8 *ReturnDataPtr
);
-
/**
The WriteMultipleByte() function provides a standard way to execute
@@ -182,25 +178,26 @@ ReadByte ( @param Length No. of bytes to be written.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Tx overflow detected.
**/
-VOID
+EFI_STATUS
EFIAPI
WriteMultipleByte (
IN UINTN I2CAddress,
IN UINT8 *WriteBuffer,
- IN UINTN Length,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN Length
);
-
/**
The ReadMultipleByte() function provides a standard way to execute
multiple byte writes to an IC2 device (e.g. when accessing sub-addresses or
- when reading block of data), as defined in the I2C Specification (I2C combined
+ when reading block of data), as defined in the I2C Specification (I2C combined
write/read protocol).
@param SlaveAddress The I2C slave address of the device
@@ -211,34 +208,35 @@ WriteMultipleByte ( @param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
- in Hi-Lo format, that need to be read (I2C combined
+ in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
@param ReadLength No. of bytes to be read.
- @param ReadLength No. of bytes to be read from I2C slave device.
+ @param ReadLength No. of bytes to be read from I2C slave device.
need to be read.
@param Buffer Contains the value of byte data read from the
I2C slave device.
- @param Status Return status for the executed command (EFI_SUCCESS or EFI_DEVICE_ERROR).
- This is an optional parameter and may be NULL.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Tx abort signaled in HW status register.
+ @retval EFI_DEVICE_ERROR Rx underflow or Rx/Tx overflow detected.
**/
-VOID
+EFI_STATUS
EFIAPI
ReadMultipleByte (
IN UINTN I2CAddress,
IN OUT UINT8 *Buffer,
IN UINTN WriteLength,
- IN UINTN ReadLength,
- OUT RETURN_STATUS *Status OPTIONAL
+ IN UINTN ReadLength
);
-
/**
-
+
The I2CWriteByte() function is a wrapper function for the WriteByte() function.
Provides a standard way to execute a standard single byte write to an IC2 device
(without accessing sub-addresses), as defined in the I2C Specification.
@@ -256,10 +254,11 @@ ReadMultipleByte ( I2C slave device.
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -267,15 +266,13 @@ I2CWriteByte ( IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
);
-
/**
The I2CReadByte() function is a wrapper function for the ReadByte() function.
- Provides a standard way to execute a standard single byte read to an IC2 device
+ Provides a standard way to execute a standard single byte read to an IC2 device
(without accessing sub-addresses), as defined in the I2C Specification.
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -291,10 +288,11 @@ I2CWriteByte ( I2C slave device.
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -302,11 +300,9 @@ I2CReadByte ( IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
);
-
/**
The I2CWriteMultipleByte() function is a wrapper function for the WriteMultipleByte() function.
@@ -325,11 +321,12 @@ I2CReadByte ( @param Buffer Contains the value of byte to be written to the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, Length or Buffer pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -341,12 +338,11 @@ I2CWriteMultipleByte ( IN OUT VOID *Buffer
);
-
/**
The I2CReadMultipleByte() function is a wrapper function for the ReadMultipleByte function.
- Provides a standard way to execute multiple byte writes to an IC2 device
- (e.g. when accessing sub-addresses or when reading block of data), as defined
+ Provides a standard way to execute multiple byte writes to an IC2 device
+ (e.g. when accessing sub-addresses or when reading block of data), as defined
in the I2C Specification (I2C combined write/read protocol).
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -358,20 +354,22 @@ I2CWriteMultipleByte ( @param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
- in Hi-Lo format, that need to be read (I2C combined
+ in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
- @param ReadLength No. of bytes to be read from I2C slave device.
+ @param ReadLength No. of bytes to be read from I2C slave device.
need to be read.
@param Buffer Contains the value of byte data read from the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, WriteLength, ReadLength or Buffer
+ pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
EFI_STATUS
@@ -384,7 +382,6 @@ I2CReadMultipleByte ( IN OUT VOID *Buffer
);
-
/**
Entry point to the DXE Driver that produces the I2C Controller Protocol.
diff --git a/QuarkSocPkg/QuarkSouthCluster/Include/I2CRegs.h b/QuarkSocPkg/QuarkSouthCluster/Include/I2CRegs.h index 8429586..ddc07bf 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Include/I2CRegs.h +++ b/QuarkSocPkg/QuarkSouthCluster/Include/I2CRegs.h @@ -37,7 +37,7 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. //----------------------------------------------------------------------------
// I2C Controller B:D:F
//----------------------------------------------------------------------------
-#define I2C_Bus 0x00
+#define I2C_Bus 0x00
#define I2C_Device 0x15
#define I2C_Func 0x02
@@ -61,7 +61,11 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define B_I2C_REG_INTR_STAT_STOP_DET (BIT9) // Interrupt Status Register STOP_DET signal status
#define I2C_REG_INTR_MASK 0x30 // Interrupt Status Mask Register
#define I2C_REG_RAW_INTR_STAT 0x34 // Raw Interrupt Status Register
-#define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status
+#define I2C_REG_RAW_INTR_STAT_STOP_DET (BIT9) // Raw Interrupt Status Register STOP_DET signal status.
+#define I2C_REG_RAW_INTR_STAT_TX_ABRT (BIT6) // Raw Interrupt Status Register TX Abort status.
+#define I2C_REG_RAW_INTR_STAT_TX_OVER (BIT3) // Raw Interrupt Status Register TX Overflow signal status.
+#define I2C_REG_RAW_INTR_STAT_RX_OVER (BIT1) // Raw Interrupt Status Register RX Overflow signal status.
+#define I2C_REG_RAW_INTR_STAT_RX_UNDER (BIT0) // Raw Interrupt Status Register RX Underflow signal status.
#define I2C_REG_RX_TL 0x38 // Receive FIFO Threshold Level Register
#define I2C_REG_TX_TL 0x3C // Transmit FIFO Threshold Level Register
#define I2C_REG_CLR_INT 0x40 // Clear Combined and Individual Interrupt Register
@@ -87,4 +91,9 @@ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. #define I2C_REG_ENABLE_STATUS 0x9C // Enable Status Register
#define I2C_REG_FS_SPKLEN 0xA0 // SS and FS Spike Suppression Limit Register
+//
+// Features.
+//
+#define I2C_FIFO_SIZE 16
+
#endif
diff --git a/QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h b/QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h index d1f8b88..3eb0cb5 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h +++ b/QuarkSocPkg/QuarkSouthCluster/Include/Ioh.h @@ -240,15 +240,11 @@ Revision History: //---------------------------------------------------------------------------
// Quark I2C / GPIO definitions
//---------------------------------------------------------------------------
-#define IOH_I2C_GPIO_BUS_NUMBER 0x00
-#define IOH_I2C_GPIO_DEVICE_NUMBER 0x15
-#define IOH_I2C_GPIO_FUNCTION_NUMBER 0x02
#define V_IOH_I2C_GPIO_VENDOR_ID INTEL_VENDOR_ID
#define V_IOH_I2C_GPIO_DEVICE_ID 0x0934
#define R_IOH_I2C_MEMBAR 0x10
-#define R_IOH_GPIO_MEMBAR 0x14
#define B_IOH_I2C_GPIO_MEMBAR_ADDR_MASK 0xFFFFF000 // [31:12].
#define GPIO_SWPORTA_DR 0x00
diff --git a/QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h b/QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h index 5a3a0e8..be86880 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h +++ b/QuarkSocPkg/QuarkSouthCluster/Include/Library/IohLib.h @@ -1,5 +1,5 @@ /** @file
- Library that provides Soc specific library services in PEI phase
+ Library that provides Soc specific library services for SouthCluster devices.
Copyright (c) 2013 Intel Corporation.
@@ -42,6 +42,12 @@ EFIAPI EnableUsbMemIoBusMaster (
IN UINT8 UsbBusNumber
);
-
+
+UINT32
+EFIAPI
+ReadIohGpioValues (
+ VOID
+ );
+
#endif
diff --git a/QuarkSocPkg/QuarkSouthCluster/Include/Protocol/I2CHc.h b/QuarkSocPkg/QuarkSouthCluster/Include/Protocol/I2CHc.h index a136ba1..72e9c6f 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Include/Protocol/I2CHc.h +++ b/QuarkSocPkg/QuarkSouthCluster/Include/Protocol/I2CHc.h @@ -1,5 +1,5 @@ /** @file
- The file provides defintion of I2C host controller management
+ The file provides defintion of I2C host controller management
functions and data transactions over the I2C Bus.
Copyright (c) 2013 Intel Corporation.
@@ -59,7 +59,7 @@ typedef enum _EFI_I2C_ADDR_MODE { } EFI_I2C_ADDR_MODE;
/**
-
+
The WriteByte() function provides a standard way to execute a
standard single byte write to an IC2 device (without accessing
sub-addresses), as defined in the I2C Specification.
@@ -71,16 +71,14 @@ typedef enum _EFI_I2C_ADDR_MODE { @param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
- @param Length No. of bytes to be written.
-
@param Buffer Contains the value of byte data to execute to the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
typedef
@@ -89,7 +87,6 @@ EFI_STATUS IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
);
@@ -106,16 +103,14 @@ EFI_STATUS @param AddrMode I2C Addressing Mode: 7-bit or 10-bit address.
- @param Length No. of bytes to be read.
-
@param Buffer Contains the value of byte data read from the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This or Buffer pointers are invalid.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
typedef
@@ -124,7 +119,6 @@ EFI_STATUS IN CONST EFI_I2C_HC_PROTOCOL *This,
IN EFI_I2C_DEVICE_ADDRESS SlaveAddress,
IN EFI_I2C_ADDR_MODE AddrMode,
- IN UINTN *Length,
IN OUT VOID *Buffer
);
@@ -146,11 +140,12 @@ EFI_STATUS @param Buffer Contains the value of byte to be written to the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, Length or Buffer pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
typedef
@@ -167,7 +162,7 @@ EFI_STATUS The ReadMultipleByte() function provides a standard way to execute
multiple byte writes to an IC2 device (e.g. when accessing sub-addresses
- or when reading block of data), as defined in the I2C Specification
+ or when reading block of data), as defined in the I2C Specification
(I2C combined write/read protocol).
@param This A pointer to the EFI_I2C_PROTOCOL instance.
@@ -179,20 +174,22 @@ EFI_STATUS @param WriteLength No. of bytes to be written. In this case data
written typically contains sub-address or sub-addresses
- in Hi-Lo format, that need to be read (I2C combined
+ in Hi-Lo format, that need to be read (I2C combined
write/read protocol).
- @param ReadLength No. of bytes to be read from I2C slave device.
+ @param ReadLength No. of bytes to be read from I2C slave device.
need to be read.
@param Buffer Contains the value of byte data read from the
I2C slave device.
-
- @retval EFI_SUCCESS I2C Operation completed successfully.
-
- @retval EFI_DEVICE_ERROR The request was not completed due to error
- accessing the slave device.
+ @retval EFI_SUCCESS Transfer success.
+ @retval EFI_INVALID_PARAMETER This, WriteLength, ReadLength or Buffer
+ pointers are invalid.
+ @retval EFI_UNSUPPORTED Unsupported input param.
+ @retval EFI_TIMEOUT Timeout while waiting xfer.
+ @retval EFI_ABORTED Controller aborted xfer.
+ @retval EFI_DEVICE_ERROR Device error detected by controller.
**/
typedef
@@ -206,7 +203,6 @@ EFI_STATUS IN OUT VOID *Buffer
);
-
//
// The EFI_I2C_HC_PROTOCOL provides I2C host controller management and basic data
// transactions over I2C. There is one EFI_I2C_HC_PROTOCOL instance for each I2C
@@ -219,7 +215,6 @@ struct _EFI_I2C_HC_PROTOCOL { EFI_I2C_READ_MULTIPLE_BYTE_OPERATION ReadMultipleByte;
};
-
extern EFI_GUID gEfiI2CHcProtocolGuid;
#endif
diff --git a/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c b/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c index 195c7b8..a6b2c18 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c +++ b/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.c @@ -46,36 +46,81 @@ InitializeIohSsvidSsid ( IN UINT8 Func
)
{
- UINTN j = 0;
+ UINTN Index;
- for (j = 0; j <= PCI_IOSF2AHB_0_MAX_FUNCS; j++)
- {
- if (((Device == PCI_IOSF2AHB_1_DEV_NUM) && (j >= PCI_IOSF2AHB_1_MAX_FUNCS)))
- {
- continue;
- }
+ for (Index = 0; Index <= PCI_IOSF2AHB_0_MAX_FUNCS; Index++) {
+ if (((Device == PCI_IOSF2AHB_1_DEV_NUM) && (Index >= PCI_IOSF2AHB_1_MAX_FUNCS))) {
+ continue;
+ }
- IohMmPci32(0, Bus, Device, j, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, j, PCI_REG_VID);
- }
+ IohMmPci32(0, Bus, Device, Index, PCI_REG_SVID0) = IohMmPci32(0, Bus, Device, Index, PCI_REG_VID);
+ }
- return EFI_SUCCESS;
+ return EFI_SUCCESS;
}
/* Enable memory, io, and bus master for USB controller */
VOID
EFIAPI
EnableUsbMemIoBusMaster (
- IN UINT8 UsbBusNumber
+ IN UINT8 UsbBusNumber
)
{
UINT16 CmdReg;
- CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
- CmdReg = (UINT16) (CmdReg | 0x7);
- PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
+ CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
+ CmdReg = (UINT16) (CmdReg | 0x7);
+ PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_OHCI_DEVICE_NUMBER, IOH_OHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
- CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
- CmdReg = (UINT16) (CmdReg | 0x7);
- PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
+ CmdReg = PciRead16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD));
+ CmdReg = (UINT16) (CmdReg | 0x7);
+ PciWrite16 (PCI_LIB_ADDRESS (UsbBusNumber, IOH_USB_EHCI_DEVICE_NUMBER, IOH_EHCI_FUNCTION_NUMBER, PCI_REG_PCICMD), CmdReg);
}
+/**
+ Read south cluster GPIO input from Port A.
+
+**/
+UINT32
+EFIAPI
+ReadIohGpioValues (
+ VOID
+ )
+{
+ UINT32 GipData;
+ UINT32 GipAddr;
+ UINT32 TempBarAddr;
+ UINT16 SaveCmdReg;
+ UINT32 SaveBarReg;
+
+ TempBarAddr = (UINT32) PcdGet64(PcdIohGpioMmioBase);
+
+ GipAddr = PCI_LIB_ADDRESS(
+ PcdGet8 (PcdIohGpioBusNumber),
+ PcdGet8 (PcdIohGpioDevNumber),
+ PcdGet8 (PcdIohGpioFunctionNumber), 0);
+
+ //
+ // Save current settings for PCI CMD/BAR registers.
+ //
+ SaveCmdReg = PciRead16 (GipAddr + PCI_COMMAND_OFFSET);
+ SaveBarReg = PciRead32 (GipAddr + PcdGet8 (PcdIohGpioBarRegister));
+
+ DEBUG ((EFI_D_INFO, "SC GPIO temporary enable at %08X\n", TempBarAddr));
+
+ // Use predefined tempory memory resource.
+ PciWrite32 ( GipAddr + PcdGet8 (PcdIohGpioBarRegister), TempBarAddr);
+ PciWrite8 ( GipAddr + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEMORY_SPACE);
+
+ // Read GPIO configuration
+ GipData = MmioRead32(TempBarAddr + GPIO_EXT_PORTA);
+
+ //
+ // Restore settings for PCI CMD/BAR registers.
+ //
+ PciWrite32 ((GipAddr + PcdGet8 (PcdIohGpioBarRegister)), SaveBarReg);
+ PciWrite16 (GipAddr + PCI_COMMAND_OFFSET, SaveCmdReg);
+
+ // Only 8 bits valid.
+ return GipData & 0x000000FF;
+}
diff --git a/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf b/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf index 782b506..fa1b221 100644 --- a/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf +++ b/QuarkSocPkg/QuarkSouthCluster/Library/IohLib/IohLib.inf @@ -65,3 +65,11 @@ PciCf8Lib
BaseLib
CpuLib
+
+[FixedPcd]
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBusNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioDevNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioFunctionNumber
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioBarRegister
+ gEfiQuarkSCSocIdTokenSpaceGuid.PcdIohGpioMmioBase
diff --git a/quarkbuild.bat b/quarkbuild.bat index 03abcfd..f0fc74f 100755 --- a/quarkbuild.bat +++ b/quarkbuild.bat @@ -55,6 +55,22 @@ subst /d %SUBSTDRIVE% subst %SUBSTDRIVE% %CURRENTDIR%
%SUBSTDRIVE%
+@REM ###########################################################################
+@REM ######################## PreSetup-processing ######################
+@REM ###########################################################################
+if NOT exist %SUBSTDRIVE%\Conf (
+ mkdir %SUBSTDRIVE%\Conf
+)
+
+if NOT exist %SUBSTDRIVE%\Conf\tools_def.txt (
+ echo copying ... tools_def.template to %SUBSTDRIVE%\Conf\tools_def.txt
+ copy /Y %SUBSTDRIVE%\QuarkPlatformPkg\Override\BaseTools\Conf\tools_def.template %SUBSTDRIVE%\Conf\tools_def.txt > nul
+)
+if NOT exist %SUBSTDRIVE%\Conf\build_rule.txt (
+ echo copying ... build_rule.template to %SUBSTDRIVE%\Conf\build_rule.txt
+ copy /Y %SUBSTDRIVE%QuarkPlatformPkg\Override\BaseTools\Conf\build_rule.template %SUBSTDRIVE%\Conf\build_rule.txt > nul
+)
+
@if not defined WORKSPACE (
call %SUBSTDRIVE%\edksetup.bat
)
@@ -118,24 +134,14 @@ if %ERRORLEVEL% NEQ 0 ( :GotCMC
-@REM ###############################################################################
-@REM ######################## PreBuild-processing ######################
-@REM ###############################################################################
+@REM ###########################################################################
+@REM ######################## PreBuild-processing ######################
+@REM ###########################################################################
if NOT exist %WORKSPACE%\Conf (
echo Error: Missing folder %WORKSPACE%\Conf\
goto End
-) else (
- if exist %WORKSPACE%\QuarkPlatformPkg\Override\BaseTools\Conf\tools_def.template (
- echo copying ... tools_def.template to %WORKSPACE%\Conf\tools_def.txt
- copy /Y %WORKSPACE%\QuarkPlatformPkg\Override\BaseTools\Conf\tools_def.template %WORKSPACE%\Conf\tools_def.txt > nul
- )
- if exist %WORKSPACE%\QuarkPlatformPkg\Override\BaseTools\Conf\build_rule.template (
- echo copying ... build_rule.template to %WORKSPACE%\Conf\build_rule.txt
- copy /Y %WORKSPACE%\QuarkPlatformPkg\Override\BaseTools\Conf\build_rule.template %WORKSPACE%\Conf\build_rule.txt > nul
- )
)
-
@if not exist Build\%PLATFORM%\%TARGET%_%VS_VERSION%%VS_X86%\IA32 (
mkdir Build\%PLATFORM%\%TARGET%_%VS_VERSION%%VS_X86%\IA32
)
@@ -152,40 +158,45 @@ if %ERRORLEVEL% NEQ 0 ( set MY_ERROR_LVL=%ERRORLEVEL% & Goto End ) @REM ###############################################################################
.\QuarkPlatformPkg\Tools\QuarkSpiFixup\QuarkSpiFixup.py %PLATFORM% %TARGET% %VS_VERSION%%VS_X86%
+@REM ####################################################################################################################
+@REM ###### Perform EDKII build again after QuarkSpiFixup so that output .fd file usable. #############
+@REM ###### Warning: parameters here are supposed to override any corresponding value in Conf/target.txt #############
+@REM ####################################################################################################################
+build -p %PLATFORM%Pkg\%PLATFORM%Pkg.dsc -b %TARGET% -a IA32 -n 4 -t %VS_VERSION%%VS_X86% -y Report.log %EDK_PARAMS% %DEBUG_PRINT_ERROR_LEVEL% %DEBUG_PROPERTY_MASK%
+if %ERRORLEVEL% NEQ 0 ( set MY_ERROR_LVL=%ERRORLEVEL% & Goto End )
+
+set OutputModulesDir=%WORKSPACE%\Build\%PLATFORM%\%TARGET%_%VS_VERSION%%VS_X86%\FV
+
+@REM Copy build output .fd file int0 FlashModules directory.
+@REM Use similar name to full Quark Spi Flash tools but emphasise only EDKII assets in bin file.
+copy /Y %OutputModulesDir%\QUARK.fd %OutputModulesDir%\FlashModules\Flash-EDKII-missingPDAT.bin
+
@REM ###############################################################################
@REM ######################## Image signing stage ####################
@REM ######################## (dummy signing) ####################
@REM ###############################################################################
-set OutputModulesDir=%WORKSPACE%\Build\%PLATFORM%\%TARGET%_%VS_VERSION%%VS_X86%\FV
-
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_BOOT_STAGE1_IMAGE1.Fv %OutputModulesDir%\EDKII_BOOT_STAGE1_IMAGE1.Fv.signed
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_BOOT_STAGE1_IMAGE2.Fv %OutputModulesDir%\EDKII_BOOT_STAGE1_IMAGE2.Fv.signed
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_BOOT_STAGE2_RECOVERY.Fv %OutputModulesDir%\EDKII_BOOT_STAGE2_RECOVERY.Fv.signed
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_BOOT_STAGE2_COMPACT.Fv %OutputModulesDir%\EDKII_BOOT_STAGE2_COMPACT.Fv.signed
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_BOOT_STAGE2.Fv %OutputModulesDir%\EDKII_BOOT_STAGE2.Fv.signed
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_RECOVERY_IMAGE1.Fv %OutputModulesDir%\EDKII_RECOVERY_IMAGE1.Fv.signed
-%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %OutputModulesDir%\FlashModules\EDKII_RECOVERY_IMAGE2.Fv %OutputModulesDir%\EDKII_RECOVERY_IMAGE2.Fv.signed
@REM ###############################################################################
@REM #################### Capsule creation stage ################
@REM #################### (Recovery and Update capsules) ################
@REM ###############################################################################
set CapsuleConfigFile=%WORKSPACE%\%PLATFORM%Pkg\Tools\CapsuleCreate\%PLATFORM%PkgCapsuleComponents.inf
-set CapsuleOutputFileNoReset=%OutputModulesDir%\%PLATFORM%PkgNoReset.Cap
set CapsuleOutputFileReset=%OutputModulesDir%\%PLATFORM%PkgReset.Cap
@REM CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000
@REM CAPSULE_FLAGS_INITIATE_RESET 0x00040000
-set CapsuleFlagsNoReset=0x00000000
set CapsuleFlagsReset=0x00050000
-%WORKSPACE%\QuarkPlatformPkg\Tools\CapsuleCreate\CapsuleCreate.exe %CapsuleConfigFile% %OutputModulesDir% %CapsuleOutputFileNoReset% %CapsuleFlagsNoReset%
%WORKSPACE%\QuarkPlatformPkg\Tools\CapsuleCreate\CapsuleCreate.exe %CapsuleConfigFile% %OutputModulesDir% %CapsuleOutputFileReset% %CapsuleFlagsReset%
%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %CapsuleOutputFileReset% %CapsuleOutputFileReset%.signed
-%WORKSPACE%\QuarkPlatformPkg\Tools\SignTool\DummySignTool.exe %CapsuleOutputFileNoReset% %CapsuleOutputFileNoReset%.signed
-
-copy /b /Y %OutputModulesDir%\EDKII_BOOT_STAGE2_RECOVERY.Fv.signed + %CapsuleOutputFileReset%.signed %OutputModulesDir%\FVMAIN.fv > nul
+copy /b /Y %OutputModulesDir%\EDKII_BOOT_STAGE2_RECOVERY.Fv.signed + %CapsuleOutputFileReset%.signed %OutputModulesDir%\FVMAIN.fv > nul
@REM ###############################################################################
@REM ################ Create useful output directories ################
@@ -195,22 +206,22 @@ copy /b /Y %OutputModulesDir%\EDKII_BOOT_STAGE2_RECOVERY.Fv.signed + %CapsuleOut )
@REM Copy the 'Recovery Capsule' and 'Update Capsules' to the RemediationModules directory
+@REM Use same/similar names in stand-alone builds compared to full Quark Spi Flash tools.
copy /Y %OutputModulesDir%\FVMAIN.fv %OutputModulesDir%\RemediationModules\.
-copy /Y %CapsuleOutputFileReset%.signed %OutputModulesDir%\RemediationModules\.
-copy /Y %CapsuleOutputFileNoReset%.signed %OutputModulesDir%\RemediationModules\.
+copy /Y %CapsuleOutputFileReset%.signed %OutputModulesDir%\RemediationModules\Flash-EDKII.cap
copy /Y %WORKSPACE%\QuarkPlatformPkg\Applications\CapsuleApp.efi %OutputModulesDir%\RemediationModules\.
@if not exist %OutputModulesDir%\Tools (
mkdir %OutputModulesDir%\Tools
)
-
+
@REM Copy the 'CapsuleCreate.exe' tool to the Tools directory
copy /Y %WORKSPACE%\QuarkPlatformPkg\Tools\CapsuleCreate\CapsuleCreate.exe %OutputModulesDir%\Tools\.
@if not exist %OutputModulesDir%\Applications (
mkdir %OutputModulesDir%\Applications
)
-
+
@REM Copy the 'CapsuleApp.efi' application to the Applications directory
copy /Y %WORKSPACE%\QuarkPlatformPkg\Applications\CapsuleApp.efi %OutputModulesDir%\Applications\.
@@ -229,4 +240,3 @@ subst /d %SUBSTDRIVE% echo.
exit /b %MY_ERROR_LVL%
-
diff --git a/quarkbuild.sh b/quarkbuild.sh index 7c535d1..6888700 100755 --- a/quarkbuild.sh +++ b/quarkbuild.sh @@ -50,23 +50,27 @@ build_all() mkdir -p Conf + + ############################################################################## + ######################## PreBuild-processing ##################### + ############################################################################## + + # Provide default config files when the user has not + for cfgf in tools_def build_rule; do + + [ -e ./Conf/"${cfgf}".txt ] || + cp -f ./QuarkPlatformPkg/Override/BaseTools/Conf/"${cfgf}".template ./Conf/"${cfgf}".txt + + done + make -C BaseTools # This defines EDK_TOOLS_PATH=..../BaseTools and others + # Note: this script will also provide all the other default Conf/ + # files (from BaseTools/), i.e., all config files besides the ones + # we provided just above . ./edksetup.sh - ############################################################################### - ######################## PreBuild-processing ###################### - ############################################################################### - if [ -e $WORKSPACE/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template ] - then - cp -f $WORKSPACE/QuarkPlatformPkg/Override/BaseTools/Conf/tools_def.template $WORKSPACE/Conf/tools_def.txt - fi - if [ -e $WORKSPACE/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template ] - then - cp -f $WORKSPACE/QuarkPlatformPkg/Override/BaseTools/Conf/build_rule.template $WORKSPACE/Conf/build_rule.txt - fi - local thread_number_opt='' if test -n "${THREAD_NUMBER}"; then thread_number_opt="-n ${THREAD_NUMBER}" @@ -85,15 +89,25 @@ build_all() ./QuarkPlatformPkg/Tools/QuarkSpiFixup/QuarkSpiFixup.py $platform $target $tool_opt + #################################################################################################################### + ###### Perform EDKII build again after QuarkSpiFixup so that output .fd file usable. ############# + ###### Warning: parameters here are supposed to override any corresponding value in Conf/target.txt ############# + #################################################################################################################### + build -p ${platform}Pkg/${platform}Pkg.dsc -b ${target} -a IA32 ${thread_number_opt} -t $tool_opt -y Report.log $_args ${debug_print_error_level} ${debug_property_mask} + + OutputModulesDir=$WORKSPACE/Build/${platform}/${target}_$tool_opt/FV + + # Copy build output .fd file int0 FlashModules directory. + # Use similar name to full Quark Spi Flash tools but emphasise only EDKII assets in bin file. + cp -f $OutputModulesDir/QUARK.fd $OutputModulesDir/FlashModules/Flash-EDKII-missingPDAT.bin + ############################################################################### ######################## Image signing stage #################### ######################## (dummy signing) #################### ############################################################################### - OutputModulesDir=$WORKSPACE/Build/${platform}/${target}_$tool_opt/FV - - if [ ! -e $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ] + if [ ! -e $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ] then - make -C $WORKSPACE/QuarkPlatformPkg/Tools/SignTool + make -C $WORKSPACE/QuarkPlatformPkg/Tools/SignTool fi $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ${OutputModulesDir}/FlashModules/EDKII_BOOT_STAGE1_IMAGE1.Fv $OutputModulesDir/EDKII_BOOT_STAGE1_IMAGE1.Fv.signed @@ -102,36 +116,31 @@ build_all() $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ${OutputModulesDir}/FlashModules/EDKII_BOOT_STAGE2_COMPACT.Fv $OutputModulesDir/EDKII_BOOT_STAGE2_COMPACT.Fv.signed $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ${OutputModulesDir}/FlashModules/EDKII_BOOT_STAGE2.Fv $OutputModulesDir/EDKII_BOOT_STAGE2.Fv.signed $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ${OutputModulesDir}/FlashModules/EDKII_RECOVERY_IMAGE1.Fv $OutputModulesDir/EDKII_RECOVERY_IMAGE1.Fv.signed - $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool ${OutputModulesDir}/FlashModules/EDKII_RECOVERY_IMAGE2.Fv $OutputModulesDir/EDKII_RECOVERY_IMAGE2.Fv.signed - ############################################################################### #################### Capsule creation stage ################ #################### (Recovery and Update capsules) ################ ############################################################################### CapsuleConfigFile=$WORKSPACE/${platform}Pkg/Tools/CapsuleCreate/${platform}PkgCapsuleComponents.inf - CapsuleOutputFileNoReset=$OutputModulesDir/${platform}PkgNoReset.Cap CapsuleOutputFileReset=$OutputModulesDir/${platform}PkgReset.Cap # CAPSULE_FLAGS_PERSIST_ACROSS_RESET 0x00010000 # CAPSULE_FLAGS_INITIATE_RESET 0x00040000 CapsuleFlagsNoReset=0x00000000 CapsuleFlagsReset=0x00050000 - + if [ ! -e $WORKSPACE/QuarkPlatformPkg/Tools/CapsuleCreate/CapsuleCreate ] then make -C $WORKSPACE/QuarkPlatformPkg/Tools/CapsuleCreate fi - + if [ -e $WORKSPACE/${platform}Pkg/Tools/CapsuleCreate/${platform}PkgCapsuleComponents.inf ] then - $WORKSPACE/QuarkPlatformPkg/Tools/CapsuleCreate/CapsuleCreate $CapsuleConfigFile $OutputModulesDir $CapsuleOutputFileNoReset $CapsuleFlagsNoReset $WORKSPACE/QuarkPlatformPkg/Tools/CapsuleCreate/CapsuleCreate $CapsuleConfigFile $OutputModulesDir $CapsuleOutputFileReset $CapsuleFlagsReset fi - + $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool $CapsuleOutputFileReset ${CapsuleOutputFileReset}.signed - $WORKSPACE/QuarkPlatformPkg/Tools/SignTool/DummySignTool $CapsuleOutputFileNoReset ${CapsuleOutputFileNoReset}.signed cat $OutputModulesDir/EDKII_BOOT_STAGE2_RECOVERY.Fv.signed $CapsuleOutputFileReset.signed > $OutputModulesDir/FVMAIN.fv - + ############################################################################### ################ Create useful output directories ################ ############################################################################### @@ -140,13 +149,13 @@ build_all() then mkdir $OutputModulesDir/RemediationModules fi - + # Copy the 'Recovery Capsule' and 'Update Capsules' to the RemediationModules directory + # Use same/similar names in stand-alone builds compared to full Quark Spi Flash tools. cp -f $OutputModulesDir/FVMAIN.fv $OutputModulesDir/RemediationModules/. - cp -f ${CapsuleOutputFileReset}.signed $OutputModulesDir/RemediationModules/. - cp -f ${CapsuleOutputFileNoReset}.signed $OutputModulesDir/RemediationModules/. + cp -f ${CapsuleOutputFileReset}.signed $OutputModulesDir/RemediationModules/Flash-EDKII.cap cp -f $WORKSPACE/QuarkPlatformPkg/Applications/CapsuleApp.efi $OutputModulesDir/RemediationModules/. - + # Create Tools directory if [ ! -e $OutputModulesDir/Tools ] then |