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| author | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2019-04-01 19:45:12 +0900 |
|---|---|---|
| committer | Takeshi Kihara <takeshi.kihara.df@renesas.com> | 2019-04-01 20:34:12 +0900 |
| commit | 915233498bcfac9369169af32d4b49625d61db35 (patch) | |
| tree | 7122ac3cc76bae968d77cf877e9164a8f6e398d9 | |
| parent | de462a6e5630bb3abe28e0eeb13f95e953fca50c (diff) | |
| download | renesas-bsp-915233498bcfac9369169af32d4b49625d61db35.tar.gz | |
Revert "arm64: dts: r8a77990: Connect SDHI to IPMMU-DS1"
This reverts commit 2cdef56231d3098a413528456fb958d236f82937.
Multiple IPMMUs can not be operated simultaneously due to H3 Ver.1.x,
H3 Ver.2.0, M3 Ver.1.x hardware restriction.
E3 has no similar hardware restriction, but disables IPMMU for SoCs
that have hardware restriction.
As a result, This reverts commit 2cdef56231d3 ("arm64: dts: r8a77990:
Connect SDHI to IPMMU-DS1") to keep IPMMU for SDHI{0,1,3} is disabled by
default.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@renesas.com>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77990.dtsi | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77990.dtsi b/arch/arm64/boot/dts/renesas/r8a77990.dtsi index e5e3386b7e6e7..7cfa102cefd8b 100644 --- a/arch/arm64/boot/dts/renesas/r8a77990.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a77990.dtsi @@ -1559,7 +1559,6 @@ max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 314>; - iommus = <&ipmmu_ds1 32>; status = "disabled"; }; @@ -1572,7 +1571,6 @@ max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 313>; - iommus = <&ipmmu_ds1 33>; status = "disabled"; }; @@ -1585,7 +1583,6 @@ max-frequency = <200000000>; power-domains = <&sysc R8A77990_PD_ALWAYS_ON>; resets = <&cpg 311>; - iommus = <&ipmmu_ds1 35>; status = "disabled"; }; |