diff options
| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2018-03-09 15:07:51 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-08-09 17:18:06 +0200 |
| commit | ef9c887963e407d0dab6fd27429eeda89033d5fc (patch) | |
| tree | 7d4a49a3c6c14896f635bb6d39ea6f0103c332d2 | |
| parent | 6b46b52120e53f6b4f4f7239aeadb8026cdf0184 (diff) | |
| download | renesas-backport-ef9c887963e407d0dab6fd27429eeda89033d5fc.tar.gz | |
arm64: dts: renesas: condor: add SCIF0 pins
Add the (previously omitted) SCIF0 pin data to the Condor board's
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit a824e63cfcfd60289023d990fe01839ec0db5950)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts index 06cf6845765ad..38f11cee42dc5 100644 --- a/arch/arm64/boot/dts/renesas/r8a77980-condor.dts +++ b/arch/arm64/boot/dts/renesas/r8a77980-condor.dts @@ -49,7 +49,22 @@ clock-frequency = <32768>; }; +&pfc { + scif0_pins: scif0 { + groups = "scif0_data"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk_b"; + function = "scif_clk"; + }; +}; + &scif0 { + pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; + pinctrl-names = "default"; + status = "okay"; }; |