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| author | Yu Chien Peter Lin <peterlin@andestech.com> | 2024-02-22 16:39:44 +0800 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-03-12 07:13:17 -0700 |
| commit | 8ecbb51f81c36f9ff5a7f00f237ecc041d429c45 (patch) | |
| tree | f758b2dbb3c7ada306757203dc6227aa37936acb | |
| parent | 9b464e19669de574b7a659c97bdd5be913d63c98 (diff) | |
| download | devicetree-rebasing-8ecbb51f81c36f9ff5a7f00f237ecc041d429c45.tar.gz | |
dt-bindings: riscv: Add Andes PMU extension description
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Link: https://lore.kernel.org/r/20240222083946.3977135-9-peterlin@andestech.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
[ upstream commit: 61609bf2b29dcb07de3aaad7d6212cc3c341192b ]
| -rw-r--r-- | Bindings/riscv/extensions.yaml | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/Bindings/riscv/extensions.yaml b/Bindings/riscv/extensions.yaml index 63d81dc895e5ce..468c646247aa5c 100644 --- a/Bindings/riscv/extensions.yaml +++ b/Bindings/riscv/extensions.yaml @@ -477,5 +477,12 @@ properties: latency, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: xandespmu + description: + The Andes Technology performance monitor extension for counter overflow + and privilege mode filtering. For more details, see Counter Related + Registers in the AX45MP datasheet. + https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + additionalProperties: true ... |