diff options
| author | Arnd Bergmann <arnd@arndb.de> | 2024-04-15 15:45:20 +0200 |
|---|---|---|
| committer | Stephen Boyd <sboyd@kernel.org> | 2024-04-19 14:38:01 -0700 |
| commit | 0a7c2fda3448b8f11a32c3e2fe94e70bd468be33 (patch) | |
| tree | 9d72eeea46bb183cde457bae2202c3a97d2b5362 | |
| parent | a12069a39b33c3b4c57929f5b42c88da681496ba (diff) | |
| download | linux-clk-sophgo.tar.gz | |
clk: sophgo: avoid open-coded 64-bit divisionclk-sophgo
On 32-bit architectures, the 64-bit division leads to a link failure:
arm-linux-gnueabi-ld: drivers/clk/sophgo/clk-cv18xx-pll.o: in function `fpll_calc_rate':
clk-cv18xx-pll.c:(.text.fpll_calc_rate+0x26): undefined reference to `__aeabi_uldivmod'
This one is not called in a fast path, and there is already another div_u64()
variant used in the same function, so convert it to div64_u64_rem().
Fixes: 80fd61ec4612 ("clk: sophgo: Add clock support for CV1800 SoC")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Link: https://lore.kernel.org/r/20240415134532.3467817-1-arnd@kernel.org
Reported-by: kernel test robot <lkp@intel.com>
Closes: https://lore.kernel.org/oe-kbuild-all/202404122344.d5pb2N1I-lkp@intel.com/
Closes: https://lore.kernel.org/oe-kbuild-all/202404140310.QEjZKtTN-lkp@intel.com/
Reviewed-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| -rw-r--r-- | drivers/clk/sophgo/clk-cv18xx-pll.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/clk/sophgo/clk-cv18xx-pll.c b/drivers/clk/sophgo/clk-cv18xx-pll.c index c546dad1791c31..29e24098bf5f91 100644 --- a/drivers/clk/sophgo/clk-cv18xx-pll.c +++ b/drivers/clk/sophgo/clk-cv18xx-pll.c @@ -205,8 +205,7 @@ static unsigned long fpll_calc_rate(unsigned long parent_rate, unsigned long rate; dividend <<= PLL_SYN_FACTOR_DOT_POS - 1; - rate = dividend / factor; - dividend %= factor; + rate = div64_u64_rem(dividend, factor, ÷nd); if (is_full_parent) { dividend <<= 1; |