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authorSerge Semin <Sergey.Semin@baikalelectronics.ru>2020-10-08 02:55:02 +0300
committerMark Brown <broonie@kernel.org>2020-10-08 23:00:16 +0100
commitfbddc989a5c441099978aad320ada0d5327309f4 (patch)
treeb47af745558915b9bfbe64cf869df5845d99e84c
parentc6cb3815f70d39e377bec6b44d25f2d8b68b324e (diff)
downloadlinux-fbddc989a5c441099978aad320ada0d5327309f4.tar.gz
spi: dw: De-assert chip-select on reset
SPI memory operations implementation will require to have the CS register cleared before executing the operation in order not to have the transmission automatically started prior the Tx FIFO is pre-initialized. Let's clear the register then on explicit controller reset to fulfil the requirements in case of an error or having the CS left set by a bootloader or another software. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Link: https://lore.kernel.org/r/20201007235511.4935-14-Sergey.Semin@baikalelectronics.ru Signed-off-by: Mark Brown <broonie@kernel.org>
-rw-r--r--drivers/spi/spi-dw.h7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
index 70fc9db9eb9865..0cb1ce28b26a4c 100644
--- a/drivers/spi/spi-dw.h
+++ b/drivers/spi/spi-dw.h
@@ -238,15 +238,16 @@ static inline void spi_umask_intr(struct dw_spi *dws, u32 mask)
}
/*
- * This disables the SPI controller, interrupts, clears the interrupts status,
- * and re-enable the controller back. Transmit and receive FIFO buffers are
- * cleared when the device is disabled.
+ * This disables the SPI controller, interrupts, clears the interrupts status
+ * and CS, then re-enables the controller back. Transmit and receive FIFO
+ * buffers are cleared when the device is disabled.
*/
static inline void spi_reset_chip(struct dw_spi *dws)
{
spi_enable_chip(dws, 0);
spi_mask_intr(dws, 0xff);
dw_readl(dws, DW_SPI_ICR);
+ dw_writel(dws, DW_SPI_SER, 0);
spi_enable_chip(dws, 1);
}