diff options
| author | Tony Luck <tony.luck@intel.com> | 2020-05-28 14:00:07 -0700 |
|---|---|---|
| committer | Andi Kleen <ak@linux.intel.com> | 2020-05-28 14:52:41 -0700 |
| commit | 391abaac9bdff385934b18134789bcc98b0adeb7 (patch) | |
| tree | 7fbf8d20a0ec39eb3b5d52c42e16104f10b38d3f | |
| parent | 78f5d82590e905f58c7d14fcdb0f5094123c1cdd (diff) | |
| download | mcelog-391abaac9bdff385934b18134789bcc98b0adeb7.tar.gz | |
mcelog: Add decode for MCi_MISC from 10nm memory controllerv170
Additional details on the source of the error are provided in the
IA32_MCi_MISC register. See Intel Software Developers' Manual
version 072, volume 3B, section 16.11.3, table 16-37.
Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Andi Kleen <ak@linux.intel.com>
| -rw-r--r-- | i10nm.c | 30 |
1 files changed, 30 insertions, 0 deletions
@@ -277,6 +277,35 @@ static struct field imc8[] = { {} }; +static void i10nm_imc_misc(u64 status, u64 misc) +{ + u32 column = EXTRACT(misc, 9, 18) << 2; + u32 row = EXTRACT(misc, 19, 39); + u32 bank = EXTRACT(misc, 42, 43); + u32 bankgroup = EXTRACT(misc, 40, 41) | (EXTRACT(misc, 44, 44) << 2); + u32 fdevice = EXTRACT(misc, 46, 51); + u32 subrank = EXTRACT(misc, 52, 55); + u32 rank = EXTRACT(misc, 56, 58); + u32 eccmode = EXTRACT(misc, 59, 62); + u32 transient = EXTRACT(misc, 63, 63); + + Wprintf("bank: 0x%x bankgroup: 0x%x row: 0x%x column: 0x%x\n", bank, bankgroup, row, column); + if (!transient && !EXTRACT(status, 61, 61)) + Wprintf("failed device: 0x%x\n", fdevice); + Wprintf("rank: 0x%x subrank: 0x%x\n", rank, subrank); + Wprintf("ecc mode: "); + switch (eccmode) { + case 0: Wprintf("SDDC memory mode\n"); break; + case 1: Wprintf("SDDC\n"); break; + case 4: Wprintf("ADDDC memory mode\n"); break; + case 5: Wprintf("ADDDC\n"); break; + case 8: Wprintf("DDRT read\n"); break; + default: Wprintf("unknown\n"); break; + } + if (transient) + Wprintf("transient\n"); +} + void i10nm_decode_model(int cputype, int bank, u64 status, u64 misc) { u64 f; @@ -339,6 +368,7 @@ void i10nm_decode_model(int cputype, int bank, u64 status, u64 misc) case 4: decode_bitfield(f, imc4); break; case 8: decode_bitfield(f, imc8); break; } + i10nm_imc_misc(status, misc); break; } } |