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| author | Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | 2011-10-10 13:30:17 +0200 |
|---|---|---|
| committer | Willy Tarreau <w@1wt.eu> | 2012-04-09 15:02:40 +0200 |
| commit | bcadae8b07b9f8abcba5d50031c55cd41dc0e748 (patch) | |
| tree | 1f7431a3814fd6c21edb1690313ebcac8606f6e3 | |
| parent | cbd2de43d233e2f85c866855d68e72311abc5749 (diff) | |
| download | linux-2.4-bcadae8b07b9f8abcba5d50031c55cd41dc0e748.tar.gz | |
8xx: start using dcbX instructions in various copy routines
Now that 8xx can fixup dcbX instructions, start using them
where possible like every other PowerPc arch do.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Willy Tarreau <w@1wt.eu>
| -rw-r--r-- | arch/ppc/kernel/misc.S | 18 | ||||
| -rw-r--r-- | arch/ppc/lib/string.S | 17 |
2 files changed, 0 insertions, 35 deletions
diff --git a/arch/ppc/kernel/misc.S b/arch/ppc/kernel/misc.S index c1c3178d4e9d50..6f579571f4e1a1 100644 --- a/arch/ppc/kernel/misc.S +++ b/arch/ppc/kernel/misc.S @@ -662,15 +662,7 @@ _GLOBAL(__flush_dcache_icache) _GLOBAL(clear_page) li r0,4096/L1_CACHE_LINE_SIZE mtctr r0 -#ifdef CONFIG_8xx - li r4, 0 -1: stw r4, 0(r3) - stw r4, 4(r3) - stw r4, 8(r3) - stw r4, 12(r3) -#else 1: dcbz 0,r3 -#endif addi r3,r3,L1_CACHE_LINE_SIZE bdnz 1b blr @@ -695,15 +687,6 @@ _GLOBAL(copy_page) addi r3,r3,-4 addi r4,r4,-4 -#ifdef CONFIG_8xx - /* don't use prefetch on 8xx */ - li r0,4096/L1_CACHE_LINE_SIZE - mtctr r0 -1: COPY_16_BYTES - bdnz 1b - blr - -#else /* not 8xx, we can prefetch */ li r5,4 #if MAX_COPY_PREFETCH > 1 @@ -744,7 +727,6 @@ _GLOBAL(copy_page) li r0,MAX_COPY_PREFETCH li r11,4 b 2b -#endif /* CONFIG_8xx */ /* * Atomic [test&set] exchange diff --git a/arch/ppc/lib/string.S b/arch/ppc/lib/string.S index 6ca54b4c3b1ae5..b6ea44bcc7caf8 100644 --- a/arch/ppc/lib/string.S +++ b/arch/ppc/lib/string.S @@ -159,14 +159,7 @@ _GLOBAL(cacheable_memzero) bdnz 4b 3: mtctr r9 li r7,4 -#if !defined(CONFIG_8xx) 10: dcbz r7,r6 -#else -10: stw r4, 4(r6) - stw r4, 8(r6) - stw r4, 12(r6) - stw r4, 16(r6) -#endif addi r6,r6,CACHELINE_BYTES bdnz 10b clrlwi r5,r8,32-LG_CACHELINE_BYTES @@ -261,9 +254,7 @@ _GLOBAL(cacheable_memcpy) mtctr r0 beq 63f 53: -#if !defined(CONFIG_8xx) dcbz r11,r6 -#endif COPY_16_BYTES #if L1_CACHE_LINE_SIZE >= 32 COPY_16_BYTES @@ -443,13 +434,6 @@ _GLOBAL(__copy_tofrom_user) li r11,4 beq 63f -#ifdef CONFIG_8xx - /* Don't use prefetch on 8xx */ - mtctr r0 -53: COPY_16_BYTES_WITHEX(0) - bdnz 53b - -#else /* not CONFIG_8xx */ /* Here we decide how far ahead to prefetch the source */ li r3,4 cmpwi r0,1 @@ -502,7 +486,6 @@ _GLOBAL(__copy_tofrom_user) li r3,4 li r7,0 bne 114b -#endif /* CONFIG_8xx */ 63: srwi. r0,r5,2 mtctr r0 |