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| author | Joakim Tjernlund <Joakim.Tjernlund@transmode.se> | 2011-10-10 13:30:13 +0200 |
|---|---|---|
| committer | Willy Tarreau <w@1wt.eu> | 2012-04-09 15:02:40 +0200 |
| commit | 08b263e5f5f159eeb635fcddf0e46f5ea7474414 (patch) | |
| tree | 3ca08eacd38b588526bd86eb3b6668a597055cc2 | |
| parent | 136fb16abaad3321cac1d4a2034a9b33f93a46fa (diff) | |
| download | linux-2.4-08b263e5f5f159eeb635fcddf0e46f5ea7474414.tar.gz | |
8xx: CPU6 errata make DTLB error too big to fit.
branch to common code in DTLB Miss instead.
Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Willy Tarreau <w@1wt.eu>
| -rw-r--r-- | arch/ppc/kernel/head_8xx.S | 23 |
1 files changed, 2 insertions, 21 deletions
diff --git a/arch/ppc/kernel/head_8xx.S b/arch/ppc/kernel/head_8xx.S index 0891b962c0595a..367fec086b0e28 100644 --- a/arch/ppc/kernel/head_8xx.S +++ b/arch/ppc/kernel/head_8xx.S @@ -469,6 +469,7 @@ DataStoreTLBMiss: * set. All other Linux PTE bits control the behavior * of the MMU. */ +finish_DTLB: 2: li r21, 0x00f0 mtspr DAR, r21 /* Tag DAR */ rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ @@ -578,27 +579,7 @@ DARFixed: ori r20, r20, _PAGE_DIRTY|_PAGE_ACCESSED|_PAGE_HWWRITE stw r20, 0(r21) /* and update pte in table */ xori r20, r20, _PAGE_RW /* RW bit is inverted */ - - /* The Linux PTE won't go exactly into the MMU TLB. - * Software indicator bits 22 and 28 must be clear. - * Software indicator bits 24, 25, 26, and 27 must be - * set. All other Linux PTE bits control the behavior - * of the MMU. - */ - li r21, 0x00f0 - mtspr DAR, r21 /* Tag DAR */ - rlwimi r20, r21, 0, 24, 28 /* Set 24-27, clear 28 */ - DO_8xx_CPU6(0x3d80, r3) - mtspr MD_RPN, r20 /* Update TLB entry */ - - mfspr r20, M_TW /* Restore registers */ - lwz r21, 0(r0) - mtcr r21 - lwz r21, 4(r0) -#ifdef CONFIG_8xx_CPU6 - lwz r3, 8(r0) -#endif - rfi + b finish_DTLB 2: mfspr r20, M_TW /* Restore registers */ lwz r21, 0(r0) |