diff options
author | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-04 11:36:41 -0700 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2011-10-04 11:36:41 -0700 |
commit | ee26bd7327da77164a04e78106c9ba7f9c0a625f (patch) | |
tree | 12d456d140883704325e7a63ffa2ea137d8202f8 | |
parent | ba97c2b32efc8a298d9aea096946dd156b2c7c79 (diff) | |
download | stable-queue-ee26bd7327da77164a04e78106c9ba7f9c0a625f.tar.gz |
3.0 patches
9 files changed, 589 insertions, 0 deletions
diff --git a/queue-3.0/asoc-fix-setting-update-bits-for-wm8753_ladc-and-wm8753_radc.patch b/queue-3.0/asoc-fix-setting-update-bits-for-wm8753_ladc-and-wm8753_radc.patch new file mode 100644 index 0000000000..d95caca516 --- /dev/null +++ b/queue-3.0/asoc-fix-setting-update-bits-for-wm8753_ladc-and-wm8753_radc.patch @@ -0,0 +1,36 @@ +From 21d17dd2a377ba894f26989915eb3c6e427a3656 Mon Sep 17 00:00:00 2001 +From: Axel Lin <axel.lin@gmail.com> +Date: Sun, 2 Oct 2011 20:41:04 +0800 +Subject: ASoC: Fix setting update bits for WM8753_LADC and WM8753_RADC + +From: Axel Lin <axel.lin@gmail.com> + +commit 21d17dd2a377ba894f26989915eb3c6e427a3656 upstream. + +Current code set update bits for WM8753_LDAC and WM8753_RDAC twice, +but missed setting update bits for WM8753_LADC and WM8753_RADC. + +I think it is a copy-paste bug in commit 776065 +"ASoC: codecs: wm8753: Fix register cache incoherency". + +Signed-off-by: Axel Lin <axel.lin@gmail.com> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + sound/soc/codecs/wm8753.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/sound/soc/codecs/wm8753.c ++++ b/sound/soc/codecs/wm8753.c +@@ -1454,8 +1454,8 @@ static int wm8753_probe(struct snd_soc_c + /* set the update bits */ + snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100); + snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100); +- snd_soc_update_bits(codec, WM8753_LDAC, 0x0100, 0x0100); +- snd_soc_update_bits(codec, WM8753_RDAC, 0x0100, 0x0100); ++ snd_soc_update_bits(codec, WM8753_LADC, 0x0100, 0x0100); ++ snd_soc_update_bits(codec, WM8753_RADC, 0x0100, 0x0100); + snd_soc_update_bits(codec, WM8753_LOUT1V, 0x0100, 0x0100); + snd_soc_update_bits(codec, WM8753_ROUT1V, 0x0100, 0x0100); + snd_soc_update_bits(codec, WM8753_LOUT2V, 0x0100, 0x0100); diff --git a/queue-3.0/asoc-use-a-valid-device-for-dev_err-in-zylonite.patch b/queue-3.0/asoc-use-a-valid-device-for-dev_err-in-zylonite.patch new file mode 100644 index 0000000000..57580505c9 --- /dev/null +++ b/queue-3.0/asoc-use-a-valid-device-for-dev_err-in-zylonite.patch @@ -0,0 +1,58 @@ +From eff919ac0fc7565e71ffa35657c333dd8cdc0520 Mon Sep 17 00:00:00 2001 +From: Arnd Bergmann <arnd@arndb.de> +Date: Sat, 1 Oct 2011 22:03:34 +0200 +Subject: ASoC: use a valid device for dev_err() in Zylonite + +From: Arnd Bergmann <arnd@arndb.de> + +commit eff919ac0fc7565e71ffa35657c333dd8cdc0520 upstream. + +A recent conversion has introduced references to &pdev->dev, which does +not actually exist in all the contexts it's used in. + +Replace this with card->dev where necessary, in order to let +the driver build again. + +Signed-off-by: Arnd Bergmann <arnd@arndb.de> +Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + sound/soc/pxa/zylonite.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/sound/soc/pxa/zylonite.c ++++ b/sound/soc/pxa/zylonite.c +@@ -196,20 +196,20 @@ static int zylonite_probe(struct snd_soc + if (clk_pout) { + pout = clk_get(NULL, "CLK_POUT"); + if (IS_ERR(pout)) { +- dev_err(&pdev->dev, "Unable to obtain CLK_POUT: %ld\n", ++ dev_err(card->dev, "Unable to obtain CLK_POUT: %ld\n", + PTR_ERR(pout)); + return PTR_ERR(pout); + } + + ret = clk_enable(pout); + if (ret != 0) { +- dev_err(&pdev->dev, "Unable to enable CLK_POUT: %d\n", ++ dev_err(card->dev, "Unable to enable CLK_POUT: %d\n", + ret); + clk_put(pout); + return ret; + } + +- dev_dbg(&pdev->dev, "MCLK enabled at %luHz\n", ++ dev_dbg(card->dev, "MCLK enabled at %luHz\n", + clk_get_rate(pout)); + } + +@@ -241,7 +241,7 @@ static int zylonite_resume_pre(struct sn + if (clk_pout) { + ret = clk_enable(pout); + if (ret != 0) +- dev_err(&pdev->dev, "Unable to enable CLK_POUT: %d\n", ++ dev_err(card->dev, "Unable to enable CLK_POUT: %d\n", + ret); + } + diff --git a/queue-3.0/drm-radeon-kms-add-retry-limits-for-native-dp-aux-defer.patch b/queue-3.0/drm-radeon-kms-add-retry-limits-for-native-dp-aux-defer.patch new file mode 100644 index 0000000000..f9e1173442 --- /dev/null +++ b/queue-3.0/drm-radeon-kms-add-retry-limits-for-native-dp-aux-defer.patch @@ -0,0 +1,83 @@ +From 6375bda073724ead7df08746866b724b1799a295 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 3 Oct 2011 09:13:46 -0400 +Subject: drm/radeon/kms: add retry limits for native DP aux defer + +From: Alex Deucher <alexander.deucher@amd.com> + +commit 6375bda073724ead7df08746866b724b1799a295 upstream. + +The previous code could potentially loop forever. Limit +the number of DP aux defer retries to 4 for native aux +transactions, same as i2c over aux transactions. + +Noticed by: Brad Campbell <lists2009@fnarfbargle.com> + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: Brad Campbell <lists2009@fnarfbargle.com> +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/gpu/drm/radeon/atombios_dp.c | 12 ++++++++---- + 1 file changed, 8 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/radeon/atombios_dp.c ++++ b/drivers/gpu/drm/radeon/atombios_dp.c +@@ -115,6 +115,7 @@ static int radeon_dp_aux_native_write(st + u8 msg[20]; + int msg_bytes = send_bytes + 4; + u8 ack; ++ unsigned retry; + + if (send_bytes > 16) + return -1; +@@ -125,20 +126,20 @@ static int radeon_dp_aux_native_write(st + msg[3] = (msg_bytes << 4) | (send_bytes - 1); + memcpy(&msg[4], send, send_bytes); + +- while (1) { ++ for (retry = 0; retry < 4; retry++) { + ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, + msg, msg_bytes, NULL, 0, delay, &ack); + if (ret < 0) + return ret; + if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) +- break; ++ return send_bytes; + else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) + udelay(400); + else + return -EIO; + } + +- return send_bytes; ++ return -EIO; + } + + static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, +@@ -149,13 +150,14 @@ static int radeon_dp_aux_native_read(str + int msg_bytes = 4; + u8 ack; + int ret; ++ unsigned retry; + + msg[0] = address; + msg[1] = address >> 8; + msg[2] = AUX_NATIVE_READ << 4; + msg[3] = (msg_bytes << 4) | (recv_bytes - 1); + +- while (1) { ++ for (retry = 0; retry < 4; retry++) { + ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, + msg, msg_bytes, recv, recv_bytes, delay, &ack); + if (ret < 0) +@@ -169,6 +171,8 @@ static int radeon_dp_aux_native_read(str + else + return -EIO; + } ++ ++ return -EIO; + } + + static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector, diff --git a/queue-3.0/drm-radeon-kms-fix-channel_remap-setup-v2.patch b/queue-3.0/drm-radeon-kms-fix-channel_remap-setup-v2.patch new file mode 100644 index 0000000000..df0e2ec5a4 --- /dev/null +++ b/queue-3.0/drm-radeon-kms-fix-channel_remap-setup-v2.patch @@ -0,0 +1,210 @@ +From 12d5180bd7e683a4ae80830b82ba67e7b7fac7b2 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Tue, 4 Oct 2011 10:46:34 -0400 +Subject: drm/radeon/kms: fix channel_remap setup (v2) +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Alex Deucher <alexander.deucher@amd.com> + +commit 12d5180bd7e683a4ae80830b82ba67e7b7fac7b2 upstream. + +Most asics just use the hw default value which requires +no explicit programming. For those that need a different +value, the vbios will program it properly. As such, +there's no need to program these registers explicitly +in the driver. Changing MC_SHARED_CHREMAP requires a reload +of all data in vram otherwise its contents will be scambled. + +Fixes: +https://bugs.freedesktop.org/show_bug.cgi?id=40103 + +v2: drop now unused channel_remap functions. + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/gpu/drm/radeon/evergreen.c | 44 ------------------------------- + drivers/gpu/drm/radeon/ni.c | 32 ----------------------- + drivers/gpu/drm/radeon/rv770.c | 51 ------------------------------------- + 3 files changed, 127 deletions(-) + +--- a/drivers/gpu/drm/radeon/evergreen.c ++++ b/drivers/gpu/drm/radeon/evergreen.c +@@ -1593,48 +1593,6 @@ static u32 evergreen_get_tile_pipe_to_ba + return backend_map; + } + +-static void evergreen_program_channel_remap(struct radeon_device *rdev) +-{ +- u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; +- +- tmp = RREG32(MC_SHARED_CHMAP); +- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { +- case 0: +- case 1: +- case 2: +- case 3: +- default: +- /* default mapping */ +- mc_shared_chremap = 0x00fac688; +- break; +- } +- +- switch (rdev->family) { +- case CHIP_HEMLOCK: +- case CHIP_CYPRESS: +- case CHIP_BARTS: +- tcp_chan_steer_lo = 0x54763210; +- tcp_chan_steer_hi = 0x0000ba98; +- break; +- case CHIP_JUNIPER: +- case CHIP_REDWOOD: +- case CHIP_CEDAR: +- case CHIP_PALM: +- case CHIP_SUMO: +- case CHIP_SUMO2: +- case CHIP_TURKS: +- case CHIP_CAICOS: +- default: +- tcp_chan_steer_lo = 0x76543210; +- tcp_chan_steer_hi = 0x0000ba98; +- break; +- } +- +- WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); +- WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); +- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); +-} +- + static void evergreen_gpu_init(struct radeon_device *rdev) + { + u32 cc_rb_backend_disable = 0; +@@ -2080,8 +2038,6 @@ static void evergreen_gpu_init(struct ra + WREG32(DMIF_ADDR_CONFIG, gb_addr_config); + WREG32(HDP_ADDR_CONFIG, gb_addr_config); + +- evergreen_program_channel_remap(rdev); +- + num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; + grbm_gfx_index = INSTANCE_BROADCAST_WRITES; + +--- a/drivers/gpu/drm/radeon/ni.c ++++ b/drivers/gpu/drm/radeon/ni.c +@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backe + return backend_map; + } + +-static void cayman_program_channel_remap(struct radeon_device *rdev) +-{ +- u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; +- +- tmp = RREG32(MC_SHARED_CHMAP); +- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { +- case 0: +- case 1: +- case 2: +- case 3: +- default: +- /* default mapping */ +- mc_shared_chremap = 0x00fac688; +- break; +- } +- +- switch (rdev->family) { +- case CHIP_CAYMAN: +- default: +- //tcp_chan_steer_lo = 0x54763210 +- tcp_chan_steer_lo = 0x76543210; +- tcp_chan_steer_hi = 0x0000ba98; +- break; +- } +- +- WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); +- WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); +- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); +-} +- + static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, + u32 disable_mask_per_se, + u32 max_disable_mask_per_se, +@@ -841,8 +811,6 @@ static void cayman_gpu_init(struct radeo + WREG32(DMIF_ADDR_CONFIG, gb_addr_config); + WREG32(HDP_ADDR_CONFIG, gb_addr_config); + +- cayman_program_channel_remap(rdev); +- + /* primary versions */ + WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); +--- a/drivers/gpu/drm/radeon/rv770.c ++++ b/drivers/gpu/drm/radeon/rv770.c +@@ -536,55 +536,6 @@ static u32 r700_get_tile_pipe_to_backend + return backend_map; + } + +-static void rv770_program_channel_remap(struct radeon_device *rdev) +-{ +- u32 tcp_chan_steer, mc_shared_chremap, tmp; +- bool force_no_swizzle; +- +- switch (rdev->family) { +- case CHIP_RV770: +- case CHIP_RV730: +- force_no_swizzle = false; +- break; +- case CHIP_RV710: +- case CHIP_RV740: +- default: +- force_no_swizzle = true; +- break; +- } +- +- tmp = RREG32(MC_SHARED_CHMAP); +- switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { +- case 0: +- case 1: +- default: +- /* default mapping */ +- mc_shared_chremap = 0x00fac688; +- break; +- case 2: +- case 3: +- if (force_no_swizzle) +- mc_shared_chremap = 0x00fac688; +- else +- mc_shared_chremap = 0x00bbc298; +- break; +- } +- +- if (rdev->family == CHIP_RV740) +- tcp_chan_steer = 0x00ef2a60; +- else +- tcp_chan_steer = 0x00fac688; +- +- /* RV770 CE has special chremap setup */ +- if (rdev->pdev->device == 0x944e) { +- tcp_chan_steer = 0x00b08b08; +- mc_shared_chremap = 0x00b08b08; +- } +- +- WREG32(TCP_CHAN_STEER, tcp_chan_steer); +- WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); +-} +- + static void rv770_gpu_init(struct radeon_device *rdev) + { + int i, j, num_qd_pipes; +@@ -784,8 +735,6 @@ static void rv770_gpu_init(struct radeon + WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); + +- rv770_program_channel_remap(rdev); +- + WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); + WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); + WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); diff --git a/queue-3.0/drm-radeon-kms-fix-logic-error-in-dp-hpd-handler.patch b/queue-3.0/drm-radeon-kms-fix-logic-error-in-dp-hpd-handler.patch new file mode 100644 index 0000000000..1a6549d996 --- /dev/null +++ b/queue-3.0/drm-radeon-kms-fix-logic-error-in-dp-hpd-handler.patch @@ -0,0 +1,42 @@ +From 5ba7ddf81634bfdf32d09261d2959e3f5b7c4263 Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 3 Oct 2011 08:37:33 -0400 +Subject: drm/radeon/kms: Fix logic error in DP HPD handler + +From: Alex Deucher <alexander.deucher@amd.com> + +commit 5ba7ddf81634bfdf32d09261d2959e3f5b7c4263 upstream. + +Only disable the pipe if the monitor is physically +disconnected. The previous logic also disabled the +pipe if the link was trained. + +Fixes: +https://bugs.freedesktop.org/show_bug.cgi?id=41248 + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/gpu/drm/radeon/radeon_connectors.c | 8 ++++---- + 1 file changed, 4 insertions(+), 4 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_connectors.c ++++ b/drivers/gpu/drm/radeon/radeon_connectors.c +@@ -68,11 +68,11 @@ void radeon_connector_hotplug(struct drm + if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) { + int saved_dpms = connector->dpms; + +- if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd) && +- radeon_dp_needs_link_train(radeon_connector)) +- drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); +- else ++ /* Only turn off the display it it's physically disconnected */ ++ if (!radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) + drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF); ++ else if (radeon_dp_needs_link_train(radeon_connector)) ++ drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); + connector->dpms = saved_dpms; + } + } diff --git a/queue-3.0/drm-radeon-kms-fix-regression-in-dp-aux-defer-handling.patch b/queue-3.0/drm-radeon-kms-fix-regression-in-dp-aux-defer-handling.patch new file mode 100644 index 0000000000..4963d20790 --- /dev/null +++ b/queue-3.0/drm-radeon-kms-fix-regression-in-dp-aux-defer-handling.patch @@ -0,0 +1,47 @@ +From 109bc10d30f33e84f1d7289f0039e0c858ade82f Mon Sep 17 00:00:00 2001 +From: Alex Deucher <alexander.deucher@amd.com> +Date: Mon, 3 Oct 2011 09:13:45 -0400 +Subject: drm/radeon/kms: fix regression in DP aux defer handling + +From: Alex Deucher <alexander.deucher@amd.com> + +commit 109bc10d30f33e84f1d7289f0039e0c858ade82f upstream. + +An incorrect ordering in the error checking code lead +to DP aux defer being skipped in the aux native write +path. Move the bytes transferred check (ret == 0) +below the defer check. + +Tracked down by: Brad Campbell <brad@fnarfbargle.com> + +Fixes: +https://bugs.freedesktop.org/show_bug.cgi?id=41121 + +Signed-off-by: Alex Deucher <alexander.deucher@amd.com> +Cc: Brad Campbell <brad@fnarfbargle.com> +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/gpu/drm/radeon/atombios_dp.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +--- a/drivers/gpu/drm/radeon/atombios_dp.c ++++ b/drivers/gpu/drm/radeon/atombios_dp.c +@@ -158,14 +158,14 @@ static int radeon_dp_aux_native_read(str + while (1) { + ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, + msg, msg_bytes, recv, recv_bytes, delay, &ack); +- if (ret == 0) +- return -EPROTO; + if (ret < 0) + return ret; + if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) + return ret; + else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) + udelay(400); ++ else if (ret == 0) ++ return -EPROTO; + else + return -EIO; + } diff --git a/queue-3.0/drm-radeon-update-avivo-cursor-coordinate-origin-before.patch b/queue-3.0/drm-radeon-update-avivo-cursor-coordinate-origin-before.patch new file mode 100644 index 0000000000..be7258191f --- /dev/null +++ b/queue-3.0/drm-radeon-update-avivo-cursor-coordinate-origin-before.patch @@ -0,0 +1,53 @@ +From b8aee294d89502469f2d80ae6afb93398d8227e0 Mon Sep 17 00:00:00 2001 +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> +Date: Fri, 30 Sep 2011 17:16:52 +0200 +Subject: drm/radeon: Update AVIVO cursor coordinate origin before + x/yorigin calculation. +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: =?UTF-8?q?Michel=20D=C3=A4nzer?= <michel.daenzer@amd.com> + +commit b8aee294d89502469f2d80ae6afb93398d8227e0 upstream. + +Fixes cursor disappearing prematurely when moving off a top/left edge which +is not located at the desktop top/left edge. + +Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> +Reviewed-by: Alex Deucher <alexander.deucher@amd.com> +Signed-off-by: Dave Airlie <airlied@redhat.com> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/gpu/drm/radeon/radeon_cursor.c | 12 +++++++----- + 1 file changed, 7 insertions(+), 5 deletions(-) + +--- a/drivers/gpu/drm/radeon/radeon_cursor.c ++++ b/drivers/gpu/drm/radeon/radeon_cursor.c +@@ -208,6 +208,13 @@ int radeon_crtc_cursor_move(struct drm_c + int xorigin = 0, yorigin = 0; + int w = radeon_crtc->cursor_width; + ++ if (ASIC_IS_AVIVO(rdev)) { ++ /* avivo cursor are offset into the total surface */ ++ x += crtc->x; ++ y += crtc->y; ++ } ++ DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); ++ + if (x < 0) + xorigin = -x + 1; + if (y < 0) +@@ -221,11 +228,6 @@ int radeon_crtc_cursor_move(struct drm_c + int i = 0; + struct drm_crtc *crtc_p; + +- /* avivo cursor are offset into the total surface */ +- x += crtc->x; +- y += crtc->y; +- DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y); +- + /* avivo cursor image can't end on 128 pixel boundary or + * go past the end of the frame if both crtcs are enabled + */ diff --git a/queue-3.0/lis3-fix-regression-of-hp-driveguard-with-8bit-chip.patch b/queue-3.0/lis3-fix-regression-of-hp-driveguard-with-8bit-chip.patch new file mode 100644 index 0000000000..ca90e5e28b --- /dev/null +++ b/queue-3.0/lis3-fix-regression-of-hp-driveguard-with-8bit-chip.patch @@ -0,0 +1,52 @@ +From 05faadcf59507e8eea57ffbeea9cbb14c9a2ab3d Mon Sep 17 00:00:00 2001 +From: Takashi Iwai <tiwai@suse.de> +Date: Mon, 3 Oct 2011 18:09:14 -0700 +Subject: lis3: fix regression of HP DriveGuard with 8bit chip + +From: Takashi Iwai <tiwai@suse.de> + +commit 05faadcf59507e8eea57ffbeea9cbb14c9a2ab3d upstream. + +Commit 2a7fade7e03 ("hwmon: lis3: Power on corrections") caused a +regression on HP laptops with 8bit chip. Writing CTRL2_BOOT_8B bit seems +clearing the BIOS setup, and no proper interrupt for DriveGuard will be +triggered any more. + +Since the init code there is basically only for embedded devices, put a +pdata check so that the problematic initialization will be skipped for +hp_accel stuff. + +Signed-off-by: Takashi Iwai <tiwai@suse.de> +Cc: Eric Piel <eric.piel@tremplin-utc.net> +Cc: Samu Onkalo <samu.p.onkalo@nokia.com> +Signed-off-by: Andrew Morton <akpm@google.com> +Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> +Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> + +--- + drivers/misc/lis3lv02d/lis3lv02d.c | 14 ++++++++------ + 1 file changed, 8 insertions(+), 6 deletions(-) + +--- a/drivers/misc/lis3lv02d/lis3lv02d.c ++++ b/drivers/misc/lis3lv02d/lis3lv02d.c +@@ -375,12 +375,14 @@ void lis3lv02d_poweron(struct lis3lv02d + * both have been read. So the value read will always be correct. + * Set BOOT bit to refresh factory tuning values. + */ +- lis3->read(lis3, CTRL_REG2, ®); +- if (lis3->whoami == WAI_12B) +- reg |= CTRL2_BDU | CTRL2_BOOT; +- else +- reg |= CTRL2_BOOT_8B; +- lis3->write(lis3, CTRL_REG2, reg); ++ if (lis3->pdata) { ++ lis3->read(lis3, CTRL_REG2, ®); ++ if (lis3->whoami == WAI_12B) ++ reg |= CTRL2_BDU | CTRL2_BOOT; ++ else ++ reg |= CTRL2_BOOT_8B; ++ lis3->write(lis3, CTRL_REG2, reg); ++ } + + /* LIS3 power on delay is quite long */ + msleep(lis3->pwron_delay / lis3lv02d_get_odr()); diff --git a/queue-3.0/series b/queue-3.0/series index 8a36a9e470..3179fb166a 100644 --- a/queue-3.0/series +++ b/queue-3.0/series @@ -8,3 +8,11 @@ sched-rt-migrate-equal-priority-tasks-to-available-cpus.patch sched-fix-up-wchan-borkage.patch ide-disk-fix-request-requeuing.patch posix-cpu-timers-cure-smp-wobbles.patch +lis3-fix-regression-of-hp-driveguard-with-8bit-chip.patch +asoc-use-a-valid-device-for-dev_err-in-zylonite.patch +asoc-fix-setting-update-bits-for-wm8753_ladc-and-wm8753_radc.patch +drm-radeon-update-avivo-cursor-coordinate-origin-before.patch +drm-radeon-kms-fix-logic-error-in-dp-hpd-handler.patch +drm-radeon-kms-fix-regression-in-dp-aux-defer-handling.patch +drm-radeon-kms-add-retry-limits-for-native-dp-aux-defer.patch +drm-radeon-kms-fix-channel_remap-setup-v2.patch |