diff options
| author | Andrzej Kacprowski <Andrzej.Kacprowski@intel.com> | 2024-02-20 14:16:24 +0100 |
|---|---|---|
| committer | Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com> | 2024-02-20 16:56:21 +0100 |
| commit | eb0d253ff9c74dee30aa92fe460b825eb28acd73 (patch) | |
| tree | 676f31709860595bd49652182dcd27a669abae4d | |
| parent | 335126937753844d36036984e96a8f343538a778 (diff) | |
| download | linux-eb0d253ff9c74dee30aa92fe460b825eb28acd73.tar.gz | |
accel/ivpu: Don't enable any tiles by default on VPU40xx
There is no point in requesting 1 tile on VPU40xx as the FW will
probably need more tiles to run workloads, so it will have to
reconfigure PLL anyway. Don't enable any tiles and allow the FW to
perform initial tile configuration.
This improves NPU boot stability as the tiles are always enabled only
by the FW from the same initial state.
Fixes: 79cdc56c4a54 ("accel/ivpu: Add initial support for VPU 4")
Cc: stable@vger.kernel.org
Signed-off-by: Andrzej Kacprowski <Andrzej.Kacprowski@intel.com>
Signed-off-by: Jacek Lawrynowicz <jacek.lawrynowicz@linux.intel.com>
Reviewed-by: Jeffrey Hugo <quic_jhugo@quicinc.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240220131624.1447813-1-jacek.lawrynowicz@linux.intel.com
Notes
Fixes: 79cdc56c4a54 ("accel/ivpu: Add initial support for VPU 4") # v6.6-rc1
Stable: cca20208515e # v6.6.19
Lore: https://lore.kernel.org/r/20240220110830.1439719-1-jacek.lawrynowicz@linux.intel.com # dri-devel, stable
Lore: https://lore.kernel.org/r/20240220131624.1447813-1-jacek.lawrynowicz@linux.intel.com # dri-devel, stable
| -rw-r--r-- | drivers/accel/ivpu/ivpu_hw_40xx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/accel/ivpu/ivpu_hw_40xx.c b/drivers/accel/ivpu/ivpu_hw_40xx.c index 1c995307c11388..a1523d0b1ef366 100644 --- a/drivers/accel/ivpu/ivpu_hw_40xx.c +++ b/drivers/accel/ivpu/ivpu_hw_40xx.c @@ -24,7 +24,7 @@ #define SKU_HW_ID_SHIFT 16u #define SKU_HW_ID_MASK 0xffff0000u -#define PLL_CONFIG_DEFAULT 0x1 +#define PLL_CONFIG_DEFAULT 0x0 #define PLL_CDYN_DEFAULT 0x80 #define PLL_EPP_DEFAULT 0x80 #define PLL_REF_CLK_FREQ (50 * 1000000) |