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authorVille Syrjälä <ville.syrjala@linux.intel.com>2023-06-09 17:13:53 +0300
committerTvrtko Ursulin <tvrtko.ursulin@intel.com>2023-07-04 10:40:21 +0100
commitfdffb7dbc74f48cb1d404d9ab0c9fd769a59caf0 (patch)
treef333a505fad4bfdacdd03f41aca80c2cc5b708bc
parent5b7826355e5b9f48eea29275215fc55165cd17c3 (diff)
downloadlinux-pm-fdffb7dbc74f48cb1d404d9ab0c9fd769a59caf0.tar.gz
drm/i915/psr: Fix BDW PSR AUX CH data register offsets
The multiplication got replaced by an addition in some cleanup. This means we never write the correct data to some of the BDW PSR data registers and thus we fail to actually wake up the panel from PSR. Fixes: 4ab4fa103217 ("drm/i915/psr: Make PSR registers relative to transcoders") Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230609141404.12729-3-ville.syrjala@linux.intel.com Reviewed-by: Jouni Högander <jouni.hogander@intel.com> (cherry picked from commit 460dc4ba1442b3e5e543328d11db2702b98d3d7c) Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
-rw-r--r--drivers/gpu/drm/i915/display/intel_psr_regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_psr_regs.h b/drivers/gpu/drm/i915/display/intel_psr_regs.h
index 0f7db617425a35..8750cb0d8d9dd0 100644
--- a/drivers/gpu/drm/i915/display/intel_psr_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_psr_regs.h
@@ -81,7 +81,7 @@
#define _SRD_AUX_DATA_A 0x60814
#define _SRD_AUX_DATA_EDP 0x6f814
-#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(tran, i) _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) * 4) /* 5 registers */
#define _SRD_STATUS_A 0x60840
#define _SRD_STATUS_EDP 0x6f840