aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-powerpc/ucc.h
blob: afe3076bdc03d862465dcf181772c6672f704c50 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
/*
 * Copyright (C) 2006 Freescale Semicondutor, Inc. All rights reserved.
 *
 * Authors: 	Shlomi Gridish <gridish@freescale.com>
 * 		Li Yang <leoli@freescale.com>
 *
 * Description:
 * Internal header file for UCC unit routines.
 *
 * This program is free software; you can redistribute  it and/or modify it
 * under  the terms of  the GNU General  Public License as published by the
 * Free Software Foundation;  either version 2 of the  License, or (at your
 * option) any later version.
 */
#ifndef __UCC_H__
#define __UCC_H__

#include <asm/immap_qe.h>
#include <asm/qe.h>

#define STATISTICS

#define UCC_MAX_NUM	8

/* Slow or fast type for UCCs.
*/
enum ucc_speed_type {
	UCC_SPEED_TYPE_FAST, UCC_SPEED_TYPE_SLOW
};

/* Initial UCCs Parameter RAM address relative to: MEM_MAP_BASE (IMMR).
*/
enum ucc_pram_initial_offset {
	UCC_PRAM_OFFSET_UCC1 = 0x8400,
	UCC_PRAM_OFFSET_UCC2 = 0x8500,
	UCC_PRAM_OFFSET_UCC3 = 0x8600,
	UCC_PRAM_OFFSET_UCC4 = 0x9000,
	UCC_PRAM_OFFSET_UCC5 = 0x8000,
	UCC_PRAM_OFFSET_UCC6 = 0x8100,
	UCC_PRAM_OFFSET_UCC7 = 0x8200,
	UCC_PRAM_OFFSET_UCC8 = 0x8300
};

/* ucc_set_type
 * Sets UCC to slow or fast mode.
 *
 * ucc_num - (In) number of UCC (0-7).
 * regs    - (In) pointer to registers base for the UCC.
 * speed   - (In) slow or fast mode for UCC.
 */
int ucc_set_type(int ucc_num, struct ucc_common *regs,
		 enum ucc_speed_type speed);

/* ucc_init_guemr
 * Init the Guemr register.
 *
 * regs - (In) pointer to registers base for the UCC.
 */
int ucc_init_guemr(struct ucc_common *regs);

int ucc_set_qe_mux_mii_mng(int ucc_num);

int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode);

int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask);

/* QE MUX clock routing for UCC
*/
static inline int ucc_set_qe_mux_grant(int ucc_num, int set)
{
	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_GRANT);
}

static inline int ucc_set_qe_mux_tsa(int ucc_num, int set)
{
	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_TSA);
}

static inline int ucc_set_qe_mux_bkpt(int ucc_num, int set)
{
	return ucc_mux_set_grant_tsa_bkpt(ucc_num, set, QE_CMXUCR_BKPT);
}

#endif				/* __UCC_H__ */