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-rw-r--r--include/asm-sh/cpu-sh4/addrspace.h3
-rw-r--r--include/asm-sh/cpu-sh4/dma-sh7780.h39
-rw-r--r--include/asm-sh/cpu-sh4/dma.h11
-rw-r--r--include/asm-sh/hs7751rvoip/hs7751rvoip.h2
-rw-r--r--include/asm-sh/irq-sh7780.h5
-rw-r--r--include/asm-sh/irq.h2
-rw-r--r--include/asm-sh/landisk/iodata_landisk.h2
-rw-r--r--include/asm-sh/r7780rp/ide.h8
-rw-r--r--include/asm-sh/r7780rp/r7780rp.h177
-rw-r--r--include/asm-sh/rts7751r2d/rts7751r2d.h2
10 files changed, 236 insertions, 15 deletions
diff --git a/include/asm-sh/cpu-sh4/addrspace.h b/include/asm-sh/cpu-sh4/addrspace.h
index 727634d886cecd..bb2e1b03060c98 100644
--- a/include/asm-sh/cpu-sh4/addrspace.h
+++ b/include/asm-sh/cpu-sh4/addrspace.h
@@ -22,5 +22,8 @@
#define P4SEG_TLB_DATA 0xf7000000
#define P4SEG_REG_BASE 0xff000000
+#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
+#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
+
#endif /* __ASM_CPU_SH4_ADDRSPACE_H */
diff --git a/include/asm-sh/cpu-sh4/dma-sh7780.h b/include/asm-sh/cpu-sh4/dma-sh7780.h
new file mode 100644
index 00000000000000..6c90d28331b27d
--- /dev/null
+++ b/include/asm-sh/cpu-sh4/dma-sh7780.h
@@ -0,0 +1,39 @@
+#ifndef __ASM_SH_CPU_SH4_DMA_SH7780_H
+#define __ASM_SH_CPU_SH4_DMA_SH7780_H
+
+#define REQ_HE 0x000000C0
+#define REQ_H 0x00000080
+#define REQ_LE 0x00000040
+#define TM_BURST 0x0000020
+#define TS_8 0x00000000
+#define TS_16 0x00000008
+#define TS_32 0x00000010
+#define TS_16BLK 0x00000018
+#define TS_32BLK 0x00100000
+
+/*
+ * The SuperH DMAC supports a number of transmit sizes, we list them here,
+ * with their respective values as they appear in the CHCR registers.
+ *
+ * Defaults to a 64-bit transfer size.
+ */
+enum {
+ XMIT_SZ_8BIT,
+ XMIT_SZ_16BIT,
+ XMIT_SZ_32BIT,
+ XMIT_SZ_128BIT,
+ XMIT_SZ_256BIT,
+};
+
+/*
+ * The DMA count is defined as the number of bytes to transfer.
+ */
+static unsigned int __attribute__ ((used)) ts_shift[] = {
+ [XMIT_SZ_8BIT] = 0,
+ [XMIT_SZ_16BIT] = 1,
+ [XMIT_SZ_32BIT] = 2,
+ [XMIT_SZ_128BIT] = 4,
+ [XMIT_SZ_256BIT] = 5,
+};
+
+#endif /* __ASM_SH_CPU_SH4_DMA_SH7780_H */
diff --git a/include/asm-sh/cpu-sh4/dma.h b/include/asm-sh/cpu-sh4/dma.h
index 0dfe61f1480216..3e4b3e6d80c02f 100644
--- a/include/asm-sh/cpu-sh4/dma.h
+++ b/include/asm-sh/cpu-sh4/dma.h
@@ -1,11 +1,17 @@
#ifndef __ASM_CPU_SH4_DMA_H
#define __ASM_CPU_SH4_DMA_H
+#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
+
#ifdef CONFIG_CPU_SH4A
#define SH_DMAC_BASE 0xfc808020
+
+#define CHCR_TS_MASK 0x18
+#define CHCR_TS_SHIFT 3
+
+#include <asm/cpu/dma-sh7780.h>
#else
#define SH_DMAC_BASE 0xffa00000
-#endif
/* Definitions for the SuperH DMAC */
#define TM_BURST 0x0000080
@@ -19,8 +25,6 @@
#define DMAOR_COD 0x00000008
-#define DMAOR_INIT ( 0x8000 | DMAOR_DME )
-
/*
* The SuperH DMAC supports a number of transmit sizes, we list them here,
* with their respective values as they appear in the CHCR registers.
@@ -45,5 +49,6 @@ static unsigned int ts_shift[] __attribute__ ((used)) = {
[XMIT_SZ_32BIT] = 2,
[XMIT_SZ_256BIT] = 5,
};
+#endif
#endif /* __ASM_CPU_SH4_DMA_H */
diff --git a/include/asm-sh/hs7751rvoip/hs7751rvoip.h b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
index 69faf0171473b2..c4cff9d33927d9 100644
--- a/include/asm-sh/hs7751rvoip/hs7751rvoip.h
+++ b/include/asm-sh/hs7751rvoip/hs7751rvoip.h
@@ -19,8 +19,6 @@
#define PA_OUTPORTR 0xa400000e /* Output Port Reguster */
#define PA_VERREG 0xa4000014 /* FPGA Version Register */
-#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
-#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
diff --git a/include/asm-sh/irq-sh7780.h b/include/asm-sh/irq-sh7780.h
index 7f90315cd83043..895c5780e45473 100644
--- a/include/asm-sh/irq-sh7780.h
+++ b/include/asm-sh/irq-sh7780.h
@@ -145,11 +145,6 @@
#define TMU_CH5_IPR_POS 1
#define TMU_CH5_PRIORITY 2
-#define RTC_IRQ 22
-#define RTC_IPR_ADDR INTC_INT2PRI1
-#define RTC_IPR_POS 0
-#define RTC_PRIORITY TIMER_PRIORITY
-
/* SCIF0 */
#define SCIF0_ERI_IRQ 40
#define SCIF0_RXI_IRQ 41
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index 611e67cd062728..7e8455b1cb44c3 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -577,7 +577,7 @@ extern int ipr_irq_demux(int irq);
#define NR_INTC2_IRQS 64
#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
#define INTC2_BASE 0xffd40000
-#define INTC2_FIRST_IRQ 22
+#define INTC2_FIRST_IRQ 21
#define INTC2_INTMSK_OFFSET (0x38)
#define INTC2_INTMSKCLR_OFFSET (0x3c)
#define NR_INTC2_IRQS 60
diff --git a/include/asm-sh/landisk/iodata_landisk.h b/include/asm-sh/landisk/iodata_landisk.h
index 9db3cdfe677618..c74d3c73f37720 100644
--- a/include/asm-sh/landisk/iodata_landisk.h
+++ b/include/asm-sh/landisk/iodata_landisk.h
@@ -22,8 +22,6 @@
/* 2003.10.31 I-O DATA NSD NWG add. for shutdown port clear */
#define PA_PWRINT_CLR 0xb0000006 /* Shutdown Interrupt clear Register */
-#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
-#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_LCD_CLRDSP 0x00 /* LCD Clear Display Offset */
#define PA_LCD_RTNHOME 0x00 /* LCD Return Home Offset */
#define PA_LCD_ENTMODE 0x00 /* LCD Entry Mode Offset */
diff --git a/include/asm-sh/r7780rp/ide.h b/include/asm-sh/r7780rp/ide.h
new file mode 100644
index 00000000000000..a1ed78e0f6173f
--- /dev/null
+++ b/include/asm-sh/r7780rp/ide.h
@@ -0,0 +1,8 @@
+#ifndef __ASM_SH_R7780RP_IDE_H
+#define __ASM_SH_R7780RP_IDE_H
+
+/* Nothing to see here.. */
+#include <asm/mach/r7780rp.h>
+
+#endif /* __ASM_SH_R7780RP_IDE_H */
+
diff --git a/include/asm-sh/r7780rp/r7780rp.h b/include/asm-sh/r7780rp/r7780rp.h
new file mode 100644
index 00000000000000..f95d9dba31a2fe
--- /dev/null
+++ b/include/asm-sh/r7780rp/r7780rp.h
@@ -0,0 +1,177 @@
+#ifndef __ASM_SH_RENESAS_R7780RP_H
+#define __ASM_SH_RENESAS_R7780RP_H
+
+/*
+ * linux/include/asm-sh/r7780rp.h
+ *
+ * Copyright (C) 2000 Atom Create Engineering Co., Ltd.
+ *
+ * Renesas Solutions Highlander R7780RP support
+ */
+
+/* Box specific addresses. */
+#if defined(CONFIG_SH_R7780MP)
+#define PA_BCR 0xa4000000 /* FPGA */
+#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_IRLPRI1 (PA_BCR+0x0004) /* Interrupt Priorty 1 */
+#define PA_IRLPRI2 (PA_BCR+0x0006) /* Interrupt Priorty 2 */
+#define PA_IRLPRI3 (PA_BCR+0x0008) /* Interrupt Priorty 3 */
+#define PA_IRLPRI4 (PA_BCR+0x000a) /* Interrupt Priorty 4 */
+#define PA_RSTCTL (PA_BCR+0x000c) /* Reset Control */
+#define PA_PCIBD (PA_BCR+0x000e) /* PCI Board detect control */
+#define PA_PCICD (PA_BCR+0x0010) /* PCI Conector detect control */
+#define PA_EXTGIO (PA_BCR+0x0016) /* Extension GPIO Control */
+#define PA_IVDRMON (PA_BCR+0x0018) /* iVDR Moniter control */
+#define PA_IVDRCTL (PA_BCR+0x001a) /* iVDR control */
+#define PA_OBLED (PA_BCR+0x001c) /* On Board LED control */
+#define PA_OBSW (PA_BCR+0x001e) /* On Board Switch control */
+#define PA_AUDIOSEL (PA_BCR+0x0020) /* Sound Interface Select control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBSW (PA_BCR+0x0200) /* Debug Board Switch control */
+#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR0 (PA_BCR+0x0400) /* SCIF0 Serial mode control */
+#define PA_SCBRR0 (PA_BCR+0x0404) /* SCIF0 Bit rate control */
+#define PA_SCSCR0 (PA_BCR+0x0408) /* SCIF0 Serial control */
+#define PA_SCFTDR0 (PA_BCR+0x040c) /* SCIF0 Send FIFO control */
+#define PA_SCFSR0 (PA_BCR+0x0410) /* SCIF0 Serial status control */
+#define PA_SCFRDR0 (PA_BCR+0x0414) /* SCIF0 Receive FIFO control */
+#define PA_SCFCR0 (PA_BCR+0x0418) /* SCIF0 FIFO control */
+#define PA_SCTFDR0 (PA_BCR+0x041c) /* SCIF0 Send FIFO data control */
+#define PA_SCRFDR0 (PA_BCR+0x0420) /* SCIF0 Receive FIFO data control */
+#define PA_SCSPTR0 (PA_BCR+0x0424) /* SCIF0 Serial Port control */
+#define PA_SCLSR0 (PA_BCR+0x0428) /* SCIF0 Line Status control */
+#define PA_SCRER0 (PA_BCR+0x042c) /* SCIF0 Serial Error control */
+#define PA_SCSMR1 (PA_BCR+0x0500) /* SCIF1 Serial mode control */
+#define PA_SCBRR1 (PA_BCR+0x0504) /* SCIF1 Bit rate control */
+#define PA_SCSCR1 (PA_BCR+0x0508) /* SCIF1 Serial control */
+#define PA_SCFTDR1 (PA_BCR+0x050c) /* SCIF1 Send FIFO control */
+#define PA_SCFSR1 (PA_BCR+0x0510) /* SCIF1 Serial status control */
+#define PA_SCFRDR1 (PA_BCR+0x0514) /* SCIF1 Receive FIFO control */
+#define PA_SCFCR1 (PA_BCR+0x0518) /* SCIF1 FIFO control */
+#define PA_SCTFDR1 (PA_BCR+0x051c) /* SCIF1 Send FIFO data control */
+#define PA_SCRFDR1 (PA_BCR+0x0520) /* SCIF1 Receive FIFO data control */
+#define PA_SCSPTR1 (PA_BCR+0x0524) /* SCIF1 Serial Port control */
+#define PA_SCLSR1 (PA_BCR+0x0528) /* SCIF1 Line Status control */
+#define PA_SCRER1 (PA_BCR+0x052c) /* SCIF1 Serial Error control */
+#define PA_ICCR (PA_BCR+0x0600) /* Serial control */
+#define PA_SAR (PA_BCR+0x0602) /* Serial Slave control */
+#define PA_MDR (PA_BCR+0x0604) /* Serial Mode control */
+#define PA_ADR1 (PA_BCR+0x0606) /* Serial Address1 control */
+#define PA_DAR1 (PA_BCR+0x0646) /* Serial Data1 control */
+#define PA_VERREG (PA_BCR+0x0700) /* FPGA Version Register */
+#define PA_POFF (PA_BCR+0x0800) /* System Power Off control */
+#define PA_PMR (PA_BCR+0x0900) /* */
+
+#define PA_AX88796L 0xa4100400 /* AX88796L Area */
+#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
+#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
+#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+
+#define IRQ_PCISLOT1 65 /* PCI Slot #1 IRQ */
+#define IRQ_PCISLOT2 66 /* PCI Slot #2 IRQ */
+#define IRQ_PCISLOT3 67 /* PCI Slot #3 IRQ */
+#define IRQ_PCISLOT4 68 /* PCI Slot #4 IRQ */
+#define IRQ_CFCARD 1 /* CF Card IRQ */
+// #define IRQ_CFINST 0 /* CF Card Insert IRQ */
+#define IRQ_TP 2 /* Touch Panel IRQ */
+#define IRQ_SCI1 3 /* SCI1 IRQ */
+#define IRQ_SCI0 4 /* SCI0 IRQ */
+#define IRQ_2SERIAL 5 /* Serial IRQ */
+#define IRQ_RTC 6 /* RTC A / B IRQ */
+#define IRQ_EXTENTION6 7 /* EXT6n IRQ */
+#define IRQ_EXTENTION5 8 /* EXT5n IRQ */
+#define IRQ_EXTENTION4 9 /* EXT4n IRQ */
+#define IRQ_EXTENTION2 10 /* EXT2n IRQ */
+#define IRQ_EXTENTION1 11 /* EXT1n IRQ */
+#define IRQ_ONETH 13 /* On board Ethernet IRQ */
+#define IRQ_PSW 14 /* Push Switch IRQ */
+
+#else /* R7780RP */
+
+#define PA_BCR 0xa5000000 /* FPGA */
+#define PA_IRLMSK (PA_BCR+0x0000) /* Interrupt Mask control */
+#define PA_IRLMON (PA_BCR+0x0002) /* Interrupt Status control */
+#define PA_SDPOW (PA_BCR+0x0004) /* SD Power control */
+#define PA_RSTCTL (PA_BCR+0x0006) /* Device Reset control */
+#define PA_PCIBD (PA_BCR+0x0008) /* PCI Board detect control */
+#define PA_PCICD (PA_BCR+0x000a) /* PCI Conector detect control */
+#define PA_ZIGIO1 (PA_BCR+0x000c) /* Zigbee IO control 1 */
+#define PA_ZIGIO2 (PA_BCR+0x000e) /* Zigbee IO control 2 */
+#define PA_ZIGIO3 (PA_BCR+0x0010) /* Zigbee IO control 3 */
+#define PA_ZIGIO4 (PA_BCR+0x0012) /* Zigbee IO control 4 */
+#define PA_IVDRMON (PA_BCR+0x0014) /* iVDR Moniter control */
+#define PA_IVDRCTL (PA_BCR+0x0016) /* iVDR control */
+#define PA_OBLED (PA_BCR+0x0018) /* On Board LED control */
+#define PA_OBSW (PA_BCR+0x001a) /* On Board Switch control */
+#define PA_AUDIOSEL (PA_BCR+0x001c) /* Sound Interface Select control */
+#define PA_EXTPLR (PA_BCR+0x001e) /* Extention Pin Polarity control */
+#define PA_TPCTL (PA_BCR+0x0100) /* Touch Panel Access control */
+#define PA_TPDCKCTL (PA_BCR+0x0102) /* Touch Panel Access data control */
+#define PA_TPCTLCLR (PA_BCR+0x0104) /* Touch Panel Access control */
+#define PA_TPXPOS (PA_BCR+0x0106) /* Touch Panel X position control */
+#define PA_TPYPOS (PA_BCR+0x0108) /* Touch Panel Y position control */
+#define PA_DBDET (PA_BCR+0x0200) /* Debug Board detect control */
+#define PA_DBDISPCTL (PA_BCR+0x0202) /* Debug Board Dot timing control */
+#define PA_DBSW (PA_BCR+0x0204) /* Debug Board Switch control */
+#define PA_CFCTL (PA_BCR+0x0300) /* CF Timing control */
+#define PA_CFPOW (PA_BCR+0x0302) /* CF Power control */
+#define PA_CFCDINTCLR (PA_BCR+0x0304) /* CF Insert Interrupt clear */
+#define PA_SCSMR (PA_BCR+0x0400) /* SCIF Serial mode control */
+#define PA_SCBRR (PA_BCR+0x0402) /* SCIF Bit rate control */
+#define PA_SCSCR (PA_BCR+0x0404) /* SCIF Serial control */
+#define PA_SCFDTR (PA_BCR+0x0406) /* SCIF Send FIFO control */
+#define PA_SCFSR (PA_BCR+0x0408) /* SCIF Serial status control */
+#define PA_SCFRDR (PA_BCR+0x040a) /* SCIF Receive FIFO control */
+#define PA_SCFCR (PA_BCR+0x040c) /* SCIF FIFO control */
+#define PA_SCFDR (PA_BCR+0x040e) /* SCIF FIFO data control */
+#define PA_SCLSR (PA_BCR+0x0412) /* SCIF Line Status control */
+#define PA_ICCR (PA_BCR+0x0500) /* Serial control */
+#define PA_SAR (PA_BCR+0x0502) /* Serial Slave control */
+#define PA_MDR (PA_BCR+0x0504) /* Serial Mode control */
+#define PA_ADR1 (PA_BCR+0x0506) /* Serial Address1 control */
+#define PA_DAR1 (PA_BCR+0x0546) /* Serial Data1 control */
+#define PA_VERREG (PA_BCR+0x0600) /* FPGA Version Register */
+
+#define PA_AX88796L 0xa5800400 /* AX88796L Area */
+#define PA_SC1602BSLB 0xa6000000 /* SC1602BSLB Area */
+#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
+#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
+#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
+#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
+
+#define IRLCNTR1 (PA_BCR + 0) /* Interrupt Control Register1 */
+
+#define IRQ_PCISLOT1 0 /* PCI Slot #1 IRQ */
+#define IRQ_PCISLOT2 1 /* PCI Slot #2 IRQ */
+#define IRQ_PCISLOT3 2 /* PCI Slot #3 IRQ */
+#define IRQ_PCISLOT4 3 /* PCI Slot #4 IRQ */
+#define IRQ_CFCARD 4 /* CF Card IRQ */
+#define IRQ_CFINST 5 /* CF Card Insert IRQ */
+#define IRQ_M66596 6 /* M66596 IRQ */
+#define IRQ_SDCARD 7 /* SD Card IRQ */
+#define IRQ_TUCHPANEL 8 /* Touch Panel IRQ */
+#define IRQ_SCI 9 /* SCI IRQ */
+#define IRQ_2SERIAL 10 /* Serial IRQ */
+#define IRQ_EXTENTION 11 /* EXTn IRQ */
+#define IRQ_ONETH 12 /* On board Ethernet IRQ */
+#define IRQ_PSW 13 /* Push Switch IRQ */
+#define IRQ_ZIGBEE 14 /* Ziggbee IO IRQ */
+
+#endif /* CONFIG_SH_R7780MP */
+
+#define __IO_PREFIX r7780rp
+#include <asm/io_generic.h>
+
+#endif /* __ASM_SH_RENESAS_R7780RP */
diff --git a/include/asm-sh/rts7751r2d/rts7751r2d.h b/include/asm-sh/rts7751r2d/rts7751r2d.h
index 4e09ba597e9a06..b112ae221fd1f4 100644
--- a/include/asm-sh/rts7751r2d/rts7751r2d.h
+++ b/include/asm-sh/rts7751r2d/rts7751r2d.h
@@ -41,8 +41,6 @@
#define PA_AX88796L 0xaa000400 /* AX88796L Area */
#define PA_VOYAGER 0xab000000 /* VOYAGER GX Area */
-#define PA_AREA5_IO 0xb4000000 /* Area 5 IO Memory */
-#define PA_AREA6_IO 0xb8000000 /* Area 6 IO Memory */
#define PA_IDE_OFFSET 0x1f0 /* CF IDE Offset */
#define AX88796L_IO_BASE 0x1000 /* AX88796L IO Base Address */
generated by cgit 1.2.3-korg (git 2.39.0) at 2024-05-18 00:25:11 +0000