diff options
| author | Colin Ngam <cngam@sgi.com> | 2005-04-25 13:07:00 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-04-25 13:07:00 -0700 |
| commit | 658b32cad9ae087bd34f35a925fd75b76d663d4e (patch) | |
| tree | b742c5e1e756912fe6f6a81ebb4a9db814c641e7 /include | |
| parent | be539c73b54dcc9f54fb2c2b70e204c93b616c9b (diff) | |
| download | linux-658b32cad9ae087bd34f35a925fd75b76d663d4e.tar.gz | |
[IA64-SGI] support variable length nasids in shub2
This patch enables our TIO IO chipset to support variable length nasids in
Shub2 chipset.
Signed-off-by: Colin Ngam <cngam@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ia64/sn/addrs.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/include/asm-ia64/sn/addrs.h b/include/asm-ia64/sn/addrs.h index c916bd22767a1..ae0bc99d573e1 100644 --- a/include/asm-ia64/sn/addrs.h +++ b/include/asm-ia64/sn/addrs.h @@ -154,8 +154,9 @@ * the chiplet id is zero. If we implement TIO-TIO dma, we might need * to insert a chiplet id into this macro. However, it is our belief * right now that this chiplet id will be ICE, which is also zero. + * Nasid starts on bit 40. */ -#define PHYS_TO_TIODMA(x) ( (((u64)(x) & NASID_MASK) << 2) | NODE_OFFSET(x)) +#define PHYS_TO_TIODMA(x) ( (((u64)(NASID_GET(x))) << 40) | NODE_OFFSET(x)) #define PHYS_TO_DMA(x) ( (((u64)(x) & NASID_MASK) >> 2) | NODE_OFFSET(x)) |