diff options
| author | Philipp Rosenberger <p.rosenberger@kunbus.com> | 2021-01-18 09:57:51 +0100 |
|---|---|---|
| committer | Alexandre Belloni <alexandre.belloni@bootlin.com> | 2021-01-26 00:26:16 +0100 |
| commit | b9ac079abefc1f1cbee8a0f7195bad1d32dc72c7 (patch) | |
| tree | fa8835b2ef13e22c4d95b9f44dca327bdc8a63c8 /drivers/rtc/rtc-pcf2127.c | |
| parent | 454ba154a62c8806e82a3581c5233a5176cd7dd7 (diff) | |
| download | linux-b9ac079abefc1f1cbee8a0f7195bad1d32dc72c7.tar.gz | |
rtc: pcf2127: Disable Power-On Reset Override
To resume normal operation after a total power loss (no or empty
battery) the "Power-On Reset Override (PORO)" facility needs to be
disabled.
The register reset value sets the PORO enabled and the data sheet
recommends setting it to disabled for normal operation.
From what I've seen on the PCF2127 and PCF2129 there is no event
generated at the interrupt pin (INT), as long the PORO bit is set. This
behavior is not documented in the manual.
Signed-off-by: Philipp Rosenberger <p.rosenberger@kunbus.com>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Link: https://lore.kernel.org/r/20210118085752.5759-2-p.rosenberger@kunbus.com
Diffstat (limited to 'drivers/rtc/rtc-pcf2127.c')
| -rw-r--r-- | drivers/rtc/rtc-pcf2127.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/drivers/rtc/rtc-pcf2127.c b/drivers/rtc/rtc-pcf2127.c index 68160d857ac1c..9cfc869b4f21c 100644 --- a/drivers/rtc/rtc-pcf2127.c +++ b/drivers/rtc/rtc-pcf2127.c @@ -26,6 +26,7 @@ /* Control register 1 */ #define PCF2127_REG_CTRL1 0x00 +#define PCF2127_BIT_CTRL1_POR_OVRD BIT(3) #define PCF2127_BIT_CTRL1_TSF1 BIT(4) /* Control register 2 */ #define PCF2127_REG_CTRL2 0x01 @@ -608,6 +609,13 @@ static int pcf2127_probe(struct device *dev, struct regmap *regmap, } /* + * The "Power-On Reset Override" facility prevents the RTC to do a reset + * after power on. For normal operation the PORO must be disabled. + */ + regmap_clear_bits(pcf2127->regmap, PCF2127_REG_CTRL1, + PCF2127_BIT_CTRL1_POR_OVRD); + + /* * Watchdog timer enabled and reset pin /RST activated when timed out. * Select 1Hz clock source for watchdog timer. * Note: Countdown timer disabled and not available. |