diff options
| author | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 09:20:47 -0800 |
|---|---|---|
| committer | Linus Torvalds <torvalds@g5.osdl.org> | 2006-03-21 09:20:47 -0800 |
| commit | 28c006c1f09ea92d4f2585a087a188955ce3f64c (patch) | |
| tree | 2615749653cd3ba4852d2f5ed22f21eec0cd5712 /arch | |
| parent | cbe037b46f564188045937e6006c5c1d6093618a (diff) | |
| parent | 7abe53155b77c31028a7158883bc9aac705790da (diff) | |
| download | linux-28c006c1f09ea92d4f2585a087a188955ce3f64c.tar.gz | |
Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm:
[ARM] Fix cosmetic typo in asm/irq.h
[ARM] 3367/1: CLCD mode no longer supported on the RealView boards
[ARM] 3366/1: Allow the 16bpp mode configuration in the CLCD control register
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-realview/core.c | 28 |
1 files changed, 2 insertions, 26 deletions
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c index 4303d988c4bf3..d13270c5d7cde 100644 --- a/arch/arm/mach-realview/core.c +++ b/arch/arm/mach-realview/core.c @@ -202,11 +202,6 @@ struct clk realview_clcd_clk = { /* * CLCD support. */ -#define SYS_CLCD_MODE_MASK (3 << 0) -#define SYS_CLCD_MODE_888 (0 << 0) -#define SYS_CLCD_MODE_5551 (1 << 0) -#define SYS_CLCD_MODE_565_RLSB (2 << 0) -#define SYS_CLCD_MODE_565_BLSB (3 << 0) #define SYS_CLCD_NLCDIOON (1 << 2) #define SYS_CLCD_VDDPOSSWITCH (1 << 3) #define SYS_CLCD_PWR3V5SWITCH (1 << 4) @@ -360,29 +355,10 @@ static void realview_clcd_enable(struct clcd_fb *fb) void __iomem *sys_clcd = __io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_CLCD_OFFSET; u32 val; - val = readl(sys_clcd); - val &= ~SYS_CLCD_MODE_MASK; - - switch (fb->fb.var.green.length) { - case 5: - val |= SYS_CLCD_MODE_5551; - break; - case 6: - val |= SYS_CLCD_MODE_565_RLSB; - break; - case 8: - val |= SYS_CLCD_MODE_888; - break; - } - - /* - * Set the MUX - */ - writel(val, sys_clcd); - /* - * And now enable the PSUs + * Enable the PSUs */ + val = readl(sys_clcd); val |= SYS_CLCD_NLCDIOON | SYS_CLCD_PWR3V5SWITCH; writel(val, sys_clcd); } |