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| author | Lennert Buytenhek <buytenh@wantstofly.org> | 2006-03-28 21:00:40 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2006-03-28 21:00:40 +0100 |
| commit | 23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa (patch) | |
| tree | 56636558e8cdeee0739e7d8c82d66ffe625340b3 /arch/arm/mm/Kconfig | |
| parent | de4533a04eb4f66dbef71f59a9c118256b886823 (diff) | |
| download | linux-23bdf86aa06ebe71bcbf6b7d25de9958c6ab33fa.tar.gz | |
[ARM] 3377/2: add support for intel xsc3 core
Patch from Lennert Buytenhek
This patch adds support for the new XScale v3 core. This is an
ARMv5 ISA core with the following additions:
- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)
I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.
L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.
There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch/arm/mm/Kconfig')
| -rw-r--r-- | arch/arm/mm/Kconfig | 19 |
1 files changed, 18 insertions, 1 deletions
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig index e680c5fd93b51..c55b739e10baf 100644 --- a/arch/arm/mm/Kconfig +++ b/arch/arm/mm/Kconfig @@ -239,6 +239,17 @@ config CPU_XSCALE select CPU_CACHE_VIVT select CPU_TLB_V4WBI +# XScale Core Version 3 +config CPU_XSC3 + bool + depends on ARCH_IXP23XX + default y + select CPU_32v5 + select CPU_ABRT_EV5T + select CPU_CACHE_VIVT + select CPU_TLB_V4WBI + select IO_36 + # ARMv6 config CPU_V6 bool "Support ARM V6 processor" @@ -361,11 +372,17 @@ config CPU_TLB_V4WBI config CPU_TLB_V6 bool +# +# CPU supports 36-bit I/O +# +config IO_36 + bool + comment "Processor Features" config ARM_THUMB bool "Support Thumb user binaries" - depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_V6 + depends on CPU_ARM720T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_V6 default y help Say Y if you want to include kernel support for running user space |