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| author | Dean Nelson <dcn@sgi.com> | 2005-03-23 19:08:00 -0700 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2005-05-03 12:11:38 -0700 |
| commit | 21e37283909c12e300ab87c20f5addc878cda9f9 (patch) | |
| tree | 0a03d3c0c90d8108eefb985272d0d49f31c2c827 | |
| parent | 7223a93a5321f84337647aef62ef947afd8df41a (diff) | |
| download | linux-21e37283909c12e300ab87c20f5addc878cda9f9.tar.gz | |
[IA64-SGI] Define some additional SHub1 and Shub2 register symbols
Define some additional SHub1 and SHub2 register symbols.
Signed-off-by: Dean Nelson <dcn@sgi.com>
Signed-off-by: Tony Luck <tony.luck@intel.com>
| -rw-r--r-- | include/asm-ia64/sn/shub_mmr.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/include/asm-ia64/sn/shub_mmr.h b/include/asm-ia64/sn/shub_mmr.h index 2f885088e09569..323fa0cd8d83d6 100644 --- a/include/asm-ia64/sn/shub_mmr.h +++ b/include/asm-ia64/sn/shub_mmr.h @@ -385,6 +385,17 @@ #define SH_EVENT_OCCURRED_RTC3_INT_MASK 0x0000000004000000 /* ==================================================================== */ +/* Register "SH_IPI_ACCESS" */ +/* CPU interrupt Access Permission Bits */ +/* ==================================================================== */ + +#define SH1_IPI_ACCESS 0x0000000110060480 +#define SH2_IPI_ACCESS0 0x0000000010060c00 +#define SH2_IPI_ACCESS1 0x0000000010060c80 +#define SH2_IPI_ACCESS2 0x0000000010060d00 +#define SH2_IPI_ACCESS3 0x0000000010060d80 + +/* ==================================================================== */ /* Register "SH_INT_CMPB" */ /* RTC Compare Value for Processor B */ /* ==================================================================== */ @@ -429,6 +440,19 @@ #define SH_INT_CMPD_REAL_TIME_CMPD_SHFT 0 #define SH_INT_CMPD_REAL_TIME_CMPD_MASK 0x007fffffffffffff +/* ==================================================================== */ +/* Register "SH_MD_DQLP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH1_MD_DQLP_MMR_DIR_PRIVEC0 0x0000000100030300 + +/* ==================================================================== */ +/* Register "SH_MD_DQRP_MMR_DIR_PRIVEC0" */ +/* privilege vector for acc=0 */ +/* ==================================================================== */ + +#define SH1_MD_DQRP_MMR_DIR_PRIVEC0 0x0000000100050300 /* ==================================================================== */ /* Some MMRs are functionally identical (or close enough) on both SHUB1 */ |