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| author | Sekhar Nori <nsekhar@ti.com> | 2020-06-17 15:42:10 +0530 |
|---|---|---|
| committer | Sekhar Nori <nsekhar@ti.com> | 2020-07-14 00:42:18 +0530 |
| commit | 9e38c9c8ec09141d30ff5a0038f9a6e4a61457f2 (patch) | |
| tree | 10582d3b5712fa9f34474ccf75666e92dc62634f | |
| parent | 726bef89d08b66b38d6bdfbbd8cb2dd54be0e1c5 (diff) | |
| download | linux-dt-9e38c9c8ec09141d30ff5a0038f9a6e4a61457f2.tar.gz | |
Add k3-am654-pcie-usb3.dtso
Add support for PCIe x1 lane + USB 3.0 card for AM654x EVM.
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
| -rw-r--r-- | Makefile | 3 | ||||
| -rw-r--r-- | arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso | 66 |
2 files changed, 68 insertions, 1 deletions
@@ -122,7 +122,8 @@ dtb-tests-arm64 := \ ti/k3-am654-base-board.dtb,ti/k3-am654-evm-hdmi.dtbo \ ti/k3-am654-base-board.dtb,ti/k3-am654-evm-oldi-lcd1evm.dtbo \ ti/k3-am654-base-board.dtb,ti/k3-am654-evm-tc358876.dtbo \ - ti/k3-am654-base-board.dtb,ti/k3-am654-pcie-usb2.dtbo + ti/k3-am654-base-board.dtb,ti/k3-am654-pcie-usb2.dtbo \ + ti/k3-am654-base-board.dtb,ti/k3-am654-pcie-usb3.dtbo dtb-tests-arm64 += \ ti/k3-j721e-common-proc-board.dtb,ti/k3-j721e-common-proc-board-infotainment.dtbo diff --git a/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso new file mode 100644 index 0000000..bb7090c --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-am654-pcie-usb3.dtso @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/** + * DT overlay for SERDES personality card: 1lane PCIe + USB3.0 DRD on AM654 EVM + * + * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/ + */ + +/dts-v1/; +/plugin/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/phy/phy.h> +#include <dt-bindings/phy/phy-am654-serdes.h> +#include <dt-bindings/pinctrl/k3.h> + +&serdes1 { + status = "okay"; +}; + +&pcie1_rc { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; + reset-gpios = <&pca9555 5 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&pcie1_ep { + num-lanes = <1>; + phys = <&serdes1 PHY_TYPE_PCIE 0>; + phy-names = "pcie-phy0"; +}; + +&main_pmx0 { + usb0_pins_default: usb0_pins_default { + pinctrl-single,pins = < + AM65X_IOPAD(0x02bc, PIN_OUTPUT, 0) /* (AD9) USB0_DRVVBUS */ + >; + }; +}; + +&serdes0 { + status = "okay"; + assigned-clocks = <&k3_clks 153 4>, <&serdes0 AM654_SERDES_CMU_REFCLK>; + assigned-clock-parents = <&k3_clks 153 7>, <&k3_clks 153 4>; +}; + +&dwc3_0 { + status = "okay"; + assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */ + <&k3_clks 151 8>; /* set PIPE3_TXB_CLK to WIZ8B2M4VSB */ + phys = <&serdes0 PHY_TYPE_USB3 0>; + phy-names = "usb3-phy"; +}; + +&usb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb0_pins_default>; + dr_mode = "host"; + maximum-speed = "super-speed"; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; +}; + +&usb0_phy { + status = "okay"; +}; |