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| author | Fabrizio Castro <fabrizio.castro@bp.renesas.com> | 2018-07-24 11:32:32 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben.hutchings@codethink.co.uk> | 2018-08-24 19:06:50 +0100 |
| commit | 27bcc133c09448eb11470c08ff0bba9d8276d726 (patch) | |
| tree | 04345476d03159044f8dc1125ba89a8cf76f9b1f | |
| parent | 4d769b2b8749e89dfc7ea179a44f652dcfbedb37 (diff) | |
| download | linux-cip-27bcc133c09448eb11470c08ff0bba9d8276d726.tar.gz | |
ARM: dts: r8a7745: Add PWM SoC support
Add the definitions for pwm[0123456] to the SoC .dtsi.
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit 3711d0ede24d2e3c90ae10e1a79746ac87169609)
(modified clocks and power-domains properties. removed resets
property)
Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
| -rw-r--r-- | arch/arm/boot/dts/r8a7745.dtsi | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index 68ef545e69df55..4163ae459b974f 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -772,6 +772,69 @@ status = "disabled"; }; + pwm0: pwm@e6e30000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e30000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm1: pwm@e6e31000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e31000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm2: pwm@e6e32000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e32000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm3: pwm@e6e33000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e33000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm4: pwm@e6e34000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e34000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm5: pwm@e6e35000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e35000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + + pwm6: pwm@e6e36000 { + compatible = "renesas,pwm-r8a7745", "renesas,pwm-rcar"; + reg = <0 0xe6e36000 0 0x8>; + clocks = <&mstp5_clks R8A7745_CLK_PWM>; + power-domains = <&cpg_clocks>; + #pwm-cells = <2>; + status = "disabled"; + }; + pci0: pci@ee090000 { compatible = "renesas,pci-r8a7745", "renesas,pci-rcar-gen2"; |