x86: swapgs ctxt refresh

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

1 files changed, 23 insertions, 23 deletions

diff --git a/queue/x86-speculation-Prepare-entry-code-for-Spectre-v1-sw.patch b/queue/x86-speculation-Prepare-entry-code-for-Spectre-v1-sw.patch
index fc7b4b1..23b5b05 100644
--- a/queue/x86-speculation-Prepare-entry-code-for-Spectre-v1-sw.patch
+++ b/queue/x86-speculation-Prepare-entry-code-for-Spectre-v1-sw.patch
@@ -1,4 +1,4 @@
-From 18ec54fdd6d18d92025af097cd042a75cf0ea24c Mon Sep 17 00:00:00 2001
+From f1b00583b93d36978e2b669bbf9ae86137d7d8ce Mon Sep 17 00:00:00 2001
 From: Josh Poimboeuf <jpoimboe@redhat.com>
 Date: Mon, 8 Jul 2019 11:52:25 -0500
 Subject: [PATCH] x86/speculation: Prepare entry code for Spectre v1 swapgs
@@ -60,13 +60,13 @@ Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
 Reviewed-by: Dave Hansen <dave.hansen@intel.com>
 
 diff --git a/arch/x86/entry/calling.h b/arch/x86/entry/calling.h
-index 9f1f9e3b8230..7ce7ac9d9d3f 100644
+index 352e70cd33e8..db63ec9707ec 100644
 --- a/arch/x86/entry/calling.h
 +++ b/arch/x86/entry/calling.h
-@@ -314,6 +314,23 @@ For 32-bit we have the following conventions - kernel is built with
- 
+@@ -185,6 +185,23 @@ For 32-bit we have the following conventions - kernel is built with
+ #ifdef CONFIG_FRAME_POINTER
+ 	leaq 1+\ptregs_offset(%rsp), %rbp
  #endif
- 
 +/*
 + * Mitigate Spectre v1 for conditional swapgs code paths.
 + *
@@ -84,14 +84,14 @@ index 9f1f9e3b8230..7ce7ac9d9d3f 100644
 +	ALTERNATIVE "", "lfence", X86_FEATURE_FENCE_SWAPGS_KERNEL
 +.endm
 +
- .macro STACKLEAK_ERASE_NOCLOBBER
- #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
- 	PUSH_AND_CLEAR_REGS
+ .endm
+ 
+ #ifdef CONFIG_PAGE_TABLE_ISOLATION
 diff --git a/arch/x86/entry/entry_64.S b/arch/x86/entry/entry_64.S
-index a829dd3117d0..57a0d96d6beb 100644
+index 6962318015f7..d584bdaf1eaa 100644
 --- a/arch/x86/entry/entry_64.S
 +++ b/arch/x86/entry/entry_64.S
-@@ -519,7 +519,7 @@ ENTRY(interrupt_entry)
+@@ -569,7 +569,7 @@ ENTRY(interrupt_entry)
  	testb	$3, CS-ORIG_RAX+8(%rsp)
  	jz	1f
  	SWAPGS
@@ -100,7 +100,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  	/*
  	 * Switch to the thread stack. The IRET frame and orig_ax are
  	 * on the stack, as well as the return address. RDI..R12 are
-@@ -549,8 +549,10 @@ ENTRY(interrupt_entry)
+@@ -599,8 +599,10 @@ ENTRY(interrupt_entry)
  	UNWIND_HINT_FUNC
  
  	movq	(%rdi), %rdi
@@ -112,8 +112,8 @@ index a829dd3117d0..57a0d96d6beb 100644
  	PUSH_AND_CLEAR_REGS save_ret=1
  	ENCODE_FRAME_POINTER 8
  
-@@ -1221,6 +1223,13 @@ ENTRY(paranoid_entry)
- 	 */
+@@ -1208,6 +1210,13 @@ ENTRY(paranoid_entry)
+ 1:
  	SAVE_AND_SWITCH_TO_KERNEL_CR3 scratch_reg=%rax save_reg=%r14
  
 +	/*
@@ -126,7 +126,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  	ret
  END(paranoid_entry)
  
-@@ -1271,6 +1280,7 @@ ENTRY(error_entry)
+@@ -1256,6 +1265,7 @@ ENTRY(error_entry)
  	 * from user mode due to an IRET fault.
  	 */
  	SWAPGS
@@ -134,7 +134,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  	/* We have user CR3.  Change to kernel CR3. */
  	SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
  
-@@ -1292,6 +1302,8 @@ ENTRY(error_entry)
+@@ -1277,6 +1287,8 @@ ENTRY(error_entry)
  	CALL_enter_from_user_mode
  	ret
  
@@ -143,7 +143,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  .Lerror_entry_done:
  	TRACE_IRQS_OFF
  	ret
-@@ -1310,7 +1322,7 @@ ENTRY(error_entry)
+@@ -1295,7 +1307,7 @@ ENTRY(error_entry)
  	cmpq	%rax, RIP+8(%rsp)
  	je	.Lbstep_iret
  	cmpq	$.Lgs_change, RIP+8(%rsp)
@@ -152,7 +152,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  
  	/*
  	 * hack: .Lgs_change can fail with user gsbase.  If this happens, fix up
-@@ -1318,6 +1330,7 @@ ENTRY(error_entry)
+@@ -1303,6 +1315,7 @@ ENTRY(error_entry)
  	 * .Lgs_change's error handler with kernel gsbase.
  	 */
  	SWAPGS
@@ -160,7 +160,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  	SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
  	jmp .Lerror_entry_done
  
-@@ -1332,6 +1345,7 @@ ENTRY(error_entry)
+@@ -1317,6 +1330,7 @@ ENTRY(error_entry)
  	 * gsbase and CR3.  Switch to kernel gsbase and CR3:
  	 */
  	SWAPGS
@@ -168,7 +168,7 @@ index a829dd3117d0..57a0d96d6beb 100644
  	SWITCH_TO_KERNEL_CR3 scratch_reg=%rax
  
  	/*
-@@ -1423,6 +1437,7 @@ ENTRY(nmi)
+@@ -1408,6 +1422,7 @@ ENTRY(nmi)
  
  	swapgs
  	cld
@@ -177,18 +177,18 @@ index a829dd3117d0..57a0d96d6beb 100644
  	movq	%rsp, %rdx
  	movq	PER_CPU_VAR(cpu_current_top_of_stack), %rsp
 diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
-index 998c2cc08363..4393278666d9 100644
+index 523eacd5cd24..efb46a3b9e5d 100644
 --- a/arch/x86/include/asm/cpufeatures.h
 +++ b/arch/x86/include/asm/cpufeatures.h
-@@ -281,6 +281,8 @@
+@@ -279,6 +279,8 @@
  #define X86_FEATURE_CQM_OCCUP_LLC	(11*32+ 1) /* LLC occupancy monitoring */
  #define X86_FEATURE_CQM_MBM_TOTAL	(11*32+ 2) /* LLC Total MBM monitoring */
  #define X86_FEATURE_CQM_MBM_LOCAL	(11*32+ 3) /* LLC Local MBM monitoring */
 +#define X86_FEATURE_FENCE_SWAPGS_USER	(11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
 +#define X86_FEATURE_FENCE_SWAPGS_KERNEL	(11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
  
- /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
- #define X86_FEATURE_AVX512_BF16		(12*32+ 5) /* AVX512 BFLOAT16 instructions */
+ /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
+ #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 -- 
 2.7.4