add in RDRAND flag to x86 proc features

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>

3 files changed, 68 insertions, 0 deletions

diff --git a/queue/series b/queue/series
index 9882c82..288ee1b 100644
--- a/queue/series
+++ b/queue/series
@@ -149,6 +149,8 @@ USB-quirks-adding-more-quirky-webcams-to-avoid-squea.patch
 
 # updates relating to /dev/random -- based on 3.4.9 queue.
 random-simplify-fips-mode.patch
+x86-cpu-Add-CPU-flags-for-F16C-and-RDRND.patch
+x86-cpufeature-Update-CPU-feature-RDRND-to-RDRAND.patch
 random-Add-support-for-architectural-random-hooks.patch
 x86-random-Architectural-inlines-to-get-random-integ.patch
 fix-typo-thinko-in-get_random_bytes.patch
diff --git a/queue/x86-cpu-Add-CPU-flags-for-F16C-and-RDRND.patch b/queue/x86-cpu-Add-CPU-flags-for-F16C-and-RDRND.patch
new file mode 100644
index 0000000..9caeda6
--- /dev/null
+++ b/queue/x86-cpu-Add-CPU-flags-for-F16C-and-RDRND.patch
@@ -0,0 +1,29 @@
+From 1c0ad749f3793123d73ec1895a461aeb229fc461 Mon Sep 17 00:00:00 2001
+From: "H. Peter Anvin" <hpa@zytor.com>
+Date: Wed, 7 Jul 2010 10:15:12 -0700
+Subject: [PATCH] x86, cpu: Add CPU flags for F16C and RDRND
+
+commit 24da9c26f3050aee9314ec09930a24c80fe76352 upstream.
+
+Add support for the newly documented F16C (16-bit floating point
+conversions) and RDRND (RDRAND instruction) CPU feature flags.
+
+Signed-off-by: H. Peter Anvin <hpa@zytor.com>
+Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
+index 5d06401..0cfa2fb 100644
+--- a/arch/x86/include/asm/cpufeature.h
++++ b/arch/x86/include/asm/cpufeature.h
+@@ -124,6 +124,8 @@
+ #define X86_FEATURE_XSAVE	(4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+ #define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
+ #define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
++#define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */
++#define X86_FEATURE_RDRND	(4*32+30) /* The RDRAND instruction */
+ #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */
+ 
+ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
+-- 
+1.7.12.rc1.1.gbce1580
+
diff --git a/queue/x86-cpufeature-Update-CPU-feature-RDRND-to-RDRAND.patch b/queue/x86-cpufeature-Update-CPU-feature-RDRND-to-RDRAND.patch
new file mode 100644
index 0000000..71a62f5
--- /dev/null
+++ b/queue/x86-cpufeature-Update-CPU-feature-RDRND-to-RDRAND.patch
@@ -0,0 +1,37 @@
+From c75e82310dc6a352e04c84a41262da419b4a1e88 Mon Sep 17 00:00:00 2001
+From: Kees Cook <kees.cook@canonical.com>
+Date: Tue, 24 May 2011 16:29:26 -0700
+Subject: [PATCH] x86, cpufeature: Update CPU feature RDRND to RDRAND
+
+commit 7ccafc5f75c87853f3c49845d5a884f2376e03ce upstream.
+
+The Intel manual changed the name of the CPUID bit to match the
+instruction name. We should follow suit for sanity's sake. (See Intel SDM
+Volume 2, Table 3-20 "Feature Information Returned in the ECX Register".)
+
+[ hpa: we can only do this at this time because there are currently no CPUs
+  with this feature on the market, hence this is pre-hardware enabling.
+  However, Cc:'ing stable so that stable can present a consistent ABI. ]
+
+Signed-off-by: Kees Cook <kees.cook@canonical.com>
+Link: http://lkml.kernel.org/r/20110524232926.GA27728@outflux.net
+Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
+Cc: Fenghua Yu <fenghua.yu@intel.com>
+Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
+
+diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h
+index 0cfa2fb..d79434e 100644
+--- a/arch/x86/include/asm/cpufeature.h
++++ b/arch/x86/include/asm/cpufeature.h
+@@ -125,7 +125,7 @@
+ #define X86_FEATURE_OSXSAVE	(4*32+27) /* "" XSAVE enabled in the OS */
+ #define X86_FEATURE_AVX		(4*32+28) /* Advanced Vector Extensions */
+ #define X86_FEATURE_F16C	(4*32+29) /* 16-bit fp conversions */
+-#define X86_FEATURE_RDRND	(4*32+30) /* The RDRAND instruction */
++#define X86_FEATURE_RDRAND	(4*32+30) /* The RDRAND instruction */
+ #define X86_FEATURE_HYPERVISOR	(4*32+31) /* Running on a hypervisor */
+ 
+ /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
+-- 
+1.7.12.rc1.1.gbce1580
+