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author | Eric Auger <eric.auger@redhat.com> | 2020-04-03 09:13:24 +0200 |
---|---|---|
committer | Andrew Jones <drjones@redhat.com> | 2020-04-03 10:03:45 +0200 |
commit | ca42f29a12344d3be60dfd0c4f6aba09b2dbc016 (patch) | |
tree | d1814dde0e1c35b5182f3797ff89c9e72d29100c | |
parent | 66fee034136c97c666d85d099b78a93f5d206bc1 (diff) | |
download | kvm-unit-tests-ca42f29a12344d3be60dfd0c4f6aba09b2dbc016.tar.gz |
arm: pmu: test 32-bit <-> 64-bit transitions
Test configurations where we transit from 32b to 64b
counters and conversely. Also tests configuration where
chain counters are configured but only one counter is
enabled.
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Signed-off-by: Andrew Jones <drjones@redhat.com>
-rw-r--r-- | arm/pmu.c | 138 | ||||
-rw-r--r-- | arm/unittests.cfg | 6 |
2 files changed, 144 insertions, 0 deletions
@@ -57,6 +57,7 @@ #define ALL_SET 0xFFFFFFFF #define ALL_CLEAR 0x0 #define PRE_OVERFLOW 0xFFFFFFF0 +#define PRE_OVERFLOW2 0xFFFFFFDC struct pmu { unsigned int version; @@ -144,6 +145,7 @@ static void test_mem_access(void) {} static void test_sw_incr(void) {} static void test_chained_counters(void) {} static void test_chained_sw_incr(void) {} +static void test_chain_promotion(void) {} #elif defined(__aarch64__) #define ID_AA64DFR0_PERFMON_SHIFT 8 @@ -594,6 +596,138 @@ static void test_chained_sw_incr(void) read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); } +static void test_chain_promotion(void) +{ + uint32_t events[] = {MEM_ACCESS, CHAIN}; + void *addr = malloc(PAGE_SIZE); + + if (!satisfy_prerequisites(events, ARRAY_SIZE(events))) + return; + + /* Only enable CHAIN counter */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x2, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn_el0(pmevcntr, 0), + "chain counter not counting if even counter is disabled"); + + /* Only enable even counter */ + pmu_reset(); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW); + write_sysreg_s(0x1, PMCNTENSET_EL0); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(!read_regn_el0(pmevcntr, 1) && (read_sysreg(pmovsclr_el0) == 0x1), + "odd counter did not increment on overflow if disabled"); + report_info("MEM_ACCESS counter #0 has value %ld", + read_regn_el0(pmevcntr, 0)); + report_info("CHAIN counter #1 has value %ld", + read_regn_el0(pmevcntr, 1)); + report_info("overflow counter %ld", read_sysreg(pmovsclr_el0)); + + /* start at 0xFFFFFFDC, +20 with CHAIN enabled, +20 with CHAIN disabled */ + pmu_reset(); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* disable the CHAIN event */ + write_sysreg_s(0x2, PMCNTENCLR_EL0); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + report(read_sysreg(pmovsclr_el0) == 0x1, + "should have triggered an overflow on #0"); + report(!read_regn_el0(pmevcntr, 1), + "CHAIN counter #1 shouldn't have incremented"); + + /* start at 0xFFFFFFDC, +20 with CHAIN disabled, +20 with CHAIN enabled */ + + pmu_reset(); + write_sysreg_s(0x1, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + report_info("counter #0 = 0x%lx, counter #1 = 0x%lx overflow=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* enable the CHAIN event */ + write_sysreg_s(0x3, PMCNTENSET_EL0); + isb(); + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), + "CHAIN counter enabled: CHAIN counter was incremented and no overflow"); + + report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", + read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as MEM_ACCESS/CPU_CYCLES and move to CHAIN/MEM_ACCESS */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + isb(); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + /* 0 becomes CHAINED */ + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + write_regn_el0(pmevcntr, 1, 0x0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("MEM_ACCESS counter #0 has value 0x%lx", + read_regn_el0(pmevcntr, 0)); + + report((read_regn_el0(pmevcntr, 1) == 1) && !read_sysreg(pmovsclr_el0), + "32b->64b: CHAIN counter incremented and no overflow"); + + report_info("CHAIN counter #1 = 0x%lx, overflow=0x%lx", + read_regn_el0(pmevcntr, 1), read_sysreg(pmovsclr_el0)); + + /* start as CHAIN/MEM_ACCESS and move to MEM_ACCESS/CPU_CYCLES */ + pmu_reset(); + write_regn_el0(pmevtyper, 0, MEM_ACCESS | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevtyper, 1, CHAIN | PMEVTYPER_EXCLUDE_EL0); + write_regn_el0(pmevcntr, 0, PRE_OVERFLOW2); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report_info("counter #0=0x%lx, counter #1=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1)); + + write_sysreg_s(0x0, PMCNTENSET_EL0); + write_regn_el0(pmevtyper, 1, CPU_CYCLES | PMEVTYPER_EXCLUDE_EL0); + write_sysreg_s(0x3, PMCNTENSET_EL0); + + mem_access_loop(addr, 20, pmu.pmcr_ro | PMU_PMCR_E); + report(read_sysreg(pmovsclr_el0) == 1, + "overflow is expected on counter 0"); + report_info("counter #0=0x%lx, counter #1=0x%lx overflow=0x%lx", + read_regn_el0(pmevcntr, 0), read_regn_el0(pmevcntr, 1), + read_sysreg(pmovsclr_el0)); +} + #endif /* @@ -792,6 +926,10 @@ int main(int argc, char *argv[]) report_prefix_push(argv[1]); test_chained_sw_incr(); report_prefix_pop(); + } else if (strcmp(argv[1], "pmu-chain-promotion") == 0) { + report_prefix_push(argv[1]); + test_chain_promotion(); + report_prefix_pop(); } else { report_abort("Unknown sub-test '%s'", argv[1]); } diff --git a/arm/unittests.cfg b/arm/unittests.cfg index d31dcbf..1b0c8c8 100644 --- a/arm/unittests.cfg +++ b/arm/unittests.cfg @@ -108,6 +108,12 @@ groups = pmu arch = arm64 extra_params = -append 'pmu-chained-sw-incr' +[pmu-chain-promotion] +file = pmu.flat +groups = pmu +arch = arm64 +extra_params = -append 'pmu-chain-promotion' + # Test PMU support (TCG) with -icount IPC=1 #[pmu-tcg-icount-1] #file = pmu.flat |