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| author | Sean Christopherson <sean.j.christopherson@intel.com> | 2020-03-09 20:47:29 -0700 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-03-31 11:14:44 -0400 |
| commit | 41692a119aa03780fab3c376080f602a7e4ad16b (patch) | |
| tree | c9b4e9f57f2d775a2578e35f99e58e6c35acc890 | |
| parent | e613718764740c409a5f22705f07c824796ecb53 (diff) | |
| download | kvm-unit-tests-41692a119aa03780fab3c376080f602a7e4ad16b.tar.gz | |
x86: Reload SS when switching to 5-level page tables
Load SS with a valid segment when switching to 5-level page tables to
avoid taking a #SS due to a NULL segment when making a CALL with paging
disabled.
The "access" test calls setup_5level_page_table()/switch_to_5level()
after generating and handling usermode exceptions. Per Intel's SDM,
SS is nullified on an exception that changes CPL:
The new SS is set to NULL if there is a change in CPL.
Signed-off-by: Sean Christopherson <sean.j.christopherson@intel.com>
Message-Id: <20200310034729.2941-1-sean.j.christopherson@intel.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | x86/cstart64.S | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/x86/cstart64.S b/x86/cstart64.S index 6c1c87d..cffbb07 100644 --- a/x86/cstart64.S +++ b/x86/cstart64.S @@ -159,6 +159,9 @@ switch_to_5level: bts $12, %eax mov %eax, %cr4 + mov $0x10, %ax + mov %ax, %ss + call enter_long_mode jmpl $8, $lvl5 |