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| author | Jean-Philippe Brucker <jean-philippe.brucker@arm.com> | 2017-11-17 14:59:16 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-01-29 15:11:53 +0000 |
| commit | a508ea95f954da77d87f1a5d6ee1d38b7b964a76 (patch) | |
| tree | 9505a351a3e4ca2a012ffa218dd74820d53e2728 | |
| parent | b7af514c7ca3d87b2e2a2da9129b2bc4c86f78de (diff) | |
| download | kvmtool-a508ea95f954da77d87f1a5d6ee1d38b7b964a76.tar.gz | |
virtio/pci: Use port I/O for configuration registers by default
Modern virtio PCI is allowed to use both memory and I/O BARs for the
config space, but legacy devices must use I/O for BAR0, as specified by
Virtio v1.0 cs04:
4.1.5.1.1.1 Legacy Interface: A Note on Device Layout Detection
"Transitional devices MUST expose the Legacy Interface in I/O space in
BAR0."
What virtio calls "I/O space" is most certainly port I/O, as hinted by the
discussion in 4.1.4 Virtio Structure PCI Capabilities, where it
distinguishes "memory BARs" from "I/O BARs". This is also the conclusion
made by SeaBIOS [1], which only looks for port I/O in BAR0 when driving a
transitional device.
I think MMIO was made the default by a463650caad6 ("kvm tools: pci: add
MMIO interface to virtio-pci devices") to support ARM targets, but we
support PIO as well as MMIO nowadays. So let's make the legacy virtio
implementation comply with the specification and use port I/O for BAR0.
[1] https://patchwork.kernel.org/patch/10038927/
Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | virtio/pci.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/virtio/pci.c b/virtio/pci.c index 2054c7ba..9a199013 100644 --- a/virtio/pci.c +++ b/virtio/pci.c @@ -450,10 +450,10 @@ int virtio_pci__init(struct kvm *kvm, void *dev, struct virtio_device *vdev, .class[2] = (class >> 16) & 0xff, .subsys_vendor_id = cpu_to_le16(PCI_SUBSYSTEM_VENDOR_ID_REDHAT_QUMRANET), .subsys_id = cpu_to_le16(subsys_id), - .bar[0] = cpu_to_le32(vpci->mmio_addr - | PCI_BASE_ADDRESS_SPACE_MEMORY), - .bar[1] = cpu_to_le32(vpci->port_addr + .bar[0] = cpu_to_le32(vpci->port_addr | PCI_BASE_ADDRESS_SPACE_IO), + .bar[1] = cpu_to_le32(vpci->mmio_addr + | PCI_BASE_ADDRESS_SPACE_MEMORY), .bar[2] = cpu_to_le32(vpci->msix_io_block | PCI_BASE_ADDRESS_SPACE_MEMORY), .status = cpu_to_le16(PCI_STATUS_CAP_LIST), |