Fix subfolder dependency generation

When building an object "foo.o", kvmtool also creates a ".foo.o.d" file,
using the dependency generation feature of CPP. This file describes in
Makefile format all headers included by foo.c. When one header is
modified, make rebuilds all objects that include it.

Dependency files in subfolders are currently ignored by make, because
the target doesn't contain the right prefix. For example virtio/.blk.o.d
has target "blk.o" instead of "virtio/blk.o". As a result, rebuilding
kvmtool without first issuing a make clean can introduce sneaky bugs,
where different objects use mismatched headers. To write the right
targets in dependency files, add a -MT argument to CPP.

Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>

1 files changed, 1 insertions, 1 deletions

diff --git a/Makefile b/Makefile
index 93dc0673..dfa0b62d 100644
--- a/Makefile
+++ b/Makefile
@@ -364,7 +364,7 @@ all: $(PROGRAM) $(PROGRAM_ALIAS)
 
 # CFLAGS used when building objects
 # This is intentionally not assigned using :=
-c_flags	= -Wp,-MD,$(depfile) $(CFLAGS)
+c_flags	= -Wp,-MD,$(depfile) -Wp,-MT,$@ $(CFLAGS)
 
 # When building -static all objects are built with appropriate flags, which
 # may differ between static & dynamic .o.  The objects are separated into