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| author | Antonio Borneo <borneo.antonio@gmail.com> | 2019-05-06 15:07:19 +0200 |
|---|---|---|
| committer | Antonio Borneo <borneo.antonio@gmail.com> | 2020-05-09 14:40:52 +0100 |
| commit | e41c3f78d13b9450c5c96d7188d8ec775df8f4ad (patch) | |
| tree | b54aa5da8fe8fda57d0a013672f474a193b33a12 | |
| parent | 4625257007b520c739a9e9437b97c7c7c7d60158 (diff) | |
| download | openocd-jz4730-e41c3f78d13b9450c5c96d7188d8ec775df8f4ad.tar.gz | |
coding style: wrap lines longer than 120 chars
The coding style is quite permissive allowing 120 chars per line,
but abuses are still present.
Fix them, wrapping the lines.
Change-Id: I94d66b651d759a60ec35f7ba115c43933e70ed69
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5626
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
| -rw-r--r-- | src/target/dsp563xx_once.c | 3 | ||||
| -rw-r--r-- | src/target/dsp5680xx.c | 13 |
2 files changed, 13 insertions, 3 deletions
diff --git a/src/target/dsp563xx_once.c b/src/target/dsp563xx_once.c index 65ef7070b..624474d1b 100644 --- a/src/target/dsp563xx_once.c +++ b/src/target/dsp563xx_once.c @@ -66,7 +66,8 @@ static inline int dsp563xx_write_dr_u32(struct jtag_tap *tap, uint32_t *dr_in, u } /** single word instruction */ -static inline int dsp563xx_once_ir_exec(struct jtag_tap *tap, int flush, uint8_t instr, uint8_t rw, uint8_t go, uint8_t ex) +static inline int dsp563xx_once_ir_exec(struct jtag_tap *tap, int flush, uint8_t instr, + uint8_t rw, uint8_t go, uint8_t ex) { int err; diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c index a50f2cd47..c74a41846 100644 --- a/src/target/dsp5680xx.c +++ b/src/target/dsp5680xx.c @@ -1731,7 +1731,12 @@ static int dsp5680xx_f_ex(struct target *t, uint16_t c, uint32_t a, uint32_t d, } /** - * Prior to the execution of any Flash module command, the Flash module Clock Divider (CLKDIV) register must be initialized. The values of this register determine the speed of the internal Flash Clock (FCLK). FCLK must be in the range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. (Running FCLK too slowly wears out the module, while running it too fast under programs Flash leading to bit errors.) + * Prior to the execution of any Flash module command, the Flash module Clock + * Divider (CLKDIV) register must be initialized. The values of this register + * determine the speed of the internal Flash Clock (FCLK). FCLK must be in the + * range of 150kHz ≤ FCLK ≤ 200kHz for proper operation of the Flash module. + * (Running FCLK too slowly wears out the module, while running it too fast + * under programs Flash leading to bit errors.) * * @param target * @@ -1787,7 +1792,11 @@ static int set_fm_ck_div(struct target *target) } /** - * Executes the FM calculate signature command. The FM will calculate over the data from @address to @address + @words -1. The result is written to a register, then read out by this function and returned in @signature. The value @signature may be compared to the the one returned by perl_crc to verify the flash was written correctly. + * Executes the FM calculate signature command. The FM will calculate over the + * data from @address to @address + @words -1. The result is written to a + * register, then read out by this function and returned in @signature. The + * value @signature may be compared to the the one returned by perl_crc to + * verify the flash was written correctly. * * @param target * @param address Start of flash array where the signature should be calculated. |